1 /*- 2 * Copyright (c) 1998 - 2005 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_ata.h" 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/endian.h> 37 #include <sys/ata.h> 38 #include <sys/conf.h> 39 #include <sys/ctype.h> 40 #include <sys/bus.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/bus.h> 45 #include <sys/rman.h> 46 #include <dev/ata/ata-all.h> 47 #include <dev/ata/ata-commands.h> 48 #include <dev/ata/ata-pci.h> 49 #include <ata_if.h> 50 51 /* prototypes */ 52 static int ata_begin_transaction(struct ata_request *); 53 static int ata_end_transaction(struct ata_request *); 54 static void ata_generic_reset(struct ata_channel *); 55 static int ata_wait(struct ata_channel *ch, struct ata_device *, u_int8_t); 56 static void ata_pio_read(struct ata_request *, int); 57 static void ata_pio_write(struct ata_request *, int); 58 static void bswap(int8_t *, int); 59 static void btrim(int8_t *, int); 60 static void bpack(int8_t *, int8_t *, int); 61 62 /* get device parameter page from device */ 63 int 64 ata_getparam(device_t parent, struct ata_device *atadev, u_int8_t command) 65 { 66 struct ata_channel *ch = device_get_softc(parent); 67 int error = 0, retry = 0; 68 69 do { 70 if (retry++ > 4) { 71 if (bootverbose) 72 printf("ata%d-%s: %s-identify retries exceeded\n", ch->unit, 73 atadev->unit == ATA_MASTER ? "master" : "slave", 74 command == ATA_ATAPI_IDENTIFY ? "ATAPI" : "ATA"); 75 error = ENXIO; 76 break; 77 } 78 79 /* select device */ 80 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 81 82 /* disable interrupt */ 83 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_4BIT | ATA_A_IDS); 84 85 /* ready to issue command ? */ 86 if ((error = ata_wait(ch, atadev, 0)) < 0) { 87 printf("ata%d-%s: timeout sending %s-identify error=%d\n", 88 device_get_unit(parent), 89 atadev->unit == ATA_MASTER ? "master" : "slave", 90 command == ATA_ATAPI_IDENTIFY ? "ATAPI" : "ATA", error); 91 error = ENXIO; 92 break; 93 } 94 95 /* select device */ 96 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 97 98 /* issue command */ 99 ATA_IDX_OUTB(ch, ATA_CMD, command); 100 101 } while (ata_wait(ch, atadev, ATA_S_DRQ)); 102 103 if (!error) { 104 ATA_IDX_INSW_STRM(ch, ATA_DATA, (void *)&atadev->param, 105 sizeof(struct ata_params)/sizeof(int16_t)); 106 ATA_IDX_INB(ch, ATA_STATUS); 107 } 108 109 if (!error && (isprint(atadev->param.model[0]) || 110 isprint(atadev->param.model[1]))) { 111 struct ata_params *atacap = &atadev->param; 112 #if BYTE_ORDER == BIG_ENDIAN 113 int16_t *ptr; 114 115 for (ptr = (int16_t *)atacap; 116 ptr < (int16_t *)atacap + sizeof(struct ata_params)/2; ptr++) { 117 *ptr = bswap16(*ptr); 118 } 119 #endif 120 if (!(!strncmp(atacap->model, "FX", 2) || 121 !strncmp(atacap->model, "NEC", 3) || 122 !strncmp(atacap->model, "Pioneer", 7) || 123 !strncmp(atacap->model, "SHARP", 5))) { 124 bswap(atacap->model, sizeof(atacap->model)); 125 bswap(atacap->revision, sizeof(atacap->revision)); 126 bswap(atacap->serial, sizeof(atacap->serial)); 127 } 128 btrim(atacap->model, sizeof(atacap->model)); 129 bpack(atacap->model, atacap->model, sizeof(atacap->model)); 130 btrim(atacap->revision, sizeof(atacap->revision)); 131 bpack(atacap->revision, atacap->revision, sizeof(atacap->revision)); 132 btrim(atacap->serial, sizeof(atacap->serial)); 133 bpack(atacap->serial, atacap->serial, sizeof(atacap->serial)); 134 if (bootverbose) 135 printf("ata%d-%s: pio=%s wdma=%s udma=%s cable=%s wire\n", 136 ch->unit, atadev->unit == ATA_MASTER ? "master":"slave", 137 ata_mode2str(ata_pmode(atacap)), 138 ata_mode2str(ata_wmode(atacap)), 139 ata_mode2str(ata_umode(atacap)), 140 (atacap->hwres & ATA_CABLE_ID) ? "80":"40"); 141 } 142 else { 143 if (!error) 144 error = ENXIO; 145 } 146 147 return error; 148 } 149 150 /* 151 * low level ATA functions 152 */ 153 void 154 ata_generic_hw(struct ata_channel *ch) 155 { 156 ch->hw.begin_transaction = ata_begin_transaction; 157 ch->hw.end_transaction = ata_end_transaction; 158 ch->hw.reset = ata_generic_reset; 159 ch->hw.command = ata_generic_command; 160 } 161 162 /* must be called with ATA channel locked */ 163 static int 164 ata_begin_transaction(struct ata_request *request) 165 { 166 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 167 struct ata_device *atadev = device_get_softc(request->dev); 168 169 ATA_DEBUG_RQ(request, "begin transaction"); 170 171 /* disable ATAPI DMA writes if HW doesn't support it */ 172 if ((ch->flags & ATA_ATAPI_DMA_RO) && 173 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 174 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 175 request->flags &= ~ATA_R_DMA; 176 177 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 178 179 /* ATA PIO data transfer and control commands */ 180 default: 181 { 182 /* record command direction here as our request might be gone later */ 183 int write = (request->flags & ATA_R_WRITE); 184 185 /* issue command */ 186 if (ch->hw.command(atadev, request->u.ata.command, 187 request->u.ata.lba, request->u.ata.count, 188 request->u.ata.feature)) { 189 device_printf(request->dev, "error issueing %s command\n", 190 ata_cmd2str(request)); 191 request->result = EIO; 192 break; 193 } 194 195 /* device reset doesn't interrupt */ 196 if (request->u.ata.command == ATA_DEVICE_RESET) { 197 int timeout = 1000000; 198 do { 199 DELAY(10); 200 request->status = ATA_IDX_INB(ch, ATA_STATUS); 201 } while (request->status & ATA_S_BUSY && timeout--); 202 if (request->status & ATA_S_ERROR) 203 request->error = ATA_IDX_INB(ch, ATA_ERROR); 204 break; 205 } 206 207 /* if write command output the data */ 208 if (write) { 209 if (ata_wait(ch, atadev, 210 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 211 device_printf(request->dev,"timeout waiting for write DRQ"); 212 request->result = EIO; 213 break; 214 } 215 ata_pio_write(request, request->transfersize); 216 } 217 } 218 return ATA_OP_CONTINUES; 219 220 /* ATA DMA data transfer commands */ 221 case ATA_R_DMA: 222 /* check sanity, setup SG list and DMA engine */ 223 if (ch->dma->load(atadev, request->data, request->bytecount, 224 request->flags & ATA_R_READ)) { 225 device_printf(request->dev, "setting up DMA failed\n"); 226 request->result = EIO; 227 break; 228 } 229 230 /* issue command */ 231 if (ch->hw.command(atadev, request->u.ata.command, 232 request->u.ata.lba, request->u.ata.count, 233 request->u.ata.feature)) { 234 device_printf(request->dev, "error issueing %s command\n", 235 ata_cmd2str(request)); 236 request->result = EIO; 237 break; 238 } 239 240 /* start DMA engine */ 241 if (ch->dma->start(ch)) { 242 device_printf(request->dev, "error starting DMA\n"); 243 request->result = EIO; 244 break; 245 } 246 return ATA_OP_CONTINUES; 247 248 /* ATAPI PIO commands */ 249 case ATA_R_ATAPI: 250 /* is this just a POLL DSC command ? */ 251 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 252 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 253 DELAY(10); 254 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC)) 255 request->result = EBUSY; 256 break; 257 } 258 259 /* start ATAPI operation */ 260 if (ch->hw.command(atadev, ATA_PACKET_CMD, 261 request->transfersize << 8, 0, 0)) { 262 device_printf(request->dev, "error issuing ATA PACKET command\n"); 263 request->result = EIO; 264 break; 265 } 266 267 /* command interrupt device ? just return and wait for interrupt */ 268 if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR) 269 return ATA_OP_CONTINUES; 270 271 /* wait for ready to write ATAPI command block */ 272 { 273 int timeout = 5000; /* might be less for fast devices */ 274 while (timeout--) { 275 int reason = ATA_IDX_INB(ch, ATA_IREASON); 276 int status = ATA_IDX_INB(ch, ATA_STATUS); 277 278 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 279 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 280 break; 281 DELAY(20); 282 } 283 if (timeout <= 0) { 284 device_printf(request->dev,"timeout waiting for ATAPI ready\n"); 285 request->result = EIO; 286 break; 287 } 288 } 289 290 /* this seems to be needed for some (slow) devices */ 291 DELAY(10); 292 293 /* output actual command block */ 294 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 295 (int16_t *)request->u.atapi.ccb, 296 (atadev->param.config & ATA_PROTO_MASK) == 297 ATA_PROTO_ATAPI_12 ? 6 : 8); 298 return ATA_OP_CONTINUES; 299 300 case ATA_R_ATAPI|ATA_R_DMA: 301 /* is this just a POLL DSC command ? */ 302 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 303 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 304 DELAY(10); 305 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC)) 306 request->result = EBUSY; 307 break; 308 } 309 310 /* check sanity, setup SG list and DMA engine */ 311 if (ch->dma->load(atadev, request->data, request->bytecount, 312 request->flags & ATA_R_READ)) { 313 device_printf(request->dev, "setting up DMA failed\n"); 314 request->result = EIO; 315 break; 316 } 317 318 /* start ATAPI operation */ 319 if (ch->hw.command(atadev, ATA_PACKET_CMD, 0, 0, ATA_F_DMA)) { 320 device_printf(request->dev, "error issuing ATAPI packet command\n"); 321 request->result = EIO; 322 break; 323 } 324 325 /* wait for ready to write ATAPI command block */ 326 { 327 int timeout = 5000; /* might be less for fast devices */ 328 while (timeout--) { 329 int reason = ATA_IDX_INB(ch, ATA_IREASON); 330 int status = ATA_IDX_INB(ch, ATA_STATUS); 331 332 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 333 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 334 break; 335 DELAY(20); 336 } 337 if (timeout <= 0) { 338 device_printf(request->dev,"timeout waiting for ATAPI ready\n"); 339 request->result = EIO; 340 break; 341 } 342 } 343 344 /* this seems to be needed for some (slow) devices */ 345 DELAY(10); 346 347 /* output actual command block */ 348 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 349 (int16_t *)request->u.atapi.ccb, 350 (atadev->param.config & ATA_PROTO_MASK) == 351 ATA_PROTO_ATAPI_12 ? 6 : 8); 352 353 /* start DMA engine */ 354 if (ch->dma->start(ch)) { 355 request->result = EIO; 356 break; 357 } 358 return ATA_OP_CONTINUES; 359 } 360 361 /* request finish here */ 362 if (ch->dma && ch->dma->flags & ATA_DMA_LOADED) 363 ch->dma->unload(ch); 364 return ATA_OP_FINISHED; 365 } 366 367 static int 368 ata_end_transaction(struct ata_request *request) 369 { 370 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 371 struct ata_device *atadev = device_get_softc(request->dev); 372 int length; 373 374 ATA_DEBUG_RQ(request, "end transaction"); 375 376 /* clear interrupt and get status */ 377 request->status = ATA_IDX_INB(ch, ATA_STATUS); 378 379 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 380 381 /* ATA PIO data transfer and control commands */ 382 default: 383 384 /* on timeouts we have no data or anything so just return */ 385 if (request->flags & ATA_R_TIMEOUT) 386 //return ATA_OP_FINISHED; 387 break; 388 389 /* on control commands read back registers to the request struct */ 390 if (request->flags & ATA_R_CONTROL) { 391 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 392 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 393 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 394 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 395 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0x0f) << 24); 396 } 397 398 /* if we got an error we are done with the HW */ 399 if (request->status & ATA_S_ERROR) { 400 request->error = ATA_IDX_INB(ch, ATA_ERROR); 401 //return ATA_OP_FINISHED; 402 break; 403 } 404 405 /* are we moving data ? */ 406 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 407 408 /* if read data get it */ 409 if (request->flags & ATA_R_READ) { 410 if (ata_wait(ch, atadev, 411 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 412 device_printf(request->dev, "timeout waiting for read DRQ"); 413 request->result = EIO; 414 //return ATA_OP_FINISHED; 415 break; 416 } 417 ata_pio_read(request, request->transfersize); 418 } 419 420 /* update how far we've gotten */ 421 request->donecount += request->transfersize; 422 423 /* do we need a scoop more ? */ 424 if (request->bytecount > request->donecount) { 425 426 /* set this transfer size according to HW capabilities */ 427 request->transfersize = 428 min((request->bytecount - request->donecount), 429 request->transfersize); 430 431 /* if data write command, output the data */ 432 if (request->flags & ATA_R_WRITE) { 433 434 /* if we get an error here we are done with the HW */ 435 if (ata_wait(ch, atadev, 436 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 437 device_printf(request->dev, 438 "timeout waiting for write DRQ"); 439 request->status = ATA_IDX_INB(ch, ATA_STATUS); 440 //return ATA_OP_FINISHED; 441 break; 442 } 443 444 /* output data and return waiting for new interrupt */ 445 ata_pio_write(request, request->transfersize); 446 return ATA_OP_CONTINUES; 447 } 448 449 /* if data read command, return & wait for interrupt */ 450 if (request->flags & ATA_R_READ) 451 return ATA_OP_CONTINUES; 452 } 453 } 454 /* done with HW */ 455 //return ATA_OP_FINISHED; 456 break; 457 458 /* ATA DMA data transfer commands */ 459 case ATA_R_DMA: 460 461 /* stop DMA engine and get status */ 462 if (ch->dma->stop) 463 request->dmastat = ch->dma->stop(ch); 464 465 /* did we get error or data */ 466 if (request->status & ATA_S_ERROR) 467 request->error = ATA_IDX_INB(ch, ATA_ERROR); 468 else if (request->dmastat & ATA_BMSTAT_ERROR) 469 request->status |= ATA_S_ERROR; 470 else if (!(request->flags & ATA_R_TIMEOUT)) 471 request->donecount = request->bytecount; 472 473 /* release SG list etc */ 474 ch->dma->unload(ch); 475 476 /* done with HW */ 477 //return ATA_OP_FINISHED; 478 break; 479 480 /* ATAPI PIO commands */ 481 case ATA_R_ATAPI: 482 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 483 484 /* on timeouts we have no data or anything so just return */ 485 if (request->flags & ATA_R_TIMEOUT) 486 //return ATA_OP_FINISHED; 487 break; 488 489 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 490 (request->status & ATA_S_DRQ)) { 491 492 case ATAPI_P_CMDOUT: 493 /* this seems to be needed for some (slow) devices */ 494 DELAY(10); 495 496 if (!(request->status & ATA_S_DRQ)) { 497 device_printf(request->dev, "command interrupt without DRQ\n"); 498 request->status = ATA_S_ERROR; 499 //return ATA_OP_FINISHED; 500 break; 501 } 502 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 503 (atadev->param.config & 504 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); 505 /* return wait for interrupt */ 506 return ATA_OP_CONTINUES; 507 508 case ATAPI_P_WRITE: 509 if (request->flags & ATA_R_READ) { 510 request->status = ATA_S_ERROR; 511 device_printf(request->dev, 512 "%s trying to write on read buffer\n", 513 ata_cmd2str(request)); 514 //return ATA_OP_FINISHED; 515 break; 516 } 517 ata_pio_write(request, length); 518 request->donecount += length; 519 520 /* set next transfer size according to HW capabilities */ 521 request->transfersize = min((request->bytecount-request->donecount), 522 request->transfersize); 523 /* return wait for interrupt */ 524 return ATA_OP_CONTINUES; 525 526 case ATAPI_P_READ: 527 if (request->flags & ATA_R_WRITE) { 528 request->status = ATA_S_ERROR; 529 device_printf(request->dev, 530 "%s trying to read on write buffer\n", 531 ata_cmd2str(request)); 532 //return ATA_OP_FINISHED; 533 break; 534 } 535 ata_pio_read(request, length); 536 request->donecount += length; 537 538 /* set next transfer size according to HW capabilities */ 539 request->transfersize = min((request->bytecount-request->donecount), 540 request->transfersize); 541 /* return wait for interrupt */ 542 return ATA_OP_CONTINUES; 543 544 case ATAPI_P_DONEDRQ: 545 device_printf(request->dev, 546 "WARNING - %s DONEDRQ non conformant device\n", 547 ata_cmd2str(request)); 548 if (request->flags & ATA_R_READ) { 549 ata_pio_read(request, length); 550 request->donecount += length; 551 } 552 else if (request->flags & ATA_R_WRITE) { 553 ata_pio_write(request, length); 554 request->donecount += length; 555 } 556 else 557 request->status = ATA_S_ERROR; 558 /* FALLTHROUGH */ 559 560 case ATAPI_P_ABORT: 561 case ATAPI_P_DONE: 562 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 563 request->error = ATA_IDX_INB(ch, ATA_ERROR); 564 //return ATA_OP_FINISHED; 565 break; 566 567 default: 568 device_printf(request->dev, "unknown transfer phase\n"); 569 request->status = ATA_S_ERROR; 570 } 571 572 /* done with HW */ 573 //return ATA_OP_FINISHED; 574 break; 575 576 /* ATAPI DMA commands */ 577 case ATA_R_ATAPI|ATA_R_DMA: 578 579 /* stop the engine and get engine status */ 580 if (ch->dma->stop) 581 request->dmastat = ch->dma->stop(ch); 582 583 /* did we get error or data */ 584 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 585 request->error = ATA_IDX_INB(ch, ATA_ERROR); 586 else if (request->dmastat & ATA_BMSTAT_ERROR) 587 request->status |= ATA_S_ERROR; 588 else if (!(request->flags & ATA_R_TIMEOUT)) 589 request->donecount = request->bytecount; 590 591 /* release SG list etc */ 592 ch->dma->unload(ch); 593 594 /* done with HW */ 595 //return ATA_OP_FINISHED; 596 break; 597 } 598 599 /* disable interrupt */ 600 //ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_4BIT | ATA_A_IDS); 601 602 return ATA_OP_FINISHED; 603 } 604 605 /* must be called with ATA channel locked */ 606 static void 607 ata_generic_reset(struct ata_channel *ch) 608 { 609 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0; 610 u_int8_t err = 0, lsb = 0, msb = 0; 611 int mask = 0, timeout; 612 613 /* if DMA functionality present stop it */ 614 if (ch->dma) { 615 if (ch->dma->stop) 616 ch->dma->stop(ch); 617 if (ch->dma->flags & ATA_DMA_LOADED) 618 ch->dma->unload(ch); 619 } 620 621 /* reset host end of channel (if supported) */ 622 ATA_RESET(device_get_parent(ch->dev), ch->dev); 623 624 /* do we have any signs of ATA/ATAPI HW being present ? */ 625 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER); 626 DELAY(10); 627 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 628 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 629 stat0 = ATA_S_BUSY; 630 mask |= 0x01; 631 } 632 633 /* in some setups we dont want to test for a slave */ 634 if (!(ch->flags & ATA_NO_SLAVE)) { 635 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_SLAVE); 636 DELAY(10); 637 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 638 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 639 stat1 = ATA_S_BUSY; 640 mask |= 0x02; 641 } 642 } 643 644 if (bootverbose) 645 device_printf(ch->dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 646 mask, ostat0, ostat1); 647 648 /* if nothing showed up there is no need to get any further */ 649 /* SOS is that too strong?, we just might loose devices here XXX */ 650 ch->devices = 0; 651 if (!mask) 652 return; 653 654 /* reset (both) devices on this channel */ 655 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER); 656 DELAY(10); 657 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS | ATA_A_RESET); 658 ata_udelay(10000); 659 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS); 660 ata_udelay(100000); 661 ATA_IDX_INB(ch, ATA_ERROR); 662 663 /* wait for BUSY to go inactive */ 664 for (timeout = 0; timeout < 310; timeout++) { 665 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) { 666 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 667 DELAY(10); 668 err = ATA_IDX_INB(ch, ATA_ERROR); 669 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 670 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 671 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 672 if (bootverbose) 673 device_printf(ch->dev, 674 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 675 stat0, err, lsb, msb); 676 if (stat0 == err && lsb == err && msb == err && timeout > 10) 677 mask &= ~0x01; 678 if (!(stat0 & ATA_S_BUSY)) { 679 if ((err & 0x7f) == ATA_E_ILI) { 680 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 681 ch->devices |= ATA_ATAPI_MASTER; 682 } 683 else if (stat0 & ATA_S_READY) { 684 ch->devices |= ATA_ATA_MASTER; 685 } 686 } 687 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 688 stat0 |= ATA_S_BUSY; 689 } 690 } 691 } 692 693 if ((mask & 0x02) && (stat1 & ATA_S_BUSY)) { 694 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 695 DELAY(10); 696 err = ATA_IDX_INB(ch, ATA_ERROR); 697 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 698 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 699 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 700 if (bootverbose) 701 device_printf(ch->dev, 702 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 703 stat1, err, lsb, msb); 704 if (stat1 == err && lsb == err && msb == err && timeout > 10) 705 mask &= ~0x02; 706 if (!(stat1 & ATA_S_BUSY)) { 707 if ((err & 0x7f) == ATA_E_ILI) { 708 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 709 ch->devices |= ATA_ATAPI_SLAVE; 710 } 711 else if (stat1 & ATA_S_READY) { 712 ch->devices |= ATA_ATA_SLAVE; 713 } 714 } 715 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 716 stat0 |= ATA_S_BUSY; 717 } 718 } 719 } 720 721 if (mask == 0x00) /* nothing to wait for */ 722 break; 723 if (mask == 0x01) /* wait for master only */ 724 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10)) 725 break; 726 if (mask == 0x02) /* wait for slave only */ 727 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10)) 728 break; 729 if (mask == 0x03) { /* wait for both master & slave */ 730 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 731 break; 732 if ((stat0 == 0xff) && (timeout > 20)) 733 mask &= ~0x01; 734 if ((stat1 == 0xff) && (timeout > 20)) 735 mask &= ~0x02; 736 } 737 ata_udelay(100000); 738 } 739 740 if (bootverbose) 741 device_printf(ch->dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n", 742 stat0, stat1, ch->devices, 743 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 744 } 745 746 static int 747 ata_wait(struct ata_channel *ch, struct ata_device *atadev, u_int8_t mask) 748 { 749 u_int8_t status; 750 int timeout = 0; 751 752 DELAY(1); 753 754 /* wait 5 seconds for device to get !BUSY */ 755 while (timeout < 5000000) { 756 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 757 758 /* if drive fails status, reselect the drive and try again */ 759 if (status == 0xff) { 760 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 761 timeout += 1000; 762 DELAY(1000); 763 continue; 764 } 765 766 /* are we done ? */ 767 if (!(status & ATA_S_BUSY)) 768 break; 769 770 if (timeout > 1000) { 771 timeout += 1000; 772 DELAY(1000); 773 } 774 else { 775 timeout += 10; 776 DELAY(10); 777 } 778 } 779 if (timeout >= 5000000) 780 return -2; 781 if (!mask) 782 return (status & ATA_S_ERROR); 783 784 DELAY(1); 785 786 /* wait 50 msec for bits wanted */ 787 timeout = 5000; 788 while (timeout--) { 789 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 790 if ((status & mask) == mask) 791 return (status & ATA_S_ERROR); 792 DELAY(10); 793 } 794 return -3; 795 } 796 797 int 798 ata_generic_command(struct ata_device *atadev, u_int8_t command, 799 u_int64_t lba, u_int16_t count, u_int16_t feature) 800 { 801 struct ata_channel *ch = device_get_softc(device_get_parent(atadev->dev)); 802 803 /* select device */ 804 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 805 806 /* ready to issue command ? */ 807 if (ata_wait(ch, atadev, 0) < 0) { 808 device_printf(atadev->dev, "timeout sending command=%02x\n", command); 809 return -1; 810 } 811 812 /* enable interrupt */ 813 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_4BIT); 814 815 /* only use 48bit addressing if needed (avoid bugs and overhead) */ 816 if ((lba >= ATA_MAX_28BIT_LBA || count > 256) && 817 atadev->param.support.command2 & ATA_SUPPORT_ADDRESS48) { 818 819 /* translate command into 48bit version */ 820 switch (command) { 821 case ATA_READ: 822 command = ATA_READ48; break; 823 case ATA_READ_MUL: 824 command = ATA_READ_MUL48; break; 825 case ATA_READ_DMA: 826 command = ATA_READ_DMA48; break; 827 case ATA_READ_DMA_QUEUED: 828 command = ATA_READ_DMA_QUEUED48; break; 829 case ATA_WRITE: 830 command = ATA_WRITE48; break; 831 case ATA_WRITE_MUL: 832 command = ATA_WRITE_MUL48; break; 833 case ATA_WRITE_DMA: 834 command = ATA_WRITE_DMA48; break; 835 case ATA_WRITE_DMA_QUEUED: 836 command = ATA_WRITE_DMA_QUEUED48; break; 837 case ATA_FLUSHCACHE: 838 command = ATA_FLUSHCACHE48; break; 839 default: 840 device_printf(atadev->dev,"can't translate cmd to 48bit version\n"); 841 return -1; 842 } 843 ATA_IDX_OUTB(ch, ATA_FEATURE, (feature>>8) & 0xff); 844 ATA_IDX_OUTB(ch, ATA_FEATURE, feature & 0xff); 845 ATA_IDX_OUTB(ch, ATA_COUNT, (count>>8) & 0xff); 846 ATA_IDX_OUTB(ch, ATA_COUNT, count & 0xff); 847 ATA_IDX_OUTB(ch, ATA_SECTOR, (lba>>24) & 0xff); 848 ATA_IDX_OUTB(ch, ATA_SECTOR, lba & 0xff); 849 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (lba>>32) & 0xff); 850 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (lba>>8) & 0xff); 851 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (lba>>40) & 0xff); 852 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (lba>>16) & 0xff); 853 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit); 854 ch->flags |= ATA_48BIT_ACTIVE; 855 } 856 else { 857 ATA_IDX_OUTB(ch, ATA_FEATURE, feature); 858 ATA_IDX_OUTB(ch, ATA_COUNT, count); 859 if (atadev->flags & ATA_D_USE_CHS) { 860 int heads, sectors; 861 862 if (atadev->param.atavalid & ATA_FLAG_54_58) { 863 heads = atadev->param.current_heads; 864 sectors = atadev->param.current_sectors; 865 } 866 else { 867 heads = atadev->param.heads; 868 sectors = atadev->param.sectors; 869 } 870 ATA_IDX_OUTB(ch, ATA_SECTOR, (lba % sectors) + 1); 871 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (lba / (sectors * heads))); 872 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (lba / (sectors * heads)) >> 8); 873 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit | 874 (((lba % (sectors * heads)) / sectors) & 0xf)); 875 } 876 else { 877 ATA_IDX_OUTB(ch, ATA_SECTOR, lba & 0xff); 878 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (lba>>8) & 0xff); 879 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (lba>>16) & 0xff); 880 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit | 881 ((lba>>24) & 0x0f)); 882 } 883 ch->flags &= ~ATA_48BIT_ACTIVE; 884 } 885 886 /* issue command to controller */ 887 ATA_IDX_OUTB(ch, ATA_CMD, command); 888 889 return 0; 890 } 891 892 static void 893 ata_pio_read(struct ata_request *request, int length) 894 { 895 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 896 int size = min(request->transfersize, length); 897 int resid; 898 899 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 900 ATA_IDX_INSW_STRM(ch, ATA_DATA, 901 (void*)((uintptr_t)request->data+request->donecount), 902 size / sizeof(int16_t)); 903 else 904 ATA_IDX_INSL_STRM(ch, ATA_DATA, 905 (void*)((uintptr_t)request->data+request->donecount), 906 size / sizeof(int32_t)); 907 908 if (request->transfersize < length) { 909 device_printf(request->dev, "WARNING - %s read data overrun %d>%d\n", 910 ata_cmd2str(request), length, request->transfersize); 911 for (resid = request->transfersize; resid < length; 912 resid += sizeof(int16_t)) 913 ATA_IDX_INW(ch, ATA_DATA); 914 } 915 } 916 917 static void 918 ata_pio_write(struct ata_request *request, int length) 919 { 920 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 921 int size = min(request->transfersize, length); 922 int resid; 923 924 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 925 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 926 (void*)((uintptr_t)request->data+request->donecount), 927 size / sizeof(int16_t)); 928 else 929 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 930 (void*)((uintptr_t)request->data+request->donecount), 931 size / sizeof(int32_t)); 932 933 if (request->transfersize < length) { 934 device_printf(request->dev, "WARNING - %s write data underrun %d>%d\n", 935 ata_cmd2str(request), length, request->transfersize); 936 for (resid = request->transfersize; resid < length; 937 resid += sizeof(int16_t)) 938 ATA_IDX_OUTW(ch, ATA_DATA, 0); 939 } 940 } 941 942 static void 943 bswap(int8_t *buf, int len) 944 { 945 u_int16_t *ptr = (u_int16_t*)(buf + len); 946 947 while (--ptr >= (u_int16_t*)buf) 948 *ptr = ntohs(*ptr); 949 } 950 951 static void 952 btrim(int8_t *buf, int len) 953 { 954 int8_t *ptr; 955 956 for (ptr = buf; ptr < buf+len; ++ptr) 957 if (!*ptr || *ptr == '_') 958 *ptr = ' '; 959 for (ptr = buf + len - 1; ptr >= buf && *ptr == ' '; --ptr) 960 *ptr = 0; 961 } 962 963 static void 964 bpack(int8_t *src, int8_t *dst, int len) 965 { 966 int i, j, blank; 967 968 for (i = j = blank = 0 ; i < len; i++) { 969 if (blank && src[i] == ' ') continue; 970 if (blank && src[i] != ' ') { 971 dst[j++] = src[i]; 972 blank = 0; 973 continue; 974 } 975 if (src[i] == ' ') { 976 blank = 1; 977 if (i == 0) 978 continue; 979 } 980 dst[j++] = src[i]; 981 } 982 if (j < len) 983 dst[j] = 0x00; 984 } 985