1 /*- 2 * Copyright (c) 1998 - 2005 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_ata.h" 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/endian.h> 37 #include <sys/ata.h> 38 #include <sys/conf.h> 39 #include <sys/ctype.h> 40 #include <sys/bus.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/bus.h> 45 #include <sys/rman.h> 46 #include <dev/ata/ata-all.h> 47 #include <dev/ata/ata-commands.h> 48 #include <dev/ata/ata-pci.h> 49 #include <ata_if.h> 50 51 /* prototypes */ 52 static int ata_begin_transaction(struct ata_request *); 53 static int ata_end_transaction(struct ata_request *); 54 static void ata_generic_reset(struct ata_channel *); 55 static int ata_wait(struct ata_channel *ch, struct ata_device *, u_int8_t); 56 static void ata_pio_read(struct ata_request *, int); 57 static void ata_pio_write(struct ata_request *, int); 58 static void bswap(int8_t *, int); 59 static void btrim(int8_t *, int); 60 static void bpack(int8_t *, int8_t *, int); 61 62 /* get device parameter page from device */ 63 int 64 ata_getparam(device_t parent, struct ata_device *atadev, u_int8_t command) 65 { 66 struct ata_channel *ch = device_get_softc(parent); 67 int error = 0, retry = 0; 68 69 do { 70 if (retry++ > 4) { 71 if (bootverbose) 72 printf("ata%d-%s: %s-identify retries exceeded\n", ch->unit, 73 atadev->unit == ATA_MASTER ? "master" : "slave", 74 command == ATA_ATAPI_IDENTIFY ? "ATAPI" : "ATA"); 75 error = ENXIO; 76 break; 77 } 78 79 /* select device */ 80 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 81 82 /* wait a bit to let slow devices settle */ 83 DELAY(100); 84 85 /* disable interrupt */ 86 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_IDS); 87 88 /* ready to issue command ? */ 89 if ((error = ata_wait(ch, atadev, 0)) < 0) { 90 printf("ata%d-%s: timeout sending %s-identify error=%d\n", 91 device_get_unit(parent), 92 atadev->unit == ATA_MASTER ? "master" : "slave", 93 command == ATA_ATAPI_IDENTIFY ? "ATAPI" : "ATA", error); 94 error = ENXIO; 95 break; 96 } 97 98 /* select device */ 99 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 100 101 /* issue command */ 102 ATA_IDX_OUTB(ch, ATA_COMMAND, command); 103 104 } while (ata_wait(ch, atadev, ATA_S_DRQ)); 105 106 if (!error) { 107 ATA_IDX_INSW_STRM(ch, ATA_DATA, (void *)&atadev->param, 108 sizeof(struct ata_params)/sizeof(int16_t)); 109 ATA_IDX_INB(ch, ATA_STATUS); 110 } 111 112 if (!error && (isprint(atadev->param.model[0]) || 113 isprint(atadev->param.model[1]))) { 114 struct ata_params *atacap = &atadev->param; 115 #if BYTE_ORDER == BIG_ENDIAN 116 int16_t *ptr; 117 118 for (ptr = (int16_t *)atacap; 119 ptr < (int16_t *)atacap + sizeof(struct ata_params)/2; ptr++) { 120 *ptr = bswap16(*ptr); 121 } 122 #endif 123 if (!(!strncmp(atacap->model, "FX", 2) || 124 !strncmp(atacap->model, "NEC", 3) || 125 !strncmp(atacap->model, "Pioneer", 7) || 126 !strncmp(atacap->model, "SHARP", 5))) { 127 bswap(atacap->model, sizeof(atacap->model)); 128 bswap(atacap->revision, sizeof(atacap->revision)); 129 bswap(atacap->serial, sizeof(atacap->serial)); 130 } 131 btrim(atacap->model, sizeof(atacap->model)); 132 bpack(atacap->model, atacap->model, sizeof(atacap->model)); 133 btrim(atacap->revision, sizeof(atacap->revision)); 134 bpack(atacap->revision, atacap->revision, sizeof(atacap->revision)); 135 btrim(atacap->serial, sizeof(atacap->serial)); 136 bpack(atacap->serial, atacap->serial, sizeof(atacap->serial)); 137 if (bootverbose) 138 printf("ata%d-%s: pio=%s wdma=%s udma=%s cable=%s wire\n", 139 ch->unit, atadev->unit == ATA_MASTER ? "master":"slave", 140 ata_mode2str(ata_pmode(atacap)), 141 ata_mode2str(ata_wmode(atacap)), 142 ata_mode2str(ata_umode(atacap)), 143 (atacap->hwres & ATA_CABLE_ID) ? "80":"40"); 144 } 145 else { 146 if (!error) 147 error = ENXIO; 148 } 149 150 return error; 151 } 152 153 /* 154 * low level ATA functions 155 */ 156 void 157 ata_generic_hw(struct ata_channel *ch) 158 { 159 ch->hw.begin_transaction = ata_begin_transaction; 160 ch->hw.end_transaction = ata_end_transaction; 161 ch->hw.reset = ata_generic_reset; 162 ch->hw.command = ata_generic_command; 163 } 164 165 /* must be called with ATA channel locked */ 166 static int 167 ata_begin_transaction(struct ata_request *request) 168 { 169 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 170 struct ata_device *atadev = device_get_softc(request->dev); 171 172 ATA_DEBUG_RQ(request, "begin transaction"); 173 174 /* disable ATAPI DMA writes if HW doesn't support it */ 175 if ((ch->flags & ATA_ATAPI_DMA_RO) && 176 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 177 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 178 request->flags &= ~ATA_R_DMA; 179 180 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 181 182 /* ATA PIO data transfer and control commands */ 183 default: 184 { 185 /* record command direction here as our request might be gone later */ 186 int write = (request->flags & ATA_R_WRITE); 187 188 /* issue command */ 189 if (ch->hw.command(atadev, request->u.ata.command, 190 request->u.ata.lba, request->u.ata.count, 191 request->u.ata.feature)) { 192 device_printf(request->dev, "error issueing %s command\n", 193 ata_cmd2str(request)); 194 request->result = EIO; 195 break; 196 } 197 198 /* device reset doesn't interrupt */ 199 if (request->u.ata.command == ATA_DEVICE_RESET) { 200 int timeout = 1000000; 201 do { 202 DELAY(10); 203 request->status = ATA_IDX_INB(ch, ATA_STATUS); 204 } while (request->status & ATA_S_BUSY && timeout--); 205 if (request->status & ATA_S_ERROR) 206 request->error = ATA_IDX_INB(ch, ATA_ERROR); 207 break; 208 } 209 210 /* if write command output the data */ 211 if (write) { 212 if (ata_wait(ch, atadev, 213 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 214 device_printf(request->dev,"timeout waiting for write DRQ"); 215 request->result = EIO; 216 break; 217 } 218 ata_pio_write(request, request->transfersize); 219 } 220 } 221 return ATA_OP_CONTINUES; 222 223 /* ATA DMA data transfer commands */ 224 case ATA_R_DMA: 225 /* check sanity, setup SG list and DMA engine */ 226 if (ch->dma->load(atadev, request->data, request->bytecount, 227 request->flags & ATA_R_READ)) { 228 device_printf(request->dev, "setting up DMA failed\n"); 229 request->result = EIO; 230 break; 231 } 232 233 /* issue command */ 234 if (ch->hw.command(atadev, request->u.ata.command, 235 request->u.ata.lba, request->u.ata.count, 236 request->u.ata.feature)) { 237 device_printf(request->dev, "error issueing %s command\n", 238 ata_cmd2str(request)); 239 request->result = EIO; 240 break; 241 } 242 243 /* start DMA engine */ 244 if (ch->dma->start(ch)) { 245 device_printf(request->dev, "error starting DMA\n"); 246 request->result = EIO; 247 break; 248 } 249 return ATA_OP_CONTINUES; 250 251 /* ATAPI PIO commands */ 252 case ATA_R_ATAPI: 253 /* is this just a POLL DSC command ? */ 254 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 255 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 256 DELAY(10); 257 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 258 request->result = EBUSY; 259 break; 260 } 261 262 /* start ATAPI operation */ 263 if (ch->hw.command(atadev, ATA_PACKET_CMD, 264 request->transfersize << 8, 0, 0)) { 265 device_printf(request->dev, "error issuing ATA PACKET command\n"); 266 request->result = EIO; 267 break; 268 } 269 270 /* command interrupt device ? just return and wait for interrupt */ 271 if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR) 272 return ATA_OP_CONTINUES; 273 274 /* wait for ready to write ATAPI command block */ 275 { 276 int timeout = 5000; /* might be less for fast devices */ 277 while (timeout--) { 278 int reason = ATA_IDX_INB(ch, ATA_IREASON); 279 int status = ATA_IDX_INB(ch, ATA_STATUS); 280 281 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 282 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 283 break; 284 DELAY(20); 285 } 286 if (timeout <= 0) { 287 device_printf(request->dev,"timeout waiting for ATAPI ready\n"); 288 request->result = EIO; 289 break; 290 } 291 } 292 293 /* this seems to be needed for some (slow) devices */ 294 DELAY(10); 295 296 /* output actual command block */ 297 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 298 (int16_t *)request->u.atapi.ccb, 299 (atadev->param.config & ATA_PROTO_MASK) == 300 ATA_PROTO_ATAPI_12 ? 6 : 8); 301 return ATA_OP_CONTINUES; 302 303 case ATA_R_ATAPI|ATA_R_DMA: 304 /* is this just a POLL DSC command ? */ 305 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 306 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 307 DELAY(10); 308 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 309 request->result = EBUSY; 310 break; 311 } 312 313 /* check sanity, setup SG list and DMA engine */ 314 if (ch->dma->load(atadev, request->data, request->bytecount, 315 request->flags & ATA_R_READ)) { 316 device_printf(request->dev, "setting up DMA failed\n"); 317 request->result = EIO; 318 break; 319 } 320 321 /* start ATAPI operation */ 322 if (ch->hw.command(atadev, ATA_PACKET_CMD, 0, 0, ATA_F_DMA)) { 323 device_printf(request->dev, "error issuing ATAPI packet command\n"); 324 request->result = EIO; 325 break; 326 } 327 328 /* wait for ready to write ATAPI command block */ 329 { 330 int timeout = 5000; /* might be less for fast devices */ 331 while (timeout--) { 332 int reason = ATA_IDX_INB(ch, ATA_IREASON); 333 int status = ATA_IDX_INB(ch, ATA_STATUS); 334 335 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 336 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 337 break; 338 DELAY(20); 339 } 340 if (timeout <= 0) { 341 device_printf(request->dev,"timeout waiting for ATAPI ready\n"); 342 request->result = EIO; 343 break; 344 } 345 } 346 347 /* this seems to be needed for some (slow) devices */ 348 DELAY(10); 349 350 /* output actual command block */ 351 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 352 (int16_t *)request->u.atapi.ccb, 353 (atadev->param.config & ATA_PROTO_MASK) == 354 ATA_PROTO_ATAPI_12 ? 6 : 8); 355 356 /* start DMA engine */ 357 if (ch->dma->start(ch)) { 358 request->result = EIO; 359 break; 360 } 361 return ATA_OP_CONTINUES; 362 } 363 364 /* request finish here */ 365 if (ch->dma && ch->dma->flags & ATA_DMA_LOADED) 366 ch->dma->unload(ch); 367 return ATA_OP_FINISHED; 368 } 369 370 static int 371 ata_end_transaction(struct ata_request *request) 372 { 373 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 374 struct ata_device *atadev = device_get_softc(request->dev); 375 int length; 376 377 ATA_DEBUG_RQ(request, "end transaction"); 378 379 /* clear interrupt and get status */ 380 request->status = ATA_IDX_INB(ch, ATA_STATUS); 381 382 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 383 384 /* ATA PIO data transfer and control commands */ 385 default: 386 387 /* on timeouts we have no data or anything so just return */ 388 if (request->flags & ATA_R_TIMEOUT) 389 //return ATA_OP_FINISHED; 390 break; 391 392 /* on control commands read back registers to the request struct */ 393 if (request->flags & ATA_R_CONTROL) { 394 if (ch->flags & ATA_48BIT_ACTIVE) { 395 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB); 396 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8); 397 request->u.ata.lba = 398 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) | 399 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) | 400 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40); 401 402 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 403 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT); 404 request->u.ata.lba |= 405 (ATA_IDX_INB(ch, ATA_SECTOR) | 406 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 407 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16)); 408 } 409 else { 410 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 411 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 412 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 413 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 414 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24); 415 } 416 } 417 418 /* if we got an error we are done with the HW */ 419 if (request->status & ATA_S_ERROR) { 420 request->error = ATA_IDX_INB(ch, ATA_ERROR); 421 //return ATA_OP_FINISHED; 422 break; 423 } 424 425 /* are we moving data ? */ 426 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 427 428 /* if read data get it */ 429 if (request->flags & ATA_R_READ) { 430 if (ata_wait(ch, atadev, 431 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 432 device_printf(request->dev, "timeout waiting for read DRQ"); 433 request->result = EIO; 434 //return ATA_OP_FINISHED; 435 break; 436 } 437 ata_pio_read(request, request->transfersize); 438 } 439 440 /* update how far we've gotten */ 441 request->donecount += request->transfersize; 442 443 /* do we need a scoop more ? */ 444 if (request->bytecount > request->donecount) { 445 446 /* set this transfer size according to HW capabilities */ 447 request->transfersize = 448 min((request->bytecount - request->donecount), 449 request->transfersize); 450 451 /* if data write command, output the data */ 452 if (request->flags & ATA_R_WRITE) { 453 454 /* if we get an error here we are done with the HW */ 455 if (ata_wait(ch, atadev, 456 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 457 device_printf(request->dev, 458 "timeout waiting for write DRQ"); 459 request->status = ATA_IDX_INB(ch, ATA_STATUS); 460 //return ATA_OP_FINISHED; 461 break; 462 } 463 464 /* output data and return waiting for new interrupt */ 465 ata_pio_write(request, request->transfersize); 466 return ATA_OP_CONTINUES; 467 } 468 469 /* if data read command, return & wait for interrupt */ 470 if (request->flags & ATA_R_READ) 471 return ATA_OP_CONTINUES; 472 } 473 } 474 /* done with HW */ 475 //return ATA_OP_FINISHED; 476 break; 477 478 /* ATA DMA data transfer commands */ 479 case ATA_R_DMA: 480 481 /* stop DMA engine and get status */ 482 if (ch->dma->stop) 483 request->dmastat = ch->dma->stop(ch); 484 485 /* did we get error or data */ 486 if (request->status & ATA_S_ERROR) 487 request->error = ATA_IDX_INB(ch, ATA_ERROR); 488 else if (request->dmastat & ATA_BMSTAT_ERROR) 489 request->status |= ATA_S_ERROR; 490 else if (!(request->flags & ATA_R_TIMEOUT)) 491 request->donecount = request->bytecount; 492 493 /* release SG list etc */ 494 ch->dma->unload(ch); 495 496 /* done with HW */ 497 //return ATA_OP_FINISHED; 498 break; 499 500 /* ATAPI PIO commands */ 501 case ATA_R_ATAPI: 502 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 503 504 /* on timeouts we have no data or anything so just return */ 505 if (request->flags & ATA_R_TIMEOUT) 506 //return ATA_OP_FINISHED; 507 break; 508 509 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 510 (request->status & ATA_S_DRQ)) { 511 512 case ATAPI_P_CMDOUT: 513 /* this seems to be needed for some (slow) devices */ 514 DELAY(10); 515 516 if (!(request->status & ATA_S_DRQ)) { 517 device_printf(request->dev, "command interrupt without DRQ\n"); 518 request->status = ATA_S_ERROR; 519 //return ATA_OP_FINISHED; 520 break; 521 } 522 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 523 (atadev->param.config & 524 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); 525 /* return wait for interrupt */ 526 return ATA_OP_CONTINUES; 527 528 case ATAPI_P_WRITE: 529 if (request->flags & ATA_R_READ) { 530 request->status = ATA_S_ERROR; 531 device_printf(request->dev, 532 "%s trying to write on read buffer\n", 533 ata_cmd2str(request)); 534 //return ATA_OP_FINISHED; 535 break; 536 } 537 ata_pio_write(request, length); 538 request->donecount += length; 539 540 /* set next transfer size according to HW capabilities */ 541 request->transfersize = min((request->bytecount-request->donecount), 542 request->transfersize); 543 /* return wait for interrupt */ 544 return ATA_OP_CONTINUES; 545 546 case ATAPI_P_READ: 547 if (request->flags & ATA_R_WRITE) { 548 request->status = ATA_S_ERROR; 549 device_printf(request->dev, 550 "%s trying to read on write buffer\n", 551 ata_cmd2str(request)); 552 //return ATA_OP_FINISHED; 553 break; 554 } 555 ata_pio_read(request, length); 556 request->donecount += length; 557 558 /* set next transfer size according to HW capabilities */ 559 request->transfersize = min((request->bytecount-request->donecount), 560 request->transfersize); 561 /* return wait for interrupt */ 562 return ATA_OP_CONTINUES; 563 564 case ATAPI_P_DONEDRQ: 565 device_printf(request->dev, 566 "WARNING - %s DONEDRQ non conformant device\n", 567 ata_cmd2str(request)); 568 if (request->flags & ATA_R_READ) { 569 ata_pio_read(request, length); 570 request->donecount += length; 571 } 572 else if (request->flags & ATA_R_WRITE) { 573 ata_pio_write(request, length); 574 request->donecount += length; 575 } 576 else 577 request->status = ATA_S_ERROR; 578 /* FALLTHROUGH */ 579 580 case ATAPI_P_ABORT: 581 case ATAPI_P_DONE: 582 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 583 request->error = ATA_IDX_INB(ch, ATA_ERROR); 584 //return ATA_OP_FINISHED; 585 break; 586 587 default: 588 device_printf(request->dev, "unknown transfer phase\n"); 589 request->status = ATA_S_ERROR; 590 } 591 592 /* done with HW */ 593 //return ATA_OP_FINISHED; 594 break; 595 596 /* ATAPI DMA commands */ 597 case ATA_R_ATAPI|ATA_R_DMA: 598 599 /* stop the engine and get engine status */ 600 if (ch->dma->stop) 601 request->dmastat = ch->dma->stop(ch); 602 603 /* did we get error or data */ 604 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 605 request->error = ATA_IDX_INB(ch, ATA_ERROR); 606 else if (request->dmastat & ATA_BMSTAT_ERROR) 607 request->status |= ATA_S_ERROR; 608 else if (!(request->flags & ATA_R_TIMEOUT)) 609 request->donecount = request->bytecount; 610 611 /* release SG list etc */ 612 ch->dma->unload(ch); 613 614 /* done with HW */ 615 //return ATA_OP_FINISHED; 616 break; 617 } 618 619 /* disable interrupt */ 620 //ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_IDS); 621 622 return ATA_OP_FINISHED; 623 } 624 625 /* must be called with ATA channel locked */ 626 static void 627 ata_generic_reset(struct ata_channel *ch) 628 { 629 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0; 630 u_int8_t err = 0, lsb = 0, msb = 0; 631 int mask = 0, timeout; 632 633 /* reset controller (host) */ 634 ATA_RESET(ch->dev); 635 636 /* do we have any signs of ATA/ATAPI HW being present ? */ 637 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER); 638 DELAY(10); 639 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 640 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 641 stat0 = ATA_S_BUSY; 642 mask |= 0x01; 643 } 644 645 /* in some setups we dont want to test for a slave */ 646 if (!(ch->flags & ATA_NO_SLAVE)) { 647 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_SLAVE); 648 DELAY(10); 649 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 650 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 651 stat1 = ATA_S_BUSY; 652 mask |= 0x02; 653 } 654 } 655 656 if (bootverbose) 657 device_printf(ch->dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 658 mask, ostat0, ostat1); 659 660 /* if nothing showed up there is no need to get any further */ 661 /* SOS is that too strong?, we just might loose devices here XXX */ 662 ch->devices = 0; 663 if (!mask) 664 return; 665 666 /* reset (both) devices on this channel */ 667 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER); 668 DELAY(10); 669 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 670 ata_udelay(10000); 671 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 672 ata_udelay(100000); 673 ATA_IDX_INB(ch, ATA_ERROR); 674 675 /* wait for BUSY to go inactive */ 676 for (timeout = 0; timeout < 310; timeout++) { 677 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) { 678 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 679 DELAY(10); 680 err = ATA_IDX_INB(ch, ATA_ERROR); 681 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 682 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 683 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 684 if (bootverbose) 685 device_printf(ch->dev, 686 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 687 stat0, err, lsb, msb); 688 if (stat0 == err && lsb == err && msb == err && timeout > 10) 689 mask &= ~0x01; 690 if (!(stat0 & ATA_S_BUSY)) { 691 if ((err & 0x7f) == ATA_E_ILI) { 692 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 693 ch->devices |= ATA_ATAPI_MASTER; 694 } 695 else if (stat0 & ATA_S_READY) { 696 ch->devices |= ATA_ATA_MASTER; 697 } 698 } 699 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 700 stat0 |= ATA_S_BUSY; 701 } 702 } 703 } 704 705 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) && 706 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) { 707 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 708 DELAY(10); 709 err = ATA_IDX_INB(ch, ATA_ERROR); 710 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 711 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 712 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 713 if (bootverbose) 714 device_printf(ch->dev, 715 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 716 stat1, err, lsb, msb); 717 if (stat1 == err && lsb == err && msb == err && timeout > 10) 718 mask &= ~0x02; 719 if (!(stat1 & ATA_S_BUSY)) { 720 if ((err & 0x7f) == ATA_E_ILI) { 721 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 722 ch->devices |= ATA_ATAPI_SLAVE; 723 } 724 else if (stat1 & ATA_S_READY) { 725 ch->devices |= ATA_ATA_SLAVE; 726 } 727 } 728 else if ((stat1 & 0x0f) && err == lsb && err == msb) { 729 stat1 |= ATA_S_BUSY; 730 } 731 } 732 } 733 734 if (mask == 0x00) /* nothing to wait for */ 735 break; 736 if (mask == 0x01) /* wait for master only */ 737 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10)) 738 break; 739 if (mask == 0x02) /* wait for slave only */ 740 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10)) 741 break; 742 if (mask == 0x03) { /* wait for both master & slave */ 743 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 744 break; 745 if ((stat0 == 0xff) && (timeout > 20)) 746 mask &= ~0x01; 747 if ((stat1 == 0xff) && (timeout > 20)) 748 mask &= ~0x02; 749 } 750 ata_udelay(100000); 751 } 752 753 if (bootverbose) 754 device_printf(ch->dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n", 755 stat0, stat1, ch->devices, 756 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 757 } 758 759 static int 760 ata_wait(struct ata_channel *ch, struct ata_device *atadev, u_int8_t mask) 761 { 762 u_int8_t status; 763 int timeout = 0; 764 765 DELAY(1); 766 767 /* wait at max 1 second for device to get !BUSY */ 768 while (timeout < 1000000) { 769 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 770 771 /* if drive fails status, reselect the drive and try again */ 772 if (status == 0xff) { 773 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 774 timeout += 1000; 775 DELAY(1000); 776 continue; 777 } 778 779 /* are we done ? */ 780 if (!(status & ATA_S_BUSY)) 781 break; 782 783 if (timeout > 1000) { 784 timeout += 1000; 785 DELAY(1000); 786 } 787 else { 788 timeout += 10; 789 DELAY(10); 790 } 791 } 792 if (timeout >= 1000000) 793 return -2; 794 if (!mask) 795 return (status & ATA_S_ERROR); 796 797 DELAY(1); 798 799 /* wait 50 msec for bits wanted */ 800 timeout = 5000; 801 while (timeout--) { 802 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 803 if ((status & mask) == mask) 804 return (status & ATA_S_ERROR); 805 DELAY(10); 806 } 807 return -3; 808 } 809 810 int 811 ata_generic_command(struct ata_device *atadev, u_int8_t command, 812 u_int64_t lba, u_int16_t count, u_int16_t feature) 813 { 814 struct ata_channel *ch = device_get_softc(device_get_parent(atadev->dev)); 815 816 /* select device */ 817 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 818 819 /* ready to issue command ? */ 820 if (ata_wait(ch, atadev, 0) < 0) { 821 device_printf(atadev->dev, "timeout sending command=%02x\n", command); 822 return -1; 823 } 824 825 /* enable interrupt */ 826 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 827 828 /* only use 48bit addressing if needed (avoid bugs and overhead) */ 829 if ((lba >= ATA_MAX_28BIT_LBA || count > 256) && 830 atadev->param.support.command2 & ATA_SUPPORT_ADDRESS48) { 831 832 /* translate command into 48bit version */ 833 switch (command) { 834 case ATA_READ: 835 command = ATA_READ48; break; 836 case ATA_READ_MUL: 837 command = ATA_READ_MUL48; break; 838 case ATA_READ_DMA: 839 command = ATA_READ_DMA48; break; 840 case ATA_READ_DMA_QUEUED: 841 command = ATA_READ_DMA_QUEUED48; break; 842 case ATA_WRITE: 843 command = ATA_WRITE48; break; 844 case ATA_WRITE_MUL: 845 command = ATA_WRITE_MUL48; break; 846 case ATA_WRITE_DMA: 847 command = ATA_WRITE_DMA48; break; 848 case ATA_WRITE_DMA_QUEUED: 849 command = ATA_WRITE_DMA_QUEUED48; break; 850 case ATA_FLUSHCACHE: 851 command = ATA_FLUSHCACHE48; break; 852 default: 853 device_printf(atadev->dev,"can't translate cmd to 48bit version\n"); 854 return -1; 855 } 856 ATA_IDX_OUTB(ch, ATA_FEATURE, (feature>>8) & 0xff); 857 ATA_IDX_OUTB(ch, ATA_FEATURE, feature & 0xff); 858 ATA_IDX_OUTB(ch, ATA_COUNT, (count>>8) & 0xff); 859 ATA_IDX_OUTB(ch, ATA_COUNT, count & 0xff); 860 ATA_IDX_OUTB(ch, ATA_SECTOR, (lba>>24) & 0xff); 861 ATA_IDX_OUTB(ch, ATA_SECTOR, lba & 0xff); 862 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (lba>>32) & 0xff); 863 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (lba>>8) & 0xff); 864 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (lba>>40) & 0xff); 865 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (lba>>16) & 0xff); 866 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit); 867 ch->flags |= ATA_48BIT_ACTIVE; 868 } 869 else { 870 ATA_IDX_OUTB(ch, ATA_FEATURE, feature); 871 ATA_IDX_OUTB(ch, ATA_COUNT, count); 872 if (atadev->flags & ATA_D_USE_CHS) { 873 int heads, sectors; 874 875 if (atadev->param.atavalid & ATA_FLAG_54_58) { 876 heads = atadev->param.current_heads; 877 sectors = atadev->param.current_sectors; 878 } 879 else { 880 heads = atadev->param.heads; 881 sectors = atadev->param.sectors; 882 } 883 ATA_IDX_OUTB(ch, ATA_SECTOR, (lba % sectors) + 1); 884 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (lba / (sectors * heads))); 885 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (lba / (sectors * heads)) >> 8); 886 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit | 887 (((lba % (sectors * heads)) / sectors) & 0xf)); 888 } 889 else { 890 ATA_IDX_OUTB(ch, ATA_SECTOR, lba & 0xff); 891 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (lba>>8) & 0xff); 892 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (lba>>16) & 0xff); 893 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit | 894 ((lba>>24) & 0x0f)); 895 } 896 ch->flags &= ~ATA_48BIT_ACTIVE; 897 } 898 899 /* issue command to controller */ 900 ATA_IDX_OUTB(ch, ATA_COMMAND, command); 901 902 return 0; 903 } 904 905 static void 906 ata_pio_read(struct ata_request *request, int length) 907 { 908 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 909 int size = min(request->transfersize, length); 910 int resid; 911 912 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 913 ATA_IDX_INSW_STRM(ch, ATA_DATA, 914 (void*)((uintptr_t)request->data+request->donecount), 915 size / sizeof(int16_t)); 916 else 917 ATA_IDX_INSL_STRM(ch, ATA_DATA, 918 (void*)((uintptr_t)request->data+request->donecount), 919 size / sizeof(int32_t)); 920 921 if (request->transfersize < length) { 922 device_printf(request->dev, "WARNING - %s read data overrun %d>%d\n", 923 ata_cmd2str(request), length, request->transfersize); 924 for (resid = request->transfersize; resid < length; 925 resid += sizeof(int16_t)) 926 ATA_IDX_INW(ch, ATA_DATA); 927 } 928 } 929 930 static void 931 ata_pio_write(struct ata_request *request, int length) 932 { 933 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 934 int size = min(request->transfersize, length); 935 int resid; 936 937 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 938 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 939 (void*)((uintptr_t)request->data+request->donecount), 940 size / sizeof(int16_t)); 941 else 942 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 943 (void*)((uintptr_t)request->data+request->donecount), 944 size / sizeof(int32_t)); 945 946 if (request->transfersize < length) { 947 device_printf(request->dev, "WARNING - %s write data underrun %d>%d\n", 948 ata_cmd2str(request), length, request->transfersize); 949 for (resid = request->transfersize; resid < length; 950 resid += sizeof(int16_t)) 951 ATA_IDX_OUTW(ch, ATA_DATA, 0); 952 } 953 } 954 955 static void 956 bswap(int8_t *buf, int len) 957 { 958 u_int16_t *ptr = (u_int16_t*)(buf + len); 959 960 while (--ptr >= (u_int16_t*)buf) 961 *ptr = ntohs(*ptr); 962 } 963 964 static void 965 btrim(int8_t *buf, int len) 966 { 967 int8_t *ptr; 968 969 for (ptr = buf; ptr < buf+len; ++ptr) 970 if (!*ptr || *ptr == '_') 971 *ptr = ' '; 972 for (ptr = buf + len - 1; ptr >= buf && *ptr == ' '; --ptr) 973 *ptr = 0; 974 } 975 976 static void 977 bpack(int8_t *src, int8_t *dst, int len) 978 { 979 int i, j, blank; 980 981 for (i = j = blank = 0 ; i < len; i++) { 982 if (blank && src[i] == ' ') continue; 983 if (blank && src[i] != ' ') { 984 dst[j++] = src[i]; 985 blank = 0; 986 continue; 987 } 988 if (src[i] == ' ') { 989 blank = 1; 990 if (i == 0) 991 continue; 992 } 993 dst[j++] = src[i]; 994 } 995 if (j < len) 996 dst[j] = 0x00; 997 } 998