1 /*- 2 * Copyright (c) 1998 - 2005 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_ata.h" 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/endian.h> 37 #include <sys/ata.h> 38 #include <sys/conf.h> 39 #include <sys/ctype.h> 40 #include <sys/bus.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/bus.h> 45 #include <sys/rman.h> 46 #include <dev/ata/ata-all.h> 47 #include <dev/ata/ata-pci.h> 48 #include <ata_if.h> 49 50 /* prototypes */ 51 static int ata_begin_transaction(struct ata_request *); 52 static int ata_end_transaction(struct ata_request *); 53 static int ata_wait(struct ata_channel *ch, struct ata_device *, u_int8_t); 54 static void ata_pio_read(struct ata_request *, int); 55 static void ata_pio_write(struct ata_request *, int); 56 57 /* 58 * low level ATA functions 59 */ 60 void 61 ata_generic_hw(device_t dev) 62 { 63 struct ata_channel *ch = device_get_softc(dev); 64 65 ch->hw.begin_transaction = ata_begin_transaction; 66 ch->hw.end_transaction = ata_end_transaction; 67 ch->hw.command = ata_generic_command; 68 } 69 70 /* must be called with ATA channel locked and state_mtx held */ 71 static int 72 ata_begin_transaction(struct ata_request *request) 73 { 74 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 75 struct ata_device *atadev = device_get_softc(request->dev); 76 int dummy; 77 78 ATA_DEBUG_RQ(request, "begin transaction"); 79 80 /* disable ATAPI DMA writes if HW doesn't support it */ 81 if ((ch->flags & ATA_ATAPI_DMA_RO) && 82 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 83 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 84 request->flags &= ~ATA_R_DMA; 85 86 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 87 88 /* ATA PIO data transfer and control commands */ 89 default: 90 { 91 /* record command direction here as our request might be gone later */ 92 int write = (request->flags & ATA_R_WRITE); 93 94 /* issue command */ 95 if (ch->hw.command(request)) { 96 device_printf(request->dev, "error issueing %s command\n", 97 ata_cmd2str(request)); 98 request->result = EIO; 99 goto begin_finished; 100 } 101 102 /* device reset doesn't interrupt */ 103 if (request->u.ata.command == ATA_DEVICE_RESET) { 104 int timeout = 1000000; 105 do { 106 DELAY(10); 107 request->status = ATA_IDX_INB(ch, ATA_STATUS); 108 } while (request->status & ATA_S_BUSY && timeout--); 109 if (request->status & ATA_S_ERROR) 110 request->error = ATA_IDX_INB(ch, ATA_ERROR); 111 goto begin_finished; 112 } 113 114 /* if write command output the data */ 115 if (write) { 116 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) { 117 device_printf(request->dev,"timeout waiting for write DRQ"); 118 request->result = EIO; 119 goto begin_finished; 120 } 121 ata_pio_write(request, request->transfersize); 122 } 123 } 124 goto begin_continue; 125 126 /* ATA DMA data transfer commands */ 127 case ATA_R_DMA: 128 /* check sanity, setup SG list and DMA engine */ 129 if (ch->dma->load(ch->dev, request->data, request->bytecount, 130 request->flags & ATA_R_READ, ch->dma->sg, &dummy)) { 131 device_printf(request->dev, "setting up DMA failed\n"); 132 request->result = EIO; 133 goto begin_finished; 134 } 135 136 /* issue command */ 137 if (ch->hw.command(request)) { 138 device_printf(request->dev, "error issueing %s command\n", 139 ata_cmd2str(request)); 140 request->result = EIO; 141 goto begin_finished; 142 } 143 144 /* start DMA engine */ 145 if (ch->dma->start && ch->dma->start(request->dev)) { 146 device_printf(request->dev, "error starting DMA\n"); 147 request->result = EIO; 148 goto begin_finished; 149 } 150 goto begin_continue; 151 152 /* ATAPI PIO commands */ 153 case ATA_R_ATAPI: 154 /* is this just a POLL DSC command ? */ 155 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 156 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 157 DELAY(10); 158 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 159 request->result = EBUSY; 160 goto begin_finished; 161 } 162 163 /* start ATAPI operation */ 164 if (ch->hw.command(request)) { 165 device_printf(request->dev, "error issuing ATA PACKET command\n"); 166 request->result = EIO; 167 goto begin_finished; 168 } 169 goto begin_continue; 170 171 /* ATAPI DMA commands */ 172 case ATA_R_ATAPI|ATA_R_DMA: 173 /* is this just a POLL DSC command ? */ 174 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 175 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 176 DELAY(10); 177 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 178 request->result = EBUSY; 179 goto begin_finished; 180 } 181 182 /* check sanity, setup SG list and DMA engine */ 183 if (ch->dma->load(ch->dev, request->data, request->bytecount, 184 request->flags & ATA_R_READ, ch->dma->sg, &dummy)) { 185 device_printf(request->dev, "setting up DMA failed\n"); 186 request->result = EIO; 187 goto begin_finished; 188 } 189 190 /* start ATAPI operation */ 191 if (ch->hw.command(request)) { 192 device_printf(request->dev, "error issuing ATA PACKET command\n"); 193 request->result = EIO; 194 goto begin_finished; 195 } 196 197 /* start DMA engine */ 198 if (ch->dma->start && ch->dma->start(request->dev)) { 199 request->result = EIO; 200 goto begin_finished; 201 } 202 goto begin_continue; 203 } 204 /* NOT REACHED */ 205 printf("ata_begin_transaction OOPS!!!\n"); 206 207 begin_finished: 208 if (ch->dma && ch->dma->flags & ATA_DMA_LOADED) 209 ch->dma->unload(ch->dev); 210 return ATA_OP_FINISHED; 211 212 begin_continue: 213 callout_reset(&request->callout, request->timeout * hz, 214 (timeout_t*)ata_timeout, request); 215 return ATA_OP_CONTINUES; 216 } 217 218 /* must be called with ATA channel locked and state_mtx held */ 219 static int 220 ata_end_transaction(struct ata_request *request) 221 { 222 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 223 struct ata_device *atadev = device_get_softc(request->dev); 224 int length; 225 226 ATA_DEBUG_RQ(request, "end transaction"); 227 228 /* clear interrupt and get status */ 229 request->status = ATA_IDX_INB(ch, ATA_STATUS); 230 231 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 232 233 /* ATA PIO data transfer and control commands */ 234 default: 235 236 /* on timeouts we have no data or anything so just return */ 237 if (request->flags & ATA_R_TIMEOUT) 238 goto end_finished; 239 240 /* on control commands read back registers to the request struct */ 241 if (request->flags & ATA_R_CONTROL) { 242 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 243 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB); 244 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8); 245 request->u.ata.lba = 246 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) | 247 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) | 248 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40); 249 250 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 251 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT); 252 request->u.ata.lba |= 253 (ATA_IDX_INB(ch, ATA_SECTOR) | 254 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 255 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16)); 256 } 257 else { 258 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 259 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 260 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 261 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 262 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24); 263 } 264 } 265 266 /* if we got an error we are done with the HW */ 267 if (request->status & ATA_S_ERROR) { 268 request->error = ATA_IDX_INB(ch, ATA_ERROR); 269 goto end_finished; 270 } 271 272 /* are we moving data ? */ 273 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 274 275 /* if read data get it */ 276 if (request->flags & ATA_R_READ) { 277 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) { 278 device_printf(request->dev, "timeout waiting for read DRQ"); 279 request->result = EIO; 280 goto end_finished; 281 } 282 ata_pio_read(request, request->transfersize); 283 } 284 285 /* update how far we've gotten */ 286 request->donecount += request->transfersize; 287 288 /* do we need a scoop more ? */ 289 if (request->bytecount > request->donecount) { 290 291 /* set this transfer size according to HW capabilities */ 292 request->transfersize = 293 min((request->bytecount - request->donecount), 294 request->transfersize); 295 296 /* if data write command, output the data */ 297 if (request->flags & ATA_R_WRITE) { 298 299 /* if we get an error here we are done with the HW */ 300 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) { 301 device_printf(request->dev, 302 "timeout waiting for write DRQ"); 303 request->status = ATA_IDX_INB(ch, ATA_STATUS); 304 goto end_finished; 305 } 306 307 /* output data and return waiting for new interrupt */ 308 ata_pio_write(request, request->transfersize); 309 goto end_continue; 310 } 311 312 /* if data read command, return & wait for interrupt */ 313 if (request->flags & ATA_R_READ) 314 goto end_continue; 315 } 316 } 317 /* done with HW */ 318 goto end_finished; 319 320 /* ATA DMA data transfer commands */ 321 case ATA_R_DMA: 322 323 /* stop DMA engine and get status */ 324 if (ch->dma->stop) 325 request->dmastat = ch->dma->stop(request->dev); 326 327 /* did we get error or data */ 328 if (request->status & ATA_S_ERROR) 329 request->error = ATA_IDX_INB(ch, ATA_ERROR); 330 else if (request->dmastat & ATA_BMSTAT_ERROR) 331 request->status |= ATA_S_ERROR; 332 else if (!(request->flags & ATA_R_TIMEOUT)) 333 request->donecount = request->bytecount; 334 335 /* release SG list etc */ 336 ch->dma->unload(ch->dev); 337 338 /* done with HW */ 339 goto end_finished; 340 341 /* ATAPI PIO commands */ 342 case ATA_R_ATAPI: 343 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 344 345 /* on timeouts we have no data or anything so just return */ 346 if (request->flags & ATA_R_TIMEOUT) 347 goto end_finished; 348 349 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 350 (request->status & ATA_S_DRQ)) { 351 352 case ATAPI_P_CMDOUT: 353 /* this seems to be needed for some (slow) devices */ 354 DELAY(10); 355 356 if (!(request->status & ATA_S_DRQ)) { 357 device_printf(request->dev, "command interrupt without DRQ\n"); 358 request->status = ATA_S_ERROR; 359 goto end_finished; 360 } 361 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 362 (atadev->param.config & 363 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); 364 /* return wait for interrupt */ 365 goto end_continue; 366 367 case ATAPI_P_WRITE: 368 if (request->flags & ATA_R_READ) { 369 request->status = ATA_S_ERROR; 370 device_printf(request->dev, 371 "%s trying to write on read buffer\n", 372 ata_cmd2str(request)); 373 goto end_finished; 374 break; 375 } 376 ata_pio_write(request, length); 377 request->donecount += length; 378 379 /* set next transfer size according to HW capabilities */ 380 request->transfersize = min((request->bytecount-request->donecount), 381 request->transfersize); 382 /* return wait for interrupt */ 383 goto end_continue; 384 385 case ATAPI_P_READ: 386 if (request->flags & ATA_R_WRITE) { 387 request->status = ATA_S_ERROR; 388 device_printf(request->dev, 389 "%s trying to read on write buffer\n", 390 ata_cmd2str(request)); 391 goto end_finished; 392 } 393 ata_pio_read(request, length); 394 request->donecount += length; 395 396 /* set next transfer size according to HW capabilities */ 397 request->transfersize = min((request->bytecount-request->donecount), 398 request->transfersize); 399 /* return wait for interrupt */ 400 goto end_continue; 401 402 case ATAPI_P_DONEDRQ: 403 device_printf(request->dev, 404 "WARNING - %s DONEDRQ non conformant device\n", 405 ata_cmd2str(request)); 406 if (request->flags & ATA_R_READ) { 407 ata_pio_read(request, length); 408 request->donecount += length; 409 } 410 else if (request->flags & ATA_R_WRITE) { 411 ata_pio_write(request, length); 412 request->donecount += length; 413 } 414 else 415 request->status = ATA_S_ERROR; 416 /* FALLTHROUGH */ 417 418 case ATAPI_P_ABORT: 419 case ATAPI_P_DONE: 420 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 421 request->error = ATA_IDX_INB(ch, ATA_ERROR); 422 goto end_finished; 423 424 default: 425 device_printf(request->dev, "unknown transfer phase\n"); 426 request->status = ATA_S_ERROR; 427 } 428 429 /* done with HW */ 430 goto end_finished; 431 432 /* ATAPI DMA commands */ 433 case ATA_R_ATAPI|ATA_R_DMA: 434 435 /* stop DMA engine and get status */ 436 if (ch->dma->stop) 437 request->dmastat = ch->dma->stop(request->dev); 438 439 /* did we get error or data */ 440 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 441 request->error = ATA_IDX_INB(ch, ATA_ERROR); 442 else if (request->dmastat & ATA_BMSTAT_ERROR) 443 request->status |= ATA_S_ERROR; 444 else if (!(request->flags & ATA_R_TIMEOUT)) 445 request->donecount = request->bytecount; 446 447 /* release SG list etc */ 448 ch->dma->unload(ch->dev); 449 450 /* done with HW */ 451 goto end_finished; 452 } 453 /* NOT REACHED */ 454 printf("ata_end_transaction OOPS!!\n"); 455 456 end_finished: 457 callout_stop(&request->callout); 458 return ATA_OP_FINISHED; 459 460 end_continue: 461 return ATA_OP_CONTINUES; 462 } 463 464 /* must be called with ATA channel locked */ 465 void 466 ata_generic_reset(device_t dev) 467 { 468 struct ata_channel *ch = device_get_softc(dev); 469 470 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0; 471 u_int8_t err = 0, lsb = 0, msb = 0; 472 int mask = 0, timeout; 473 474 /* do we have any signs of ATA/ATAPI HW being present ? */ 475 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER); 476 DELAY(10); 477 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 478 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 479 stat0 = ATA_S_BUSY; 480 mask |= 0x01; 481 } 482 483 /* in some setups we dont want to test for a slave */ 484 if (!(ch->flags & ATA_NO_SLAVE)) { 485 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_SLAVE); 486 DELAY(10); 487 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 488 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 489 stat1 = ATA_S_BUSY; 490 mask |= 0x02; 491 } 492 } 493 494 if (bootverbose) 495 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 496 mask, ostat0, ostat1); 497 498 /* if nothing showed up there is no need to get any further */ 499 /* XXX SOS is that too strong?, we just might loose devices here */ 500 ch->devices = 0; 501 if (!mask) 502 return; 503 504 /* reset (both) devices on this channel */ 505 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER); 506 DELAY(10); 507 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 508 ata_udelay(10000); 509 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 510 ata_udelay(100000); 511 ATA_IDX_INB(ch, ATA_ERROR); 512 513 /* wait for BUSY to go inactive */ 514 for (timeout = 0; timeout < 310; timeout++) { 515 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) { 516 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 517 DELAY(10); 518 err = ATA_IDX_INB(ch, ATA_ERROR); 519 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 520 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 521 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 522 if (bootverbose) 523 device_printf(dev, 524 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 525 stat0, err, lsb, msb); 526 if (stat0 == err && lsb == err && msb == err && 527 timeout > (stat0 & ATA_S_BUSY ? 100 : 10)) 528 mask &= ~0x01; 529 if (!(stat0 & ATA_S_BUSY)) { 530 if ((err & 0x7f) == ATA_E_ILI) { 531 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 532 ch->devices |= ATA_ATAPI_MASTER; 533 } 534 else if (stat0 & ATA_S_READY) { 535 ch->devices |= ATA_ATA_MASTER; 536 } 537 } 538 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 539 stat0 |= ATA_S_BUSY; 540 } 541 } 542 } 543 544 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) && 545 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) { 546 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 547 DELAY(10); 548 err = ATA_IDX_INB(ch, ATA_ERROR); 549 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 550 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 551 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 552 if (bootverbose) 553 device_printf(dev, 554 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 555 stat1, err, lsb, msb); 556 if (stat1 == err && lsb == err && msb == err && 557 timeout > (stat1 & ATA_S_BUSY ? 100 : 10)) 558 mask &= ~0x02; 559 if (!(stat1 & ATA_S_BUSY)) { 560 if ((err & 0x7f) == ATA_E_ILI) { 561 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 562 ch->devices |= ATA_ATAPI_SLAVE; 563 } 564 else if (stat1 & ATA_S_READY) { 565 ch->devices |= ATA_ATA_SLAVE; 566 } 567 } 568 else if ((stat1 & 0x0f) && err == lsb && err == msb) { 569 stat1 |= ATA_S_BUSY; 570 } 571 } 572 } 573 574 if (mask == 0x00) /* nothing to wait for */ 575 break; 576 if (mask == 0x01) /* wait for master only */ 577 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10)) 578 break; 579 if (mask == 0x02) /* wait for slave only */ 580 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10)) 581 break; 582 if (mask == 0x03) { /* wait for both master & slave */ 583 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 584 break; 585 if ((stat0 == 0xff) && (timeout > 20)) 586 mask &= ~0x01; 587 if ((stat1 == 0xff) && (timeout > 20)) 588 mask &= ~0x02; 589 } 590 ata_udelay(100000); 591 } 592 593 if (bootverbose) 594 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n", 595 stat0, stat1, ch->devices, 596 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 597 } 598 599 static int 600 ata_wait(struct ata_channel *ch, struct ata_device *atadev, u_int8_t mask) 601 { 602 u_int8_t status; 603 int timeout = 0; 604 605 DELAY(1); 606 607 /* wait at max 1 second for device to get !BUSY */ 608 while (timeout < 1000000) { 609 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 610 611 /* if drive fails status, reselect the drive and try again */ 612 if (status == 0xff) { 613 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 614 timeout += 1000; 615 DELAY(1000); 616 continue; 617 } 618 619 /* are we done ? */ 620 if (!(status & ATA_S_BUSY)) 621 break; 622 623 if (timeout > 1000) { 624 timeout += 1000; 625 DELAY(1000); 626 } 627 else { 628 timeout += 10; 629 DELAY(10); 630 } 631 } 632 if (timeout >= 1000000) 633 return -2; 634 if (!mask) 635 return (status & ATA_S_ERROR); 636 637 DELAY(1); 638 639 /* wait 50 msec for bits wanted */ 640 timeout = 5000; 641 while (timeout--) { 642 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 643 if ((status & mask) == mask) 644 return (status & ATA_S_ERROR); 645 DELAY(10); 646 } 647 return -3; 648 } 649 650 int 651 ata_generic_command(struct ata_request *request) 652 { 653 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 654 struct ata_device *atadev = device_get_softc(request->dev); 655 656 /* select device */ 657 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 658 659 /* ready to issue command ? */ 660 if (ata_wait(ch, atadev, 0) < 0) { 661 device_printf(request->dev, "timeout waiting to issue command\n"); 662 return -1; 663 } 664 665 /* enable interrupt */ 666 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 667 668 if (request->flags & ATA_R_ATAPI) { 669 int timeout = 5000; 670 671 /* issue packet command to controller */ 672 if (request->flags & ATA_R_DMA) { 673 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA); 674 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0); 675 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0); 676 } 677 else { 678 ATA_IDX_OUTB(ch, ATA_FEATURE, 0); 679 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize); 680 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8); 681 } 682 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD); 683 684 /* command interrupt device ? just return and wait for interrupt */ 685 if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR) 686 return 0; 687 688 /* wait for ready to write ATAPI command block */ 689 while (timeout--) { 690 int reason = ATA_IDX_INB(ch, ATA_IREASON); 691 int status = ATA_IDX_INB(ch, ATA_STATUS); 692 693 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 694 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 695 break; 696 DELAY(20); 697 } 698 if (timeout <= 0) { 699 device_printf(request->dev,"timeout waiting for ATAPI ready\n"); 700 request->result = EIO; 701 return -1; 702 } 703 704 /* this seems to be needed for some (slow) devices */ 705 DELAY(10); 706 707 /* output command block */ 708 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 709 (atadev->param.config & ATA_PROTO_MASK) == 710 ATA_PROTO_ATAPI_12 ? 6 : 8); 711 } 712 else { 713 u_int8_t command = ata_modify_if_48bit(request); 714 715 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 716 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8); 717 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 718 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8); 719 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 720 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24); 721 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 722 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32); 723 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 724 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40); 725 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 726 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit); 727 } 728 else { 729 command = request->u.ata.command; 730 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 731 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 732 if (atadev->flags & ATA_D_USE_CHS) { 733 int heads, sectors; 734 735 if (atadev->param.atavalid & ATA_FLAG_54_58) { 736 heads = atadev->param.current_heads; 737 sectors = atadev->param.current_sectors; 738 } 739 else { 740 heads = atadev->param.heads; 741 sectors = atadev->param.sectors; 742 } 743 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 744 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 745 (request->u.ata.lba / (sectors * heads))); 746 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 747 (request->u.ata.lba / (sectors * heads)) >> 8); 748 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit | 749 (((request->u.ata.lba% (sectors * heads)) / 750 sectors) & 0xf)); 751 } 752 else { 753 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 754 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 755 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 756 ATA_IDX_OUTB(ch, ATA_DRIVE, 757 ATA_D_IBM | ATA_D_LBA | atadev->unit | 758 ((request->u.ata.lba >> 24) & 0x0f)); 759 } 760 } 761 762 /* issue command to controller */ 763 ATA_IDX_OUTB(ch, ATA_COMMAND, command); 764 } 765 766 return 0; 767 } 768 769 static void 770 ata_pio_read(struct ata_request *request, int length) 771 { 772 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 773 int size = min(request->transfersize, length); 774 int resid; 775 776 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 777 ATA_IDX_INSW_STRM(ch, ATA_DATA, 778 (void*)((uintptr_t)request->data+request->donecount), 779 size / sizeof(int16_t)); 780 else 781 ATA_IDX_INSL_STRM(ch, ATA_DATA, 782 (void*)((uintptr_t)request->data+request->donecount), 783 size / sizeof(int32_t)); 784 785 if (request->transfersize < length) { 786 device_printf(request->dev, "WARNING - %s read data overrun %d>%d\n", 787 ata_cmd2str(request), length, request->transfersize); 788 for (resid = request->transfersize; resid < length; 789 resid += sizeof(int16_t)) 790 ATA_IDX_INW(ch, ATA_DATA); 791 } 792 } 793 794 static void 795 ata_pio_write(struct ata_request *request, int length) 796 { 797 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 798 int size = min(request->transfersize, length); 799 int resid; 800 801 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 802 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 803 (void*)((uintptr_t)request->data+request->donecount), 804 size / sizeof(int16_t)); 805 else 806 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 807 (void*)((uintptr_t)request->data+request->donecount), 808 size / sizeof(int32_t)); 809 810 if (request->transfersize < length) { 811 device_printf(request->dev, "WARNING - %s write data underrun %d>%d\n", 812 ata_cmd2str(request), length, request->transfersize); 813 for (resid = request->transfersize; resid < length; 814 resid += sizeof(int16_t)) 815 ATA_IDX_OUTW(ch, ATA_DATA, 0); 816 } 817 } 818