1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/endian.h> 35 #include <sys/ata.h> 36 #include <sys/conf.h> 37 #include <sys/ctype.h> 38 #include <sys/bus.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/ata/ata-all.h> 45 #include <dev/ata/ata-pci.h> 46 #include <ata_if.h> 47 48 /* prototypes */ 49 static int ata_generic_status(device_t dev); 50 static int ata_wait(struct ata_channel *ch, struct ata_device *, u_int8_t); 51 static void ata_pio_read(struct ata_request *, int); 52 static void ata_pio_write(struct ata_request *, int); 53 static void ata_tf_read(struct ata_request *); 54 static void ata_tf_write(struct ata_request *); 55 56 /* 57 * low level ATA functions 58 */ 59 void 60 ata_generic_hw(device_t dev) 61 { 62 struct ata_channel *ch = device_get_softc(dev); 63 64 ch->hw.begin_transaction = ata_begin_transaction; 65 ch->hw.end_transaction = ata_end_transaction; 66 ch->hw.status = ata_generic_status; 67 ch->hw.softreset = NULL; 68 ch->hw.command = ata_generic_command; 69 ch->hw.tf_read = ata_tf_read; 70 ch->hw.tf_write = ata_tf_write; 71 ch->hw.pm_read = NULL; 72 ch->hw.pm_write = NULL; 73 } 74 75 /* must be called with ATA channel locked and state_mtx held */ 76 int 77 ata_begin_transaction(struct ata_request *request) 78 { 79 struct ata_channel *ch = device_get_softc(request->parent); 80 struct ata_device *atadev = device_get_softc(request->dev); 81 int dummy, error; 82 83 ATA_DEBUG_RQ(request, "begin transaction"); 84 85 /* disable ATAPI DMA writes if HW doesn't support it */ 86 if ((ch->flags & ATA_ATAPI_DMA_RO) && 87 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 88 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 89 request->flags &= ~ATA_R_DMA; 90 91 /* check for 48 bit access and convert if needed */ 92 ata_modify_if_48bit(request); 93 94 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 95 96 /* ATA PIO data transfer and control commands */ 97 default: 98 { 99 /* record command direction here as our request might be gone later */ 100 int write = (request->flags & ATA_R_WRITE); 101 102 /* issue command */ 103 if (ch->hw.command(request)) { 104 device_printf(request->dev, "error issuing %s command\n", 105 ata_cmd2str(request)); 106 request->result = EIO; 107 goto begin_finished; 108 } 109 110 /* device reset doesn't interrupt */ 111 if (request->u.ata.command == ATA_DEVICE_RESET) { 112 113 int timeout = 1000000; 114 do { 115 DELAY(10); 116 request->status = ATA_IDX_INB(ch, ATA_STATUS); 117 } while (request->status & ATA_S_BUSY && timeout--); 118 if (request->status & ATA_S_ERROR) 119 request->error = ATA_IDX_INB(ch, ATA_ERROR); 120 goto begin_finished; 121 } 122 123 /* if write command output the data */ 124 if (write) { 125 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) { 126 device_printf(request->dev, 127 "timeout waiting for write DRQ\n"); 128 request->result = EIO; 129 goto begin_finished; 130 } 131 ata_pio_write(request, request->transfersize); 132 } 133 } 134 goto begin_continue; 135 136 /* ATA DMA data transfer commands */ 137 case ATA_R_DMA: 138 /* check sanity, setup SG list and DMA engine */ 139 if ((error = ch->dma.load(request, NULL, &dummy))) { 140 device_printf(request->dev, "setting up DMA failed\n"); 141 request->result = error; 142 goto begin_finished; 143 } 144 145 /* issue command */ 146 if (ch->hw.command(request)) { 147 device_printf(request->dev, "error issuing %s command\n", 148 ata_cmd2str(request)); 149 request->result = EIO; 150 goto begin_finished; 151 } 152 153 /* start DMA engine */ 154 if (ch->dma.start && ch->dma.start(request)) { 155 device_printf(request->dev, "error starting DMA\n"); 156 request->result = EIO; 157 goto begin_finished; 158 } 159 goto begin_continue; 160 161 /* ATAPI PIO commands */ 162 case ATA_R_ATAPI: 163 /* is this just a POLL DSC command ? */ 164 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 165 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit)); 166 DELAY(10); 167 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 168 request->result = EBUSY; 169 goto begin_finished; 170 } 171 172 /* start ATAPI operation */ 173 if (ch->hw.command(request)) { 174 device_printf(request->dev, "error issuing ATA PACKET command\n"); 175 request->result = EIO; 176 goto begin_finished; 177 } 178 goto begin_continue; 179 180 /* ATAPI DMA commands */ 181 case ATA_R_ATAPI|ATA_R_DMA: 182 /* is this just a POLL DSC command ? */ 183 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 184 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit)); 185 DELAY(10); 186 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 187 request->result = EBUSY; 188 goto begin_finished; 189 } 190 191 /* check sanity, setup SG list and DMA engine */ 192 if ((error = ch->dma.load(request, NULL, &dummy))) { 193 device_printf(request->dev, "setting up DMA failed\n"); 194 request->result = error; 195 goto begin_finished; 196 } 197 198 /* start ATAPI operation */ 199 if (ch->hw.command(request)) { 200 device_printf(request->dev, "error issuing ATA PACKET command\n"); 201 request->result = EIO; 202 goto begin_finished; 203 } 204 205 /* start DMA engine */ 206 if (ch->dma.start && ch->dma.start(request)) { 207 request->result = EIO; 208 goto begin_finished; 209 } 210 goto begin_continue; 211 } 212 /* NOT REACHED */ 213 printf("ata_begin_transaction OOPS!!!\n"); 214 215 begin_finished: 216 ch->dma.unload(request); 217 return ATA_OP_FINISHED; 218 219 begin_continue: 220 callout_reset(&request->callout, request->timeout * hz, 221 (timeout_t*)ata_timeout, request); 222 return ATA_OP_CONTINUES; 223 } 224 225 /* must be called with ATA channel locked and state_mtx held */ 226 int 227 ata_end_transaction(struct ata_request *request) 228 { 229 struct ata_channel *ch = device_get_softc(request->parent); 230 struct ata_device *atadev = device_get_softc(request->dev); 231 int length; 232 233 ATA_DEBUG_RQ(request, "end transaction"); 234 235 /* clear interrupt and get status */ 236 request->status = ATA_IDX_INB(ch, ATA_STATUS); 237 238 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 239 240 /* ATA PIO data transfer and control commands */ 241 default: 242 243 /* on timeouts we have no data or anything so just return */ 244 if (request->flags & ATA_R_TIMEOUT) 245 goto end_finished; 246 247 /* on control commands read back registers to the request struct */ 248 if (request->flags & ATA_R_CONTROL) { 249 ch->hw.tf_read(request); 250 } 251 252 /* if we got an error we are done with the HW */ 253 if (request->status & ATA_S_ERROR) { 254 request->error = ATA_IDX_INB(ch, ATA_ERROR); 255 goto end_finished; 256 } 257 258 /* are we moving data ? */ 259 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 260 261 /* if read data get it */ 262 if (request->flags & ATA_R_READ) { 263 int flags = ATA_S_DRQ; 264 265 if (request->u.ata.command != ATA_ATAPI_IDENTIFY) 266 flags |= ATA_S_READY; 267 if (ata_wait(ch, atadev, flags) < 0) { 268 device_printf(request->dev, 269 "timeout waiting for read DRQ\n"); 270 request->result = EIO; 271 goto end_finished; 272 } 273 ata_pio_read(request, request->transfersize); 274 } 275 276 /* update how far we've gotten */ 277 request->donecount += request->transfersize; 278 279 /* do we need a scoop more ? */ 280 if (request->bytecount > request->donecount) { 281 282 /* set this transfer size according to HW capabilities */ 283 request->transfersize = 284 min((request->bytecount - request->donecount), 285 request->transfersize); 286 287 /* if data write command, output the data */ 288 if (request->flags & ATA_R_WRITE) { 289 290 /* if we get an error here we are done with the HW */ 291 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) { 292 device_printf(request->dev, 293 "timeout waiting for write DRQ\n"); 294 request->status = ATA_IDX_INB(ch, ATA_STATUS); 295 goto end_finished; 296 } 297 298 /* output data and return waiting for new interrupt */ 299 ata_pio_write(request, request->transfersize); 300 goto end_continue; 301 } 302 303 /* if data read command, return & wait for interrupt */ 304 if (request->flags & ATA_R_READ) 305 goto end_continue; 306 } 307 } 308 /* done with HW */ 309 goto end_finished; 310 311 /* ATA DMA data transfer commands */ 312 case ATA_R_DMA: 313 314 /* stop DMA engine and get status */ 315 if (ch->dma.stop) 316 request->dma->status = ch->dma.stop(request); 317 318 /* did we get error or data */ 319 if (request->status & ATA_S_ERROR) 320 request->error = ATA_IDX_INB(ch, ATA_ERROR); 321 else if (request->dma->status & ATA_BMSTAT_ERROR) 322 request->status |= ATA_S_ERROR; 323 else if (!(request->flags & ATA_R_TIMEOUT)) 324 request->donecount = request->bytecount; 325 326 /* release SG list etc */ 327 ch->dma.unload(request); 328 329 /* done with HW */ 330 goto end_finished; 331 332 /* ATAPI PIO commands */ 333 case ATA_R_ATAPI: 334 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 335 336 /* on timeouts we have no data or anything so just return */ 337 if (request->flags & ATA_R_TIMEOUT) 338 goto end_finished; 339 340 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 341 (request->status & ATA_S_DRQ)) { 342 343 case ATAPI_P_CMDOUT: 344 /* this seems to be needed for some (slow) devices */ 345 DELAY(10); 346 347 if (!(request->status & ATA_S_DRQ)) { 348 device_printf(request->dev, "command interrupt without DRQ\n"); 349 request->status = ATA_S_ERROR; 350 goto end_finished; 351 } 352 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 353 (atadev->param.config & 354 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); 355 /* return wait for interrupt */ 356 goto end_continue; 357 358 case ATAPI_P_WRITE: 359 if (request->flags & ATA_R_READ) { 360 request->status = ATA_S_ERROR; 361 device_printf(request->dev, 362 "%s trying to write on read buffer\n", 363 ata_cmd2str(request)); 364 goto end_finished; 365 break; 366 } 367 ata_pio_write(request, length); 368 request->donecount += length; 369 370 /* set next transfer size according to HW capabilities */ 371 request->transfersize = min((request->bytecount-request->donecount), 372 request->transfersize); 373 /* return wait for interrupt */ 374 goto end_continue; 375 376 case ATAPI_P_READ: 377 if (request->flags & ATA_R_WRITE) { 378 request->status = ATA_S_ERROR; 379 device_printf(request->dev, 380 "%s trying to read on write buffer\n", 381 ata_cmd2str(request)); 382 goto end_finished; 383 } 384 ata_pio_read(request, length); 385 request->donecount += length; 386 387 /* set next transfer size according to HW capabilities */ 388 request->transfersize = min((request->bytecount-request->donecount), 389 request->transfersize); 390 /* return wait for interrupt */ 391 goto end_continue; 392 393 case ATAPI_P_DONEDRQ: 394 device_printf(request->dev, 395 "WARNING - %s DONEDRQ non conformant device\n", 396 ata_cmd2str(request)); 397 if (request->flags & ATA_R_READ) { 398 ata_pio_read(request, length); 399 request->donecount += length; 400 } 401 else if (request->flags & ATA_R_WRITE) { 402 ata_pio_write(request, length); 403 request->donecount += length; 404 } 405 else 406 request->status = ATA_S_ERROR; 407 /* FALLTHROUGH */ 408 409 case ATAPI_P_ABORT: 410 case ATAPI_P_DONE: 411 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 412 request->error = ATA_IDX_INB(ch, ATA_ERROR); 413 goto end_finished; 414 415 default: 416 device_printf(request->dev, "unknown transfer phase\n"); 417 request->status = ATA_S_ERROR; 418 } 419 420 /* done with HW */ 421 goto end_finished; 422 423 /* ATAPI DMA commands */ 424 case ATA_R_ATAPI|ATA_R_DMA: 425 426 /* stop DMA engine and get status */ 427 if (ch->dma.stop) 428 request->dma->status = ch->dma.stop(request); 429 430 /* did we get error or data */ 431 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 432 request->error = ATA_IDX_INB(ch, ATA_ERROR); 433 else if (request->dma->status & ATA_BMSTAT_ERROR) 434 request->status |= ATA_S_ERROR; 435 else if (!(request->flags & ATA_R_TIMEOUT)) 436 request->donecount = request->bytecount; 437 438 /* release SG list etc */ 439 ch->dma.unload(request); 440 441 /* done with HW */ 442 goto end_finished; 443 } 444 /* NOT REACHED */ 445 printf("ata_end_transaction OOPS!!\n"); 446 447 end_finished: 448 callout_stop(&request->callout); 449 return ATA_OP_FINISHED; 450 451 end_continue: 452 return ATA_OP_CONTINUES; 453 } 454 455 /* must be called with ATA channel locked and state_mtx held */ 456 void 457 ata_generic_reset(device_t dev) 458 { 459 struct ata_channel *ch = device_get_softc(dev); 460 461 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0; 462 u_int8_t err = 0, lsb = 0, msb = 0; 463 int mask = 0, timeout; 464 465 /* do we have any signs of ATA/ATAPI HW being present ? */ 466 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 467 DELAY(10); 468 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 469 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 470 stat0 = ATA_S_BUSY; 471 mask |= 0x01; 472 } 473 474 /* in some setups we dont want to test for a slave */ 475 if (!(ch->flags & ATA_NO_SLAVE)) { 476 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_SLAVE)); 477 DELAY(10); 478 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 479 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 480 stat1 = ATA_S_BUSY; 481 mask |= 0x02; 482 } 483 } 484 485 if (bootverbose) 486 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 487 mask, ostat0, ostat1); 488 489 /* if nothing showed up there is no need to get any further */ 490 /* XXX SOS is that too strong?, we just might loose devices here */ 491 ch->devices = 0; 492 if (!mask) 493 return; 494 495 /* reset (both) devices on this channel */ 496 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 497 DELAY(10); 498 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 499 ata_udelay(10000); 500 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 501 ata_udelay(100000); 502 ATA_IDX_INB(ch, ATA_ERROR); 503 504 /* wait for BUSY to go inactive */ 505 for (timeout = 0; timeout < 310; timeout++) { 506 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) { 507 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_MASTER)); 508 DELAY(10); 509 err = ATA_IDX_INB(ch, ATA_ERROR); 510 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 511 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 512 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 513 if (bootverbose) 514 device_printf(dev, 515 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 516 stat0, err, lsb, msb); 517 if (stat0 == err && lsb == err && msb == err && 518 timeout > (stat0 & ATA_S_BUSY ? 100 : 10)) 519 mask &= ~0x01; 520 if (!(stat0 & ATA_S_BUSY)) { 521 if ((err & 0x7f) == ATA_E_ILI) { 522 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 523 ch->devices |= ATA_ATAPI_MASTER; 524 } 525 else if (stat0 & ATA_S_READY) { 526 ch->devices |= ATA_ATA_MASTER; 527 } 528 } 529 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 530 stat0 |= ATA_S_BUSY; 531 } 532 } 533 } 534 535 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) && 536 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) { 537 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_SLAVE)); 538 DELAY(10); 539 err = ATA_IDX_INB(ch, ATA_ERROR); 540 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 541 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 542 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 543 if (bootverbose) 544 device_printf(dev, 545 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 546 stat1, err, lsb, msb); 547 if (stat1 == err && lsb == err && msb == err && 548 timeout > (stat1 & ATA_S_BUSY ? 100 : 10)) 549 mask &= ~0x02; 550 if (!(stat1 & ATA_S_BUSY)) { 551 if ((err & 0x7f) == ATA_E_ILI) { 552 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 553 ch->devices |= ATA_ATAPI_SLAVE; 554 } 555 else if (stat1 & ATA_S_READY) { 556 ch->devices |= ATA_ATA_SLAVE; 557 } 558 } 559 else if ((stat1 & 0x0f) && err == lsb && err == msb) { 560 stat1 |= ATA_S_BUSY; 561 } 562 } 563 } 564 565 if (mask == 0x00) /* nothing to wait for */ 566 break; 567 if (mask == 0x01) /* wait for master only */ 568 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10)) 569 break; 570 if (mask == 0x02) /* wait for slave only */ 571 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10)) 572 break; 573 if (mask == 0x03) { /* wait for both master & slave */ 574 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 575 break; 576 if ((stat0 == 0xff) && (timeout > 20)) 577 mask &= ~0x01; 578 if ((stat1 == 0xff) && (timeout > 20)) 579 mask &= ~0x02; 580 } 581 ata_udelay(100000); 582 } 583 584 if (bootverbose) 585 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%x\n", 586 stat0, stat1, ch->devices); 587 } 588 589 /* must be called with ATA channel locked and state_mtx held */ 590 int 591 ata_generic_status(device_t dev) 592 { 593 struct ata_channel *ch = device_get_softc(dev); 594 595 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 596 DELAY(100); 597 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 598 return 0; 599 } 600 return 1; 601 } 602 603 static int 604 ata_wait(struct ata_channel *ch, struct ata_device *atadev, u_int8_t mask) 605 { 606 u_int8_t status; 607 int timeout = 0; 608 609 DELAY(1); 610 611 /* wait at max 1 second for device to get !BUSY */ 612 while (timeout < 1000000) { 613 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 614 615 /* if drive fails status, reselect the drive and try again */ 616 if (status == 0xff) { 617 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit)); 618 timeout += 1000; 619 DELAY(1000); 620 continue; 621 } 622 623 /* are we done ? */ 624 if (!(status & ATA_S_BUSY)) 625 break; 626 627 if (timeout > 1000) { 628 timeout += 1000; 629 DELAY(1000); 630 } 631 else { 632 timeout += 10; 633 DELAY(10); 634 } 635 } 636 if (timeout >= 1000000) 637 return -2; 638 if (!mask) 639 return (status & ATA_S_ERROR); 640 641 DELAY(1); 642 643 /* wait 50 msec for bits wanted */ 644 timeout = 5000; 645 while (timeout--) { 646 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 647 if ((status & mask) == mask) 648 return (status & ATA_S_ERROR); 649 DELAY(10); 650 } 651 return -3; 652 } 653 654 int 655 ata_generic_command(struct ata_request *request) 656 { 657 struct ata_channel *ch = device_get_softc(request->parent); 658 struct ata_device *atadev = device_get_softc(request->dev); 659 660 /* select device */ 661 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(atadev->unit)); 662 663 /* ready to issue command ? */ 664 if (ata_wait(ch, atadev, 0) < 0) { 665 device_printf(request->dev, "timeout waiting to issue command\n"); 666 return -1; 667 } 668 669 /* enable interrupt */ 670 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 671 672 if (request->flags & ATA_R_ATAPI) { 673 int timeout = 5000; 674 675 /* issue packet command to controller */ 676 if (request->flags & ATA_R_DMA) { 677 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA); 678 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0); 679 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0); 680 } 681 else { 682 ATA_IDX_OUTB(ch, ATA_FEATURE, 0); 683 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize); 684 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8); 685 } 686 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD); 687 688 /* command interrupt device ? just return and wait for interrupt */ 689 if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR) 690 return 0; 691 692 /* wait for ready to write ATAPI command block */ 693 while (timeout--) { 694 int reason = ATA_IDX_INB(ch, ATA_IREASON); 695 int status = ATA_IDX_INB(ch, ATA_STATUS); 696 697 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 698 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 699 break; 700 DELAY(20); 701 } 702 if (timeout <= 0) { 703 device_printf(request->dev, "timeout waiting for ATAPI ready\n"); 704 request->result = EIO; 705 return -1; 706 } 707 708 /* this seems to be needed for some (slow) devices */ 709 DELAY(10); 710 711 /* output command block */ 712 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 713 (atadev->param.config & ATA_PROTO_MASK) == 714 ATA_PROTO_ATAPI_12 ? 6 : 8); 715 } 716 else { 717 ch->hw.tf_write(request); 718 719 /* issue command to controller */ 720 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 721 } 722 return 0; 723 } 724 725 static void 726 ata_tf_read(struct ata_request *request) 727 { 728 struct ata_channel *ch = device_get_softc(request->parent); 729 struct ata_device *atadev = device_get_softc(request->dev); 730 731 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 732 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB); 733 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8); 734 request->u.ata.lba = 735 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) | 736 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) | 737 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40); 738 739 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 740 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT); 741 request->u.ata.lba |= 742 (ATA_IDX_INB(ch, ATA_SECTOR) | 743 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 744 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16)); 745 } 746 else { 747 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 748 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 749 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 750 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 751 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24); 752 } 753 } 754 755 static void 756 ata_tf_write(struct ata_request *request) 757 { 758 struct ata_channel *ch = device_get_softc(request->parent); 759 struct ata_device *atadev = device_get_softc(request->dev); 760 761 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 762 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8); 763 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 764 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8); 765 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 766 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24); 767 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 768 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32); 769 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 770 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40); 771 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 772 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(atadev->unit)); 773 } 774 else { 775 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 776 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 777 if (atadev->flags & ATA_D_USE_CHS) { 778 int heads, sectors; 779 780 if (atadev->param.atavalid & ATA_FLAG_54_58) { 781 heads = atadev->param.current_heads; 782 sectors = atadev->param.current_sectors; 783 } 784 else { 785 heads = atadev->param.heads; 786 sectors = atadev->param.sectors; 787 } 788 789 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 790 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 791 (request->u.ata.lba / (sectors * heads))); 792 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 793 (request->u.ata.lba / (sectors * heads)) >> 8); 794 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit) | 795 (((request->u.ata.lba% (sectors * heads)) / 796 sectors) & 0xf)); 797 } 798 else { 799 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 800 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 801 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 802 ATA_IDX_OUTB(ch, ATA_DRIVE, 803 ATA_D_IBM | ATA_D_LBA | ATA_DEV(atadev->unit) | 804 ((request->u.ata.lba >> 24) & 0x0f)); 805 } 806 } 807 } 808 809 static void 810 ata_pio_read(struct ata_request *request, int length) 811 { 812 struct ata_channel *ch = device_get_softc(request->parent); 813 int size = min(request->transfersize, length); 814 int resid; 815 816 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 817 ATA_IDX_INSW_STRM(ch, ATA_DATA, 818 (void*)((uintptr_t)request->data+request->donecount), 819 size / sizeof(int16_t)); 820 else 821 ATA_IDX_INSL_STRM(ch, ATA_DATA, 822 (void*)((uintptr_t)request->data+request->donecount), 823 size / sizeof(int32_t)); 824 825 if (request->transfersize < length) { 826 device_printf(request->dev, "WARNING - %s read data overrun %d>%d\n", 827 ata_cmd2str(request), length, request->transfersize); 828 for (resid = request->transfersize; resid < length; 829 resid += sizeof(int16_t)) 830 ATA_IDX_INW(ch, ATA_DATA); 831 } 832 } 833 834 static void 835 ata_pio_write(struct ata_request *request, int length) 836 { 837 struct ata_channel *ch = device_get_softc(request->parent); 838 int size = min(request->transfersize, length); 839 int resid; 840 841 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 842 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 843 (void*)((uintptr_t)request->data+request->donecount), 844 size / sizeof(int16_t)); 845 else 846 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 847 (void*)((uintptr_t)request->data+request->donecount), 848 size / sizeof(int32_t)); 849 850 if (request->transfersize < length) { 851 device_printf(request->dev, "WARNING - %s write data underrun %d>%d\n", 852 ata_cmd2str(request), length, request->transfersize); 853 for (resid = request->transfersize; resid < length; 854 resid += sizeof(int16_t)) 855 ATA_IDX_OUTW(ch, ATA_DATA, 0); 856 } 857 } 858