1 /*- 2 * Copyright (c) 1998 - 2004 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_ata.h" 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/ata.h> 36 #include <sys/kernel.h> 37 #include <sys/conf.h> 38 #include <sys/bus.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/ata/ata-all.h> 45 46 /* prototypes */ 47 static int ata_generic_transaction(struct ata_request *); 48 static void ata_generic_interrupt(void *); 49 static void ata_generic_reset(struct ata_channel *); 50 static int ata_wait(struct ata_device *, u_int8_t); 51 /*static int ata_command(struct ata_device *, u_int8_t, u_int64_t, u_int16_t, u_int16_t);*/ 52 static void ata_pio_read(struct ata_request *, int); 53 static void ata_pio_write(struct ata_request *, int); 54 55 /* local vars */ 56 static int atadebug = 0; 57 58 /* 59 * low level ATA functions 60 */ 61 void 62 ata_generic_hw(struct ata_channel *ch) 63 { 64 ch->hw.reset = ata_generic_reset; 65 ch->hw.transaction = ata_generic_transaction; 66 ch->hw.interrupt = ata_generic_interrupt; 67 ch->hw.command = ata_generic_command; 68 } 69 70 /* must be called with ATA channel locked */ 71 static int 72 ata_generic_transaction(struct ata_request *request) 73 { 74 struct ata_channel *ch = request->device->channel; 75 76 /* safetybelt for HW that went away */ 77 if (!request->device->param || request->device->channel->flags&ATA_HWGONE) { 78 request->retries = 0; 79 request->result = ENXIO; 80 return ATA_OP_FINISHED; 81 } 82 83 /* record the request as running */ 84 ch->running = request; 85 86 ATA_DEBUG_RQ(request, "transaction"); 87 88 /* disable ATAPI DMA writes if HW doesn't support it */ 89 if ((ch->flags & ATA_ATAPI_DMA_RO) && 90 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 91 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 92 request->flags &= ~ATA_R_DMA; 93 94 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 95 96 /* ATA PIO data transfer and control commands */ 97 default: 98 { 99 /* record command direction here as our request might be gone later */ 100 int write = (request->flags & ATA_R_WRITE); 101 102 /* issue command */ 103 if (ch->hw.command(request->device, request->u.ata.command, 104 request->u.ata.lba, request->u.ata.count, 105 request->u.ata.feature)) { 106 ata_prtdev(request->device, "error issueing PIO command\n"); 107 request->result = EIO; 108 break; 109 } 110 111 /* if write command output the data */ 112 if (write) { 113 if (ata_wait(request->device, 114 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 115 ata_prtdev(request->device,"timeout waiting for write DRQ"); 116 request->result = EIO; 117 break; 118 } 119 ata_pio_write(request, request->transfersize); 120 } 121 } 122 123 /* return and wait for interrupt */ 124 return ATA_OP_CONTINUES; 125 126 /* ATA DMA data transfer commands */ 127 case ATA_R_DMA: 128 /* check sanity, setup SG list and DMA engine */ 129 if (ch->dma->load(request->device, request->data, request->bytecount, 130 request->flags & ATA_R_READ)) { 131 ata_prtdev(request->device, "setting up DMA failed\n"); 132 request->result = EIO; 133 break; 134 } 135 136 /* issue command */ 137 if (ch->hw.command(request->device, request->u.ata.command, 138 request->u.ata.lba, request->u.ata.count, 139 request->u.ata.feature)) { 140 ata_prtdev(request->device, "error issuing DMA command\n"); 141 request->result = EIO; 142 break; 143 } 144 145 /* start DMA engine */ 146 if (ch->dma->start(ch)) { 147 ata_prtdev(request->device, "error starting DMA\n"); 148 request->result = EIO; 149 break; 150 } 151 152 /* return and wait for interrupt */ 153 return ATA_OP_CONTINUES; 154 155 /* ATAPI PIO commands */ 156 case ATA_R_ATAPI: 157 /* is this just a POLL DSC command ? */ 158 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 159 ATA_IDX_OUTB(ch, ATA_DRIVE, 160 ATA_D_IBM | request->device->unit); 161 DELAY(10); 162 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC)) 163 request->result = EBUSY; 164 break; 165 } 166 167 /* start ATAPI operation */ 168 if (ch->hw.command(request->device, ATA_PACKET_CMD, 169 request->transfersize << 8, 0, 0)) { 170 ata_prtdev(request->device, "error issuing ATA PACKET command\n"); 171 request->result = EIO; 172 break; 173 } 174 175 /* command interrupt device ? just return and wait for interrupt */ 176 if ((request->device->param->config & ATA_DRQ_MASK) == ATA_DRQ_INTR) 177 return ATA_OP_CONTINUES; 178 179 /* wait for ready to write ATAPI command block */ 180 { 181 int timeout = 5000; /* might be less for fast devices */ 182 while (timeout--) { 183 int reason = ATA_IDX_INB(ch, ATA_IREASON); 184 int status = ATA_IDX_INB(ch, ATA_STATUS); 185 186 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 187 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 188 break; 189 DELAY(20); 190 } 191 if (timeout <= 0) { 192 ata_prtdev(request->device, 193 "timeout waiting for ATAPI ready\n"); 194 request->result = EIO; 195 break; 196 } 197 } 198 199 /* this seems to be needed for some (slow) devices */ 200 DELAY(10); 201 202 /* output actual command block */ 203 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 204 (int16_t *)request->u.atapi.ccb, 205 (request->device->param->config & ATA_PROTO_MASK) == 206 ATA_PROTO_ATAPI_12 ? 6 : 8); 207 208 /* return and wait for interrupt */ 209 return ATA_OP_CONTINUES; 210 211 case ATA_R_ATAPI|ATA_R_DMA: 212 /* is this just a POLL DSC command ? */ 213 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 214 ATA_IDX_OUTB(ch, ATA_DRIVE, 215 ATA_D_IBM | request->device->unit); 216 DELAY(10); 217 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC)) 218 request->result = EBUSY; 219 break; 220 } 221 222 /* check sanity, setup SG list and DMA engine */ 223 if (ch->dma->load(request->device, 224 request->data, 225 request->bytecount, 226 request->flags & ATA_R_READ)) { 227 ata_prtdev(request->device, "setting up DMA failed\n"); 228 request->result = EIO; 229 break; 230 } 231 232 /* start ATAPI operation */ 233 if (ch->hw.command(request->device, ATA_PACKET_CMD, 0, 0, ATA_F_DMA)) { 234 ata_prtdev(request->device, "error issuing ATAPI packet command\n"); 235 request->result = EIO; 236 break; 237 } 238 239 /* wait for ready to write ATAPI command block */ 240 { 241 int timeout = 5000; /* might be less for fast devices */ 242 while (timeout--) { 243 int reason = ATA_IDX_INB(ch, ATA_IREASON); 244 int status = ATA_IDX_INB(ch, ATA_STATUS); 245 246 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 247 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 248 break; 249 DELAY(20); 250 } 251 if (timeout <= 0) { 252 ata_prtdev(request->device,"timeout waiting for ATAPI ready\n"); 253 request->result = EIO; 254 break; 255 } 256 } 257 258 /* this seems to be needed for some (slow) devices */ 259 DELAY(10); 260 261 /* output actual command block */ 262 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 263 (int16_t *)request->u.atapi.ccb, 264 (request->device->param->config & ATA_PROTO_MASK) == 265 ATA_PROTO_ATAPI_12 ? 6 : 8); 266 267 /* start DMA engine */ 268 if (ch->dma->start(ch)) { 269 request->result = EIO; 270 break; 271 } 272 273 /* return and wait for interrupt */ 274 return ATA_OP_CONTINUES; 275 } 276 277 /* request finish here */ 278 if (ch->dma->flags & ATA_DMA_ACTIVE) 279 ch->dma->unload(ch); 280 ch->running = NULL; 281 return ATA_OP_FINISHED; 282 } 283 284 static void 285 ata_generic_interrupt(void *data) 286 { 287 struct ata_channel *ch = (struct ata_channel *)data; 288 struct ata_request *request = ch->running; 289 int length; 290 291 /* ignore this interrupt if there is no running request */ 292 if (!request) 293 return; 294 295 ATA_DEBUG_RQ(request, "interrupt"); 296 297 /* ignore interrupt if device is busy */ 298 if (!(request->flags & ATA_R_TIMEOUT) && 299 ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 300 DELAY(100); 301 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DRQ)) 302 return; 303 } 304 305 ATA_DEBUG_RQ(request, "interrupt accepted"); 306 307 /* clear interrupt and get status */ 308 request->status = ATA_IDX_INB(ch, ATA_STATUS); 309 310 /* register interrupt */ 311 if (!(request->flags & ATA_R_TIMEOUT)) 312 request->flags |= ATA_R_INTR_SEEN; 313 314 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 315 316 /* ATA PIO data transfer and control commands */ 317 default: 318 319 /* on control commands read back registers to the request struct */ 320 if (request->flags & ATA_R_CONTROL) { 321 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 322 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 323 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 324 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16); 325 } 326 327 /* if we got an error we are done with the HW */ 328 if (request->status & ATA_S_ERROR) { 329 request->error = ATA_IDX_INB(ch, ATA_ERROR); 330 break; 331 } 332 333 /* are we moving data ? */ 334 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 335 336 /* if read data get it */ 337 if (request->flags & ATA_R_READ) 338 ata_pio_read(request, request->transfersize); 339 340 /* update how far we've gotten */ 341 request->donecount += request->transfersize; 342 343 /* do we need a scoop more ? */ 344 if (request->bytecount > request->donecount) { 345 346 /* set this transfer size according to HW capabilities */ 347 request->transfersize = 348 min((request->bytecount - request->donecount), 349 request->transfersize); 350 351 /* clear interrupt seen flag as we need to wait again */ 352 request->flags &= ~ATA_R_INTR_SEEN; 353 354 /* if data write command, output the data */ 355 if (request->flags & ATA_R_WRITE) { 356 357 /* if we get an error here we are done with the HW */ 358 if (ata_wait(request->device, 359 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 360 ata_prtdev(request->device, 361 "timeout waiting for write DRQ"); 362 request->status = ATA_IDX_INB(ch, ATA_STATUS); 363 break; 364 } 365 366 /* output data and return waiting for new interrupt */ 367 ata_pio_write(request, request->transfersize); 368 return; 369 } 370 371 /* if data read command, return & wait for interrupt */ 372 if (request->flags & ATA_R_READ) 373 return; 374 } 375 } 376 /* done with HW */ 377 break; 378 379 /* ATA DMA data transfer commands */ 380 case ATA_R_DMA: 381 382 /* stop DMA engine and get status */ 383 if (ch->dma->stop) 384 request->dmastat = ch->dma->stop(ch); 385 386 /* did we get error or data */ 387 if (request->status & ATA_S_ERROR) 388 request->error = ATA_IDX_INB(ch, ATA_ERROR); 389 else if (request->dmastat & ATA_BMSTAT_ERROR) 390 request->status |= ATA_S_ERROR; 391 else 392 request->donecount = request->bytecount; 393 394 /* release SG list etc */ 395 ch->dma->unload(ch); 396 397 /* done with HW */ 398 break; 399 400 /* ATAPI PIO commands */ 401 case ATA_R_ATAPI: 402 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 403 404 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 405 (request->status & ATA_S_DRQ)) { 406 407 case ATAPI_P_CMDOUT: 408 /* this seems to be needed for some (slow) devices */ 409 DELAY(10); 410 411 if (!(request->status & ATA_S_DRQ)) { 412 ata_prtdev(request->device, "command interrupt without DRQ\n"); 413 request->status = ATA_S_ERROR; 414 break; 415 } 416 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 417 (request->device->param->config & 418 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); 419 /* return wait for interrupt */ 420 return; 421 422 case ATAPI_P_WRITE: 423 if (request->flags & ATA_R_READ) { 424 request->status = ATA_S_ERROR; 425 ata_prtdev(request->device, 426 "%s trying to write on read buffer\n", 427 ata_cmd2str(request)); 428 break; 429 } 430 ata_pio_write(request, length); 431 request->donecount += length; 432 433 /* set next transfer size according to HW capabilities */ 434 request->transfersize = min((request->bytecount-request->donecount), 435 request->transfersize); 436 /* return wait for interrupt */ 437 return; 438 439 case ATAPI_P_READ: 440 if (request->flags & ATA_R_WRITE) { 441 request->status = ATA_S_ERROR; 442 ata_prtdev(request->device, 443 "%s trying to read on write buffer\n", 444 ata_cmd2str(request)); 445 break; 446 } 447 ata_pio_read(request, length); 448 request->donecount += length; 449 450 /* set next transfer size according to HW capabilities */ 451 request->transfersize = min((request->bytecount-request->donecount), 452 request->transfersize); 453 /* return wait for interrupt */ 454 return; 455 456 case ATAPI_P_DONEDRQ: 457 ata_prtdev(request->device, 458 "WARNING - %s DONEDRQ non conformant device\n", 459 ata_cmd2str(request)); 460 if (request->flags & ATA_R_READ) { 461 ata_pio_read(request, length); 462 request->donecount += length; 463 } 464 else if (request->flags & ATA_R_WRITE) { 465 ata_pio_write(request, length); 466 request->donecount += length; 467 } 468 else 469 request->status = ATA_S_ERROR; 470 /* FALLTHROUGH */ 471 472 case ATAPI_P_ABORT: 473 case ATAPI_P_DONE: 474 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 475 request->error = ATA_IDX_INB(ch, ATA_ERROR); 476 break; 477 478 default: 479 ata_prtdev(request->device, "unknown transfer phase\n"); 480 request->status = ATA_S_ERROR; 481 } 482 483 /* done with HW */ 484 break; 485 486 /* ATAPI DMA commands */ 487 case ATA_R_ATAPI|ATA_R_DMA: 488 489 /* stop the engine and get engine status */ 490 if (ch->dma->stop) 491 request->dmastat = ch->dma->stop(ch); 492 493 /* did we get error or data */ 494 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 495 request->error = ATA_IDX_INB(ch, ATA_ERROR); 496 else if (request->dmastat & ATA_BMSTAT_ERROR) 497 request->status |= ATA_S_ERROR; 498 else 499 request->donecount = request->bytecount; 500 501 /* release SG list etc */ 502 ch->dma->unload(ch); 503 504 /* done with HW */ 505 break; 506 } 507 508 /* if we timed out the unlocking of the ATA channel is done later */ 509 if (!(request->flags & ATA_R_TIMEOUT)) { 510 ch->running = NULL; 511 ATA_UNLOCK_CH(ch); 512 ch->locking(ch, ATA_LF_UNLOCK); 513 } 514 515 /* schedule completition for this request */ 516 ata_finish(request); 517 } 518 519 /* must be called with ATA channel locked */ 520 static void 521 ata_generic_reset(struct ata_channel *ch) 522 { 523 u_int8_t err, lsb, msb, ostat0, ostat1; 524 u_int8_t stat0 = 0, stat1 = 0; 525 int mask = 0, timeout; 526 527 /* reset host end of channel (if supported) */ 528 if (ch->reset) 529 ch->reset(ch); 530 531 /* do we have any signs of ATA/ATAPI HW being present ? */ 532 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 533 DELAY(10); 534 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 535 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 536 stat0 = ATA_S_BUSY; 537 mask |= 0x01; 538 } 539 540 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 541 DELAY(10); 542 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 543 544 /* in some setups we dont want to test for a slave */ 545 if (!(ch->flags & ATA_NO_SLAVE)) { 546 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 547 stat1 = ATA_S_BUSY; 548 mask |= 0x02; 549 } 550 } 551 552 if (bootverbose) 553 ata_printf(ch, -1, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 554 mask, ostat0, ostat1); 555 556 /* if nothing showed up there is no need to get any further */ 557 /* SOS is that too strong?, we just might loose devices here XXX */ 558 ch->devices = 0; 559 if (!mask) 560 return; 561 562 /* reset (both) devices on this channel */ 563 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 564 DELAY(10); 565 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS | ATA_A_RESET); 566 DELAY(10000); 567 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS); 568 DELAY(100000); 569 ATA_IDX_INB(ch, ATA_ERROR); 570 571 /* wait for BUSY to go inactive */ 572 for (timeout = 0; timeout < 310; timeout++) { 573 if (stat0 & ATA_S_BUSY) { 574 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 575 DELAY(10); 576 err = ATA_IDX_INB(ch, ATA_ERROR); 577 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 578 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 579 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 580 if (bootverbose) 581 ata_printf(ch, ATA_MASTER, 582 "stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 583 stat0, err, lsb, msb); 584 if (!(stat0 & ATA_S_BUSY)) { 585 if ((err & 0x7f) == ATA_E_ILI) { 586 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 587 ch->devices |= ATA_ATAPI_MASTER; 588 } 589 else if (stat0 & ATA_S_READY) { 590 ch->devices |= ATA_ATA_MASTER; 591 } 592 } 593 else if ((stat0 & 0x4f) && err == lsb && err == msb) { 594 stat0 |= ATA_S_BUSY; 595 } 596 } 597 } 598 if (!((mask == 0x03) && (stat0 & ATA_S_BUSY)) && (stat1 & ATA_S_BUSY)) { 599 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 600 DELAY(10); 601 err = ATA_IDX_INB(ch, ATA_ERROR); 602 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 603 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 604 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 605 if (bootverbose) 606 ata_printf(ch, ATA_SLAVE, 607 " stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 608 stat1, err, lsb, msb); 609 if (!(stat1 & ATA_S_BUSY)) { 610 if ((err & 0x7f) == ATA_E_ILI) { 611 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 612 ch->devices |= ATA_ATAPI_SLAVE; 613 } 614 else if (stat1 & ATA_S_READY) { 615 ch->devices |= ATA_ATA_SLAVE; 616 } 617 } 618 else if ((stat1 & 0x4f) && err == lsb && err == msb) { 619 stat1 |= ATA_S_BUSY; 620 } 621 } 622 } 623 if (mask == 0x01) /* wait for master only */ 624 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 5)) 625 break; 626 if (mask == 0x02) /* wait for slave only */ 627 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 5)) 628 break; 629 if (mask == 0x03) { /* wait for both master & slave */ 630 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 631 break; 632 if (stat0 == 0xff && timeout > 5) 633 mask &= ~0x01; 634 if (stat1 == 0xff && timeout > 5) 635 mask &= ~0x02; 636 } 637 DELAY(100000); 638 } 639 640 if (bootverbose) 641 ata_printf(ch, -1, 642 "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n", 643 stat0, stat1, ch->devices, 644 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 645 } 646 647 static int 648 ata_wait(struct ata_device *atadev, u_int8_t mask) 649 { 650 u_int8_t status; 651 int timeout = 0; 652 653 DELAY(1); 654 655 /* wait 5 seconds for device to get !BUSY */ 656 while (timeout < 5000000) { 657 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 658 659 /* if drive fails status, reselect the drive just to be sure */ 660 if (status == 0xff) { 661 ata_prtdev(atadev, "WARNING no status, reselecting device\n"); 662 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit); 663 DELAY(10); 664 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 665 if (status == 0xff) 666 return -1; 667 } 668 669 /* are we done ? */ 670 if (!(status & ATA_S_BUSY)) 671 break; 672 673 if (timeout > 1000) { 674 timeout += 1000; 675 DELAY(1000); 676 } 677 else { 678 timeout += 10; 679 DELAY(10); 680 } 681 } 682 if (timeout >= 5000000) 683 return -1; 684 if (!mask) 685 return (status & ATA_S_ERROR); 686 687 DELAY(1); 688 689 /* wait 50 msec for bits wanted */ 690 timeout = 5000; 691 while (timeout--) { 692 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 693 if ((status & mask) == mask) 694 return (status & ATA_S_ERROR); 695 DELAY (10); 696 } 697 return -1; 698 } 699 700 int 701 ata_generic_command(struct ata_device *atadev, u_int8_t command, 702 u_int64_t lba, u_int16_t count, u_int16_t feature) 703 { 704 if (atadebug) 705 ata_prtdev(atadev, "ata_command: addr=%04lx, command=%02x, " 706 "lba=%jd, count=%d, feature=%d\n", 707 rman_get_start(atadev->channel->r_io[ATA_DATA].res), 708 command, (intmax_t)lba, count, feature); 709 710 /* select device */ 711 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit); 712 713 /* ready to issue command ? */ 714 if (ata_wait(atadev, 0) < 0) { 715 ata_prtdev(atadev, "timeout sending command=%02x\n", command); 716 return -1; 717 } 718 719 /* enable interrupt */ 720 ATA_IDX_OUTB(atadev->channel, ATA_ALTSTAT, ATA_A_4BIT); 721 722 /* only use 48bit addressing if needed (avoid bugs and overhead) */ 723 if ((lba > 268435455 || count > 256) && atadev->param && 724 atadev->param->support.command2 & ATA_SUPPORT_ADDRESS48) { 725 726 /* translate command into 48bit version */ 727 switch (command) { 728 case ATA_READ: 729 command = ATA_READ48; break; 730 case ATA_READ_MUL: 731 command = ATA_READ_MUL48; break; 732 case ATA_READ_DMA: 733 command = ATA_READ_DMA48; break; 734 case ATA_READ_DMA_QUEUED: 735 command = ATA_READ_DMA_QUEUED48; break; 736 case ATA_WRITE: 737 command = ATA_WRITE48; break; 738 case ATA_WRITE_MUL: 739 command = ATA_WRITE_MUL48; break; 740 case ATA_WRITE_DMA: 741 command = ATA_WRITE_DMA48; break; 742 case ATA_WRITE_DMA_QUEUED: 743 command = ATA_WRITE_DMA_QUEUED48; break; 744 case ATA_FLUSHCACHE: 745 command = ATA_FLUSHCACHE48; break; 746 default: 747 ata_prtdev(atadev, "can't translate cmd to 48bit version\n"); 748 return -1; 749 } 750 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, (feature>>8) & 0xff); 751 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature & 0xff); 752 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, (count>>8) & 0xff); 753 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count & 0xff); 754 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, (lba>>24) & 0xff); 755 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff); 756 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>32) & 0xff); 757 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff); 758 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>40) & 0xff); 759 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff); 760 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_LBA | atadev->unit); 761 atadev->channel->flags |= ATA_48BIT_ACTIVE; 762 } 763 else { 764 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature); 765 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count); 766 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff); 767 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff); 768 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff); 769 if (atadev->flags & ATA_D_USE_CHS) 770 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, 771 ATA_D_IBM | atadev->unit | ((lba>>24) & 0xf)); 772 else 773 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, 774 ATA_D_IBM | ATA_D_LBA | atadev->unit|((lba>>24)&0xf)); 775 atadev->channel->flags &= ~ATA_48BIT_ACTIVE; 776 } 777 778 /* issue command to controller */ 779 ATA_IDX_OUTB(atadev->channel, ATA_CMD, command); 780 781 return 0; 782 } 783 784 static void 785 ata_pio_read(struct ata_request *request, int length) 786 { 787 int size = min(request->transfersize, length); 788 struct ata_channel *ch = request->device->channel; 789 int resid; 790 791 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 792 ATA_IDX_INSW_STRM(ch, ATA_DATA, 793 (void*)((uintptr_t)request->data+request->donecount), 794 size / sizeof(int16_t)); 795 else 796 ATA_IDX_INSL_STRM(ch, ATA_DATA, 797 (void*)((uintptr_t)request->data+request->donecount), 798 size / sizeof(int32_t)); 799 800 if (request->transfersize < length) { 801 ata_prtdev(request->device, "WARNING - %s read data overrun %d>%d\n", 802 ata_cmd2str(request), length, request->transfersize); 803 for (resid = request->transfersize; resid < length; 804 resid += sizeof(int16_t)) 805 ATA_IDX_INW(ch, ATA_DATA); 806 } 807 } 808 809 static void 810 ata_pio_write(struct ata_request *request, int length) 811 { 812 int size = min(request->transfersize, length); 813 struct ata_channel *ch = request->device->channel; 814 int resid; 815 816 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 817 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 818 (void*)((uintptr_t)request->data+request->donecount), 819 size / sizeof(int16_t)); 820 else 821 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 822 (void*)((uintptr_t)request->data+request->donecount), 823 size / sizeof(int32_t)); 824 825 if (request->transfersize < length) { 826 ata_prtdev(request->device, "WARNING - %s write data underrun %d>%d\n", 827 ata_cmd2str(request), length, request->transfersize); 828 for (resid = request->transfersize; resid < length; 829 resid += sizeof(int16_t)) 830 ATA_IDX_OUTW(ch, ATA_DATA, 0); 831 } 832 } 833