1 /*- 2 * Copyright (c) 1998 - 2004 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_ata.h" 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/ata.h> 36 #include <sys/kernel.h> 37 #include <sys/conf.h> 38 #include <sys/bus.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/ata/ata-all.h> 45 46 /* prototypes */ 47 static int ata_generic_transaction(struct ata_request *); 48 static void ata_generic_interrupt(void *); 49 static void ata_generic_reset(struct ata_channel *); 50 static int ata_wait(struct ata_device *, u_int8_t); 51 /*static int ata_command(struct ata_device *, u_int8_t, u_int64_t, u_int16_t, u_int16_t);*/ 52 static void ata_pio_read(struct ata_request *, int); 53 static void ata_pio_write(struct ata_request *, int); 54 55 /* local vars */ 56 static int atadebug = 0; 57 58 /* 59 * low level ATA functions 60 */ 61 void 62 ata_generic_hw(struct ata_channel *ch) 63 { 64 ch->hw.reset = ata_generic_reset; 65 ch->hw.transaction = ata_generic_transaction; 66 ch->hw.interrupt = ata_generic_interrupt; 67 ch->hw.command = ata_generic_command; 68 } 69 70 /* must be called with ATA channel locked */ 71 static int 72 ata_generic_transaction(struct ata_request *request) 73 { 74 struct ata_channel *ch = request->device->channel; 75 76 /* safetybelt for HW that went away */ 77 if (!request->device->param || request->device->channel->flags&ATA_HWGONE) { 78 request->retries = 0; 79 request->result = ENXIO; 80 return ATA_OP_FINISHED; 81 } 82 83 ATA_DEBUG_RQ(request, "transaction"); 84 85 /* disable ATAPI DMA writes if HW doesn't support it */ 86 if ((ch->flags & ATA_ATAPI_DMA_RO) && 87 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 88 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 89 request->flags &= ~ATA_R_DMA; 90 91 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 92 93 /* ATA PIO data transfer and control commands */ 94 default: 95 { 96 /* record command direction here as our request might be gone later */ 97 int write = (request->flags & ATA_R_WRITE); 98 99 /* issue command */ 100 if (ch->hw.command(request->device, request->u.ata.command, 101 request->u.ata.lba, request->u.ata.count, 102 request->u.ata.feature)) { 103 ata_prtdev(request->device, "error issueing %s command\n", 104 ata_cmd2str(request)); 105 request->result = EIO; 106 break; 107 } 108 109 /* device reset doesn't interrupt */ 110 if (request->u.ata.command == ATA_ATAPI_RESET) { 111 int timeout = 1000000; 112 do { 113 DELAY(10); 114 request->status = ATA_IDX_INB(ch, ATA_STATUS); 115 } while (request->status & ATA_S_BUSY && timeout--); 116 if (timeout) 117 printf("ATAPI_RESET time = %dus\n", (1000000-timeout)*10); 118 else 119 printf("ATAPI_RESET timeout\n"); 120 121 if (request->status & ATA_S_ERROR) 122 request->error = ATA_IDX_INB(ch, ATA_ERROR); 123 break; 124 } 125 126 /* if write command output the data */ 127 if (write) { 128 if (ata_wait(request->device, 129 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 130 ata_prtdev(request->device,"timeout waiting for write DRQ"); 131 request->result = EIO; 132 break; 133 } 134 ata_pio_write(request, request->transfersize); 135 } 136 } 137 138 /* record the request as running and return for interrupt */ 139 ch->running = request; 140 return ATA_OP_CONTINUES; 141 142 /* ATA DMA data transfer commands */ 143 case ATA_R_DMA: 144 /* check sanity, setup SG list and DMA engine */ 145 if (ch->dma->load(request->device, request->data, request->bytecount, 146 request->flags & ATA_R_READ)) { 147 ata_prtdev(request->device, "setting up DMA failed\n"); 148 request->result = EIO; 149 break; 150 } 151 152 /* issue command */ 153 if (ch->hw.command(request->device, request->u.ata.command, 154 request->u.ata.lba, request->u.ata.count, 155 request->u.ata.feature)) { 156 ata_prtdev(request->device, "error issueing %s command\n", 157 ata_cmd2str(request)); 158 request->result = EIO; 159 break; 160 } 161 162 /* start DMA engine */ 163 if (ch->dma->start(ch)) { 164 ata_prtdev(request->device, "error starting DMA\n"); 165 request->result = EIO; 166 break; 167 } 168 169 /* record the request as running and return for interrupt */ 170 ch->running = request; 171 return ATA_OP_CONTINUES; 172 173 /* ATAPI PIO commands */ 174 case ATA_R_ATAPI: 175 /* is this just a POLL DSC command ? */ 176 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 177 ATA_IDX_OUTB(ch, ATA_DRIVE, 178 ATA_D_IBM | request->device->unit); 179 DELAY(10); 180 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC)) 181 request->result = EBUSY; 182 break; 183 } 184 185 /* start ATAPI operation */ 186 if (ch->hw.command(request->device, ATA_PACKET_CMD, 187 request->transfersize << 8, 0, 0)) { 188 ata_prtdev(request->device, "error issuing ATA PACKET command\n"); 189 request->result = EIO; 190 break; 191 } 192 193 /* command interrupt device ? just return and wait for interrupt */ 194 if ((request->device->param->config & ATA_DRQ_MASK) == ATA_DRQ_INTR) { 195 ch->running = request; 196 return ATA_OP_CONTINUES; 197 } 198 199 /* wait for ready to write ATAPI command block */ 200 { 201 int timeout = 5000; /* might be less for fast devices */ 202 while (timeout--) { 203 int reason = ATA_IDX_INB(ch, ATA_IREASON); 204 int status = ATA_IDX_INB(ch, ATA_STATUS); 205 206 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 207 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 208 break; 209 DELAY(20); 210 } 211 if (timeout <= 0) { 212 ata_prtdev(request->device, 213 "timeout waiting for ATAPI ready\n"); 214 request->result = EIO; 215 break; 216 } 217 } 218 219 /* this seems to be needed for some (slow) devices */ 220 DELAY(10); 221 222 /* output actual command block */ 223 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 224 (int16_t *)request->u.atapi.ccb, 225 (request->device->param->config & ATA_PROTO_MASK) == 226 ATA_PROTO_ATAPI_12 ? 6 : 8); 227 228 /* record the request as running and return for interrupt */ 229 ch->running = request; 230 return ATA_OP_CONTINUES; 231 232 case ATA_R_ATAPI|ATA_R_DMA: 233 /* is this just a POLL DSC command ? */ 234 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 235 ATA_IDX_OUTB(ch, ATA_DRIVE, 236 ATA_D_IBM | request->device->unit); 237 DELAY(10); 238 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC)) 239 request->result = EBUSY; 240 break; 241 } 242 243 /* check sanity, setup SG list and DMA engine */ 244 if (ch->dma->load(request->device, 245 request->data, 246 request->bytecount, 247 request->flags & ATA_R_READ)) { 248 ata_prtdev(request->device, "setting up DMA failed\n"); 249 request->result = EIO; 250 break; 251 } 252 253 /* start ATAPI operation */ 254 if (ch->hw.command(request->device, ATA_PACKET_CMD, 0, 0, ATA_F_DMA)) { 255 ata_prtdev(request->device, "error issuing ATAPI packet command\n"); 256 request->result = EIO; 257 break; 258 } 259 260 /* wait for ready to write ATAPI command block */ 261 { 262 int timeout = 5000; /* might be less for fast devices */ 263 while (timeout--) { 264 int reason = ATA_IDX_INB(ch, ATA_IREASON); 265 int status = ATA_IDX_INB(ch, ATA_STATUS); 266 267 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 268 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 269 break; 270 DELAY(20); 271 } 272 if (timeout <= 0) { 273 ata_prtdev(request->device,"timeout waiting for ATAPI ready\n"); 274 request->result = EIO; 275 break; 276 } 277 } 278 279 /* this seems to be needed for some (slow) devices */ 280 DELAY(10); 281 282 /* output actual command block */ 283 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 284 (int16_t *)request->u.atapi.ccb, 285 (request->device->param->config & ATA_PROTO_MASK) == 286 ATA_PROTO_ATAPI_12 ? 6 : 8); 287 288 /* start DMA engine */ 289 if (ch->dma->start(ch)) { 290 request->result = EIO; 291 break; 292 } 293 294 /* record the request as running and return for interrupt */ 295 ch->running = request; 296 return ATA_OP_CONTINUES; 297 } 298 299 /* request finish here */ 300 if (ch->dma && ch->dma->flags & ATA_DMA_LOADED) 301 ch->dma->unload(ch); 302 return ATA_OP_FINISHED; 303 } 304 305 static void 306 ata_generic_interrupt(void *data) 307 { 308 struct ata_channel *ch = (struct ata_channel *)data; 309 struct ata_request *request = ch->running; 310 int length; 311 312 /* ignore this interrupt if there is no running request */ 313 if (!request) 314 return; 315 316 ATA_DEBUG_RQ(request, "interrupt"); 317 318 /* ignore interrupt if device is busy */ 319 if (!(request->flags & ATA_R_TIMEOUT) && 320 ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 321 DELAY(100); 322 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DRQ)) 323 return; 324 } 325 326 ATA_DEBUG_RQ(request, "interrupt accepted"); 327 328 /* clear interrupt and get status */ 329 request->status = ATA_IDX_INB(ch, ATA_STATUS); 330 331 /* register interrupt */ 332 if (!(request->flags & ATA_R_TIMEOUT)) 333 request->flags |= ATA_R_INTR_SEEN; 334 335 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 336 337 /* ATA PIO data transfer and control commands */ 338 default: 339 340 /* on control commands read back registers to the request struct */ 341 if (request->flags & ATA_R_CONTROL) { 342 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 343 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 344 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 345 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16); 346 } 347 348 /* if we got an error we are done with the HW */ 349 if (request->status & ATA_S_ERROR) { 350 request->error = ATA_IDX_INB(ch, ATA_ERROR); 351 break; 352 } 353 354 /* are we moving data ? */ 355 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 356 357 /* if read data get it */ 358 if (request->flags & ATA_R_READ) 359 ata_pio_read(request, request->transfersize); 360 361 /* update how far we've gotten */ 362 request->donecount += request->transfersize; 363 364 /* do we need a scoop more ? */ 365 if (request->bytecount > request->donecount) { 366 367 /* set this transfer size according to HW capabilities */ 368 request->transfersize = 369 min((request->bytecount - request->donecount), 370 request->transfersize); 371 372 /* clear interrupt seen flag as we need to wait again */ 373 request->flags &= ~ATA_R_INTR_SEEN; 374 375 /* if data write command, output the data */ 376 if (request->flags & ATA_R_WRITE) { 377 378 /* if we get an error here we are done with the HW */ 379 if (ata_wait(request->device, 380 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 381 ata_prtdev(request->device, 382 "timeout waiting for write DRQ"); 383 request->status = ATA_IDX_INB(ch, ATA_STATUS); 384 break; 385 } 386 387 /* output data and return waiting for new interrupt */ 388 ata_pio_write(request, request->transfersize); 389 return; 390 } 391 392 /* if data read command, return & wait for interrupt */ 393 if (request->flags & ATA_R_READ) 394 return; 395 } 396 } 397 /* done with HW */ 398 break; 399 400 /* ATA DMA data transfer commands */ 401 case ATA_R_DMA: 402 403 /* stop DMA engine and get status */ 404 if (ch->dma->stop) 405 request->dmastat = ch->dma->stop(ch); 406 407 /* did we get error or data */ 408 if (request->status & ATA_S_ERROR) 409 request->error = ATA_IDX_INB(ch, ATA_ERROR); 410 else if (request->dmastat & ATA_BMSTAT_ERROR) 411 request->status |= ATA_S_ERROR; 412 else 413 request->donecount = request->bytecount; 414 415 /* release SG list etc */ 416 ch->dma->unload(ch); 417 418 /* done with HW */ 419 break; 420 421 /* ATAPI PIO commands */ 422 case ATA_R_ATAPI: 423 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 424 425 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 426 (request->status & ATA_S_DRQ)) { 427 428 case ATAPI_P_CMDOUT: 429 /* this seems to be needed for some (slow) devices */ 430 DELAY(10); 431 432 if (!(request->status & ATA_S_DRQ)) { 433 ata_prtdev(request->device, "command interrupt without DRQ\n"); 434 request->status = ATA_S_ERROR; 435 break; 436 } 437 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 438 (request->device->param->config & 439 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); 440 /* return wait for interrupt */ 441 return; 442 443 case ATAPI_P_WRITE: 444 if (request->flags & ATA_R_READ) { 445 request->status = ATA_S_ERROR; 446 ata_prtdev(request->device, 447 "%s trying to write on read buffer\n", 448 ata_cmd2str(request)); 449 break; 450 } 451 ata_pio_write(request, length); 452 request->donecount += length; 453 454 /* set next transfer size according to HW capabilities */ 455 request->transfersize = min((request->bytecount-request->donecount), 456 request->transfersize); 457 /* return wait for interrupt */ 458 return; 459 460 case ATAPI_P_READ: 461 if (request->flags & ATA_R_WRITE) { 462 request->status = ATA_S_ERROR; 463 ata_prtdev(request->device, 464 "%s trying to read on write buffer\n", 465 ata_cmd2str(request)); 466 break; 467 } 468 ata_pio_read(request, length); 469 request->donecount += length; 470 471 /* set next transfer size according to HW capabilities */ 472 request->transfersize = min((request->bytecount-request->donecount), 473 request->transfersize); 474 /* return wait for interrupt */ 475 return; 476 477 case ATAPI_P_DONEDRQ: 478 ata_prtdev(request->device, 479 "WARNING - %s DONEDRQ non conformant device\n", 480 ata_cmd2str(request)); 481 if (request->flags & ATA_R_READ) { 482 ata_pio_read(request, length); 483 request->donecount += length; 484 } 485 else if (request->flags & ATA_R_WRITE) { 486 ata_pio_write(request, length); 487 request->donecount += length; 488 } 489 else 490 request->status = ATA_S_ERROR; 491 /* FALLTHROUGH */ 492 493 case ATAPI_P_ABORT: 494 case ATAPI_P_DONE: 495 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 496 request->error = ATA_IDX_INB(ch, ATA_ERROR); 497 break; 498 499 default: 500 ata_prtdev(request->device, "unknown transfer phase\n"); 501 request->status = ATA_S_ERROR; 502 } 503 504 /* done with HW */ 505 break; 506 507 /* ATAPI DMA commands */ 508 case ATA_R_ATAPI|ATA_R_DMA: 509 510 /* stop the engine and get engine status */ 511 if (ch->dma->stop) 512 request->dmastat = ch->dma->stop(ch); 513 514 /* did we get error or data */ 515 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 516 request->error = ATA_IDX_INB(ch, ATA_ERROR); 517 else if (request->dmastat & ATA_BMSTAT_ERROR) 518 request->status |= ATA_S_ERROR; 519 else 520 request->donecount = request->bytecount; 521 522 /* release SG list etc */ 523 ch->dma->unload(ch); 524 525 /* done with HW */ 526 break; 527 } 528 529 /* finished running this request schedule completition */ 530 ch->running = NULL; 531 ata_finish(request); 532 } 533 534 /* must be called with ATA channel locked */ 535 static void 536 ata_generic_reset(struct ata_channel *ch) 537 { 538 u_int8_t err, lsb, msb, ostat0, ostat1; 539 u_int8_t stat0 = 0, stat1 = 0; 540 int mask = 0, timeout; 541 542 /* if DMA functionality present stop it */ 543 if (ch->dma) { 544 if (ch->dma->stop) 545 ch->dma->stop(ch); 546 if (ch->dma->flags & ATA_DMA_LOADED) 547 ch->dma->unload(ch); 548 } 549 550 /* reset host end of channel (if supported) */ 551 if (ch->reset) 552 ch->reset(ch); 553 554 /* do we have any signs of ATA/ATAPI HW being present ? */ 555 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 556 DELAY(10); 557 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 558 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 559 stat0 = ATA_S_BUSY; 560 mask |= 0x01; 561 } 562 563 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 564 DELAY(10); 565 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 566 567 /* in some setups we dont want to test for a slave */ 568 if (!(ch->flags & ATA_NO_SLAVE)) { 569 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 570 stat1 = ATA_S_BUSY; 571 mask |= 0x02; 572 } 573 } 574 575 if (bootverbose) 576 ata_printf(ch, -1, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 577 mask, ostat0, ostat1); 578 579 /* if nothing showed up there is no need to get any further */ 580 /* SOS is that too strong?, we just might loose devices here XXX */ 581 ch->devices = 0; 582 if (!mask) 583 return; 584 585 /* reset (both) devices on this channel */ 586 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 587 DELAY(10); 588 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS | ATA_A_RESET); 589 ata_udelay(10000); 590 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS); 591 ata_udelay(100000); 592 ATA_IDX_INB(ch, ATA_ERROR); 593 594 /* wait for BUSY to go inactive */ 595 for (timeout = 0; timeout < 310; timeout++) { 596 if (stat0 & ATA_S_BUSY) { 597 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 598 DELAY(10); 599 err = ATA_IDX_INB(ch, ATA_ERROR); 600 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 601 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 602 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 603 if (bootverbose) 604 ata_printf(ch, ATA_MASTER, 605 "stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 606 stat0, err, lsb, msb); 607 if (!(stat0 & ATA_S_BUSY)) { 608 if ((err & 0x7f) == ATA_E_ILI) { 609 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 610 ch->devices |= ATA_ATAPI_MASTER; 611 } 612 else if (stat0 & ATA_S_READY) { 613 ch->devices |= ATA_ATA_MASTER; 614 } 615 } 616 else if ((stat0 & 0x4f) && err == lsb && err == msb) { 617 stat0 |= ATA_S_BUSY; 618 } 619 } 620 } 621 if (!((mask == 0x03) && (stat0 & ATA_S_BUSY)) && (stat1 & ATA_S_BUSY)) { 622 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 623 DELAY(10); 624 err = ATA_IDX_INB(ch, ATA_ERROR); 625 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 626 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 627 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 628 if (bootverbose) 629 ata_printf(ch, ATA_SLAVE, 630 " stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 631 stat1, err, lsb, msb); 632 if (!(stat1 & ATA_S_BUSY)) { 633 if ((err & 0x7f) == ATA_E_ILI) { 634 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 635 ch->devices |= ATA_ATAPI_SLAVE; 636 } 637 else if (stat1 & ATA_S_READY) { 638 ch->devices |= ATA_ATA_SLAVE; 639 } 640 } 641 else if ((stat1 & 0x4f) && err == lsb && err == msb) { 642 stat1 |= ATA_S_BUSY; 643 } 644 } 645 } 646 if (mask == 0x01) /* wait for master only */ 647 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 5)) 648 break; 649 if (mask == 0x02) /* wait for slave only */ 650 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 5)) 651 break; 652 if (mask == 0x03) { /* wait for both master & slave */ 653 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 654 break; 655 if (stat0 == 0xff && timeout > 5) 656 mask &= ~0x01; 657 if (stat1 == 0xff && timeout > 5) 658 mask &= ~0x02; 659 } 660 ata_udelay(100000); 661 } 662 663 if (bootverbose) 664 ata_printf(ch, -1, 665 "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n", 666 stat0, stat1, ch->devices, 667 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 668 } 669 670 static int 671 ata_wait(struct ata_device *atadev, u_int8_t mask) 672 { 673 u_int8_t status; 674 int timeout = 0; 675 676 DELAY(1); 677 678 /* wait 5 seconds for device to get !BUSY */ 679 while (timeout < 5000000) { 680 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 681 682 /* if drive fails status, reselect the drive just to be sure */ 683 if (status == 0xff) { 684 ata_prtdev(atadev, "WARNING no status, reselecting device\n"); 685 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit); 686 DELAY(10); 687 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 688 if (status == 0xff) 689 return -1; 690 } 691 692 /* are we done ? */ 693 if (!(status & ATA_S_BUSY)) 694 break; 695 696 if (timeout > 1000) { 697 timeout += 1000; 698 DELAY(1000); 699 } 700 else { 701 timeout += 10; 702 DELAY(10); 703 } 704 } 705 if (timeout >= 5000000) 706 return -1; 707 if (!mask) 708 return (status & ATA_S_ERROR); 709 710 DELAY(1); 711 712 /* wait 50 msec for bits wanted */ 713 timeout = 5000; 714 while (timeout--) { 715 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 716 if ((status & mask) == mask) 717 return (status & ATA_S_ERROR); 718 DELAY (10); 719 } 720 return -1; 721 } 722 723 int 724 ata_generic_command(struct ata_device *atadev, u_int8_t command, 725 u_int64_t lba, u_int16_t count, u_int16_t feature) 726 { 727 if (atadebug) 728 ata_prtdev(atadev, "ata_command: addr=%04lx, command=%02x, " 729 "lba=%jd, count=%d, feature=%d\n", 730 rman_get_start(atadev->channel->r_io[ATA_DATA].res), 731 command, (intmax_t)lba, count, feature); 732 733 /* select device */ 734 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit); 735 736 /* ready to issue command ? */ 737 if (ata_wait(atadev, 0) < 0) { 738 ata_prtdev(atadev, "timeout sending command=%02x\n", command); 739 return -1; 740 } 741 742 /* enable interrupt */ 743 ATA_IDX_OUTB(atadev->channel, ATA_ALTSTAT, ATA_A_4BIT); 744 745 /* only use 48bit addressing if needed (avoid bugs and overhead) */ 746 if ((lba > 268435455 || count > 256) && atadev->param && 747 atadev->param->support.command2 & ATA_SUPPORT_ADDRESS48) { 748 749 /* translate command into 48bit version */ 750 switch (command) { 751 case ATA_READ: 752 command = ATA_READ48; break; 753 case ATA_READ_MUL: 754 command = ATA_READ_MUL48; break; 755 case ATA_READ_DMA: 756 command = ATA_READ_DMA48; break; 757 case ATA_READ_DMA_QUEUED: 758 command = ATA_READ_DMA_QUEUED48; break; 759 case ATA_WRITE: 760 command = ATA_WRITE48; break; 761 case ATA_WRITE_MUL: 762 command = ATA_WRITE_MUL48; break; 763 case ATA_WRITE_DMA: 764 command = ATA_WRITE_DMA48; break; 765 case ATA_WRITE_DMA_QUEUED: 766 command = ATA_WRITE_DMA_QUEUED48; break; 767 case ATA_FLUSHCACHE: 768 command = ATA_FLUSHCACHE48; break; 769 default: 770 ata_prtdev(atadev, "can't translate cmd to 48bit version\n"); 771 return -1; 772 } 773 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, (feature>>8) & 0xff); 774 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature & 0xff); 775 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, (count>>8) & 0xff); 776 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count & 0xff); 777 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, (lba>>24) & 0xff); 778 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff); 779 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>32) & 0xff); 780 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff); 781 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>40) & 0xff); 782 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff); 783 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_LBA | atadev->unit); 784 atadev->channel->flags |= ATA_48BIT_ACTIVE; 785 } 786 else { 787 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature); 788 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count); 789 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff); 790 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff); 791 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff); 792 if (atadev->flags & ATA_D_USE_CHS) 793 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, 794 ATA_D_IBM | atadev->unit | ((lba>>24) & 0xf)); 795 else 796 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, 797 ATA_D_IBM | ATA_D_LBA | atadev->unit|((lba>>24)&0xf)); 798 atadev->channel->flags &= ~ATA_48BIT_ACTIVE; 799 } 800 801 /* issue command to controller */ 802 ATA_IDX_OUTB(atadev->channel, ATA_CMD, command); 803 804 return 0; 805 } 806 807 static void 808 ata_pio_read(struct ata_request *request, int length) 809 { 810 int size = min(request->transfersize, length); 811 struct ata_channel *ch = request->device->channel; 812 int resid; 813 814 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 815 ATA_IDX_INSW_STRM(ch, ATA_DATA, 816 (void*)((uintptr_t)request->data+request->donecount), 817 size / sizeof(int16_t)); 818 else 819 ATA_IDX_INSL_STRM(ch, ATA_DATA, 820 (void*)((uintptr_t)request->data+request->donecount), 821 size / sizeof(int32_t)); 822 823 if (request->transfersize < length) { 824 ata_prtdev(request->device, "WARNING - %s read data overrun %d>%d\n", 825 ata_cmd2str(request), length, request->transfersize); 826 for (resid = request->transfersize; resid < length; 827 resid += sizeof(int16_t)) 828 ATA_IDX_INW(ch, ATA_DATA); 829 } 830 } 831 832 static void 833 ata_pio_write(struct ata_request *request, int length) 834 { 835 int size = min(request->transfersize, length); 836 struct ata_channel *ch = request->device->channel; 837 int resid; 838 839 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 840 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 841 (void*)((uintptr_t)request->data+request->donecount), 842 size / sizeof(int16_t)); 843 else 844 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 845 (void*)((uintptr_t)request->data+request->donecount), 846 size / sizeof(int32_t)); 847 848 if (request->transfersize < length) { 849 ata_prtdev(request->device, "WARNING - %s write data underrun %d>%d\n", 850 ata_cmd2str(request), length, request->transfersize); 851 for (resid = request->transfersize; resid < length; 852 resid += sizeof(int16_t)) 853 ATA_IDX_OUTW(ch, ATA_DATA, 0); 854 } 855 } 856