1 /*- 2 * Copyright (c) 1998 - 2007 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/endian.h> 35 #include <sys/ata.h> 36 #include <sys/conf.h> 37 #include <sys/ctype.h> 38 #include <sys/bus.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/ata/ata-all.h> 45 #include <dev/ata/ata-pci.h> 46 #include <ata_if.h> 47 48 /* prototypes */ 49 static int ata_generic_status(device_t dev); 50 static int ata_wait(struct ata_channel *ch, struct ata_device *, u_int8_t); 51 static void ata_pio_read(struct ata_request *, int); 52 static void ata_pio_write(struct ata_request *, int); 53 54 /* 55 * low level ATA functions 56 */ 57 void 58 ata_generic_hw(device_t dev) 59 { 60 struct ata_channel *ch = device_get_softc(dev); 61 62 ch->hw.begin_transaction = ata_begin_transaction; 63 ch->hw.end_transaction = ata_end_transaction; 64 ch->hw.status = ata_generic_status; 65 ch->hw.command = ata_generic_command; 66 } 67 68 /* must be called with ATA channel locked and state_mtx held */ 69 int 70 ata_begin_transaction(struct ata_request *request) 71 { 72 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 73 struct ata_device *atadev = device_get_softc(request->dev); 74 int dummy, error; 75 76 ATA_DEBUG_RQ(request, "begin transaction"); 77 78 /* disable ATAPI DMA writes if HW doesn't support it */ 79 if ((ch->flags & ATA_ATAPI_DMA_RO) && 80 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 81 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 82 request->flags &= ~ATA_R_DMA; 83 84 /* check for 48 bit access and convert if needed */ 85 ata_modify_if_48bit(request); 86 87 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 88 89 /* ATA PIO data transfer and control commands */ 90 default: 91 { 92 /* record command direction here as our request might be gone later */ 93 int write = (request->flags & ATA_R_WRITE); 94 95 /* issue command */ 96 if (ch->hw.command(request)) { 97 device_printf(request->dev, "error issuing %s command\n", 98 ata_cmd2str(request)); 99 request->result = EIO; 100 goto begin_finished; 101 } 102 103 /* device reset doesn't interrupt */ 104 if (request->u.ata.command == ATA_DEVICE_RESET) { 105 106 int timeout = 1000000; 107 do { 108 DELAY(10); 109 request->status = ATA_IDX_INB(ch, ATA_STATUS); 110 } while (request->status & ATA_S_BUSY && timeout--); 111 if (request->status & ATA_S_ERROR) 112 request->error = ATA_IDX_INB(ch, ATA_ERROR); 113 goto begin_finished; 114 } 115 116 /* if write command output the data */ 117 if (write) { 118 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) { 119 device_printf(request->dev, 120 "timeout waiting for write DRQ\n"); 121 request->result = EIO; 122 goto begin_finished; 123 } 124 ata_pio_write(request, request->transfersize); 125 } 126 } 127 goto begin_continue; 128 129 /* ATA DMA data transfer commands */ 130 case ATA_R_DMA: 131 /* check sanity, setup SG list and DMA engine */ 132 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount, 133 request->flags & ATA_R_READ, ch->dma->sg, 134 &dummy))) { 135 device_printf(request->dev, "setting up DMA failed\n"); 136 request->result = error; 137 goto begin_finished; 138 } 139 140 /* issue command */ 141 if (ch->hw.command(request)) { 142 device_printf(request->dev, "error issuing %s command\n", 143 ata_cmd2str(request)); 144 request->result = EIO; 145 goto begin_finished; 146 } 147 148 /* start DMA engine */ 149 if (ch->dma->start && ch->dma->start(request->dev)) { 150 device_printf(request->dev, "error starting DMA\n"); 151 request->result = EIO; 152 goto begin_finished; 153 } 154 goto begin_continue; 155 156 /* ATAPI PIO commands */ 157 case ATA_R_ATAPI: 158 /* is this just a POLL DSC command ? */ 159 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 160 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 161 DELAY(10); 162 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 163 request->result = EBUSY; 164 goto begin_finished; 165 } 166 167 /* start ATAPI operation */ 168 if (ch->hw.command(request)) { 169 device_printf(request->dev, "error issuing ATA PACKET command\n"); 170 request->result = EIO; 171 goto begin_finished; 172 } 173 goto begin_continue; 174 175 /* ATAPI DMA commands */ 176 case ATA_R_ATAPI|ATA_R_DMA: 177 /* is this just a POLL DSC command ? */ 178 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 179 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 180 DELAY(10); 181 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 182 request->result = EBUSY; 183 goto begin_finished; 184 } 185 186 /* check sanity, setup SG list and DMA engine */ 187 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount, 188 request->flags & ATA_R_READ, ch->dma->sg, 189 &dummy))) { 190 device_printf(request->dev, "setting up DMA failed\n"); 191 request->result = error; 192 goto begin_finished; 193 } 194 195 /* start ATAPI operation */ 196 if (ch->hw.command(request)) { 197 device_printf(request->dev, "error issuing ATA PACKET command\n"); 198 request->result = EIO; 199 goto begin_finished; 200 } 201 202 /* start DMA engine */ 203 if (ch->dma->start && ch->dma->start(request->dev)) { 204 request->result = EIO; 205 goto begin_finished; 206 } 207 goto begin_continue; 208 } 209 /* NOT REACHED */ 210 printf("ata_begin_transaction OOPS!!!\n"); 211 212 begin_finished: 213 if (ch->dma && ch->dma->flags & ATA_DMA_LOADED) 214 ch->dma->unload(ch->dev); 215 return ATA_OP_FINISHED; 216 217 begin_continue: 218 callout_reset(&request->callout, request->timeout * hz, 219 (timeout_t*)ata_timeout, request); 220 return ATA_OP_CONTINUES; 221 } 222 223 /* must be called with ATA channel locked and state_mtx held */ 224 int 225 ata_end_transaction(struct ata_request *request) 226 { 227 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 228 struct ata_device *atadev = device_get_softc(request->dev); 229 int length; 230 231 ATA_DEBUG_RQ(request, "end transaction"); 232 233 /* clear interrupt and get status */ 234 request->status = ATA_IDX_INB(ch, ATA_STATUS); 235 236 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 237 238 /* ATA PIO data transfer and control commands */ 239 default: 240 241 /* on timeouts we have no data or anything so just return */ 242 if (request->flags & ATA_R_TIMEOUT) 243 goto end_finished; 244 245 /* on control commands read back registers to the request struct */ 246 if (request->flags & ATA_R_CONTROL) { 247 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 248 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB); 249 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8); 250 request->u.ata.lba = 251 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) | 252 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) | 253 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40); 254 255 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 256 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT); 257 request->u.ata.lba |= 258 (ATA_IDX_INB(ch, ATA_SECTOR) | 259 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 260 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16)); 261 } 262 else { 263 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 264 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 265 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 266 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 267 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24); 268 } 269 } 270 271 /* if we got an error we are done with the HW */ 272 if (request->status & ATA_S_ERROR) { 273 request->error = ATA_IDX_INB(ch, ATA_ERROR); 274 goto end_finished; 275 } 276 277 /* are we moving data ? */ 278 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 279 280 /* if read data get it */ 281 if (request->flags & ATA_R_READ) { 282 int flags = ATA_S_DRQ; 283 284 if (request->u.ata.command != ATA_ATAPI_IDENTIFY) 285 flags |= ATA_S_READY; 286 if (ata_wait(ch, atadev, flags) < 0) { 287 device_printf(request->dev, 288 "timeout waiting for read DRQ\n"); 289 request->result = EIO; 290 goto end_finished; 291 } 292 ata_pio_read(request, request->transfersize); 293 } 294 295 /* update how far we've gotten */ 296 request->donecount += request->transfersize; 297 298 /* do we need a scoop more ? */ 299 if (request->bytecount > request->donecount) { 300 301 /* set this transfer size according to HW capabilities */ 302 request->transfersize = 303 min((request->bytecount - request->donecount), 304 request->transfersize); 305 306 /* if data write command, output the data */ 307 if (request->flags & ATA_R_WRITE) { 308 309 /* if we get an error here we are done with the HW */ 310 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) { 311 device_printf(request->dev, 312 "timeout waiting for write DRQ\n"); 313 request->status = ATA_IDX_INB(ch, ATA_STATUS); 314 goto end_finished; 315 } 316 317 /* output data and return waiting for new interrupt */ 318 ata_pio_write(request, request->transfersize); 319 goto end_continue; 320 } 321 322 /* if data read command, return & wait for interrupt */ 323 if (request->flags & ATA_R_READ) 324 goto end_continue; 325 } 326 } 327 /* done with HW */ 328 goto end_finished; 329 330 /* ATA DMA data transfer commands */ 331 case ATA_R_DMA: 332 333 /* stop DMA engine and get status */ 334 if (ch->dma->stop) 335 request->dmastat = ch->dma->stop(request->dev); 336 337 /* did we get error or data */ 338 if (request->status & ATA_S_ERROR) 339 request->error = ATA_IDX_INB(ch, ATA_ERROR); 340 else if (request->dmastat & ATA_BMSTAT_ERROR) 341 request->status |= ATA_S_ERROR; 342 else if (!(request->flags & ATA_R_TIMEOUT)) 343 request->donecount = request->bytecount; 344 345 /* release SG list etc */ 346 ch->dma->unload(ch->dev); 347 348 /* done with HW */ 349 goto end_finished; 350 351 /* ATAPI PIO commands */ 352 case ATA_R_ATAPI: 353 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 354 355 /* on timeouts we have no data or anything so just return */ 356 if (request->flags & ATA_R_TIMEOUT) 357 goto end_finished; 358 359 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 360 (request->status & ATA_S_DRQ)) { 361 362 case ATAPI_P_CMDOUT: 363 /* this seems to be needed for some (slow) devices */ 364 DELAY(10); 365 366 if (!(request->status & ATA_S_DRQ)) { 367 device_printf(request->dev, "command interrupt without DRQ\n"); 368 request->status = ATA_S_ERROR; 369 goto end_finished; 370 } 371 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 372 (atadev->param.config & 373 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); 374 /* return wait for interrupt */ 375 goto end_continue; 376 377 case ATAPI_P_WRITE: 378 if (request->flags & ATA_R_READ) { 379 request->status = ATA_S_ERROR; 380 device_printf(request->dev, 381 "%s trying to write on read buffer\n", 382 ata_cmd2str(request)); 383 goto end_finished; 384 break; 385 } 386 ata_pio_write(request, length); 387 request->donecount += length; 388 389 /* set next transfer size according to HW capabilities */ 390 request->transfersize = min((request->bytecount-request->donecount), 391 request->transfersize); 392 /* return wait for interrupt */ 393 goto end_continue; 394 395 case ATAPI_P_READ: 396 if (request->flags & ATA_R_WRITE) { 397 request->status = ATA_S_ERROR; 398 device_printf(request->dev, 399 "%s trying to read on write buffer\n", 400 ata_cmd2str(request)); 401 goto end_finished; 402 } 403 ata_pio_read(request, length); 404 request->donecount += length; 405 406 /* set next transfer size according to HW capabilities */ 407 request->transfersize = min((request->bytecount-request->donecount), 408 request->transfersize); 409 /* return wait for interrupt */ 410 goto end_continue; 411 412 case ATAPI_P_DONEDRQ: 413 device_printf(request->dev, 414 "WARNING - %s DONEDRQ non conformant device\n", 415 ata_cmd2str(request)); 416 if (request->flags & ATA_R_READ) { 417 ata_pio_read(request, length); 418 request->donecount += length; 419 } 420 else if (request->flags & ATA_R_WRITE) { 421 ata_pio_write(request, length); 422 request->donecount += length; 423 } 424 else 425 request->status = ATA_S_ERROR; 426 /* FALLTHROUGH */ 427 428 case ATAPI_P_ABORT: 429 case ATAPI_P_DONE: 430 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 431 request->error = ATA_IDX_INB(ch, ATA_ERROR); 432 goto end_finished; 433 434 default: 435 device_printf(request->dev, "unknown transfer phase\n"); 436 request->status = ATA_S_ERROR; 437 } 438 439 /* done with HW */ 440 goto end_finished; 441 442 /* ATAPI DMA commands */ 443 case ATA_R_ATAPI|ATA_R_DMA: 444 445 /* stop DMA engine and get status */ 446 if (ch->dma->stop) 447 request->dmastat = ch->dma->stop(request->dev); 448 449 /* did we get error or data */ 450 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 451 request->error = ATA_IDX_INB(ch, ATA_ERROR); 452 else if (request->dmastat & ATA_BMSTAT_ERROR) 453 request->status |= ATA_S_ERROR; 454 else if (!(request->flags & ATA_R_TIMEOUT)) 455 request->donecount = request->bytecount; 456 457 /* release SG list etc */ 458 ch->dma->unload(ch->dev); 459 460 /* done with HW */ 461 goto end_finished; 462 } 463 /* NOT REACHED */ 464 printf("ata_end_transaction OOPS!!\n"); 465 466 end_finished: 467 callout_stop(&request->callout); 468 return ATA_OP_FINISHED; 469 470 end_continue: 471 return ATA_OP_CONTINUES; 472 } 473 474 /* must be called with ATA channel locked and state_mtx held */ 475 void 476 ata_generic_reset(device_t dev) 477 { 478 struct ata_channel *ch = device_get_softc(dev); 479 480 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0; 481 u_int8_t err = 0, lsb = 0, msb = 0; 482 int mask = 0, timeout; 483 484 /* do we have any signs of ATA/ATAPI HW being present ? */ 485 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER); 486 DELAY(10); 487 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 488 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 489 stat0 = ATA_S_BUSY; 490 mask |= 0x01; 491 } 492 493 /* in some setups we dont want to test for a slave */ 494 if (!(ch->flags & ATA_NO_SLAVE)) { 495 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_SLAVE); 496 DELAY(10); 497 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 498 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 499 stat1 = ATA_S_BUSY; 500 mask |= 0x02; 501 } 502 } 503 504 if (bootverbose) 505 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 506 mask, ostat0, ostat1); 507 508 /* if nothing showed up there is no need to get any further */ 509 /* XXX SOS is that too strong?, we just might loose devices here */ 510 ch->devices = 0; 511 if (!mask) 512 return; 513 514 /* reset (both) devices on this channel */ 515 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER); 516 DELAY(10); 517 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 518 ata_udelay(10000); 519 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 520 ata_udelay(100000); 521 ATA_IDX_INB(ch, ATA_ERROR); 522 523 /* wait for BUSY to go inactive */ 524 for (timeout = 0; timeout < 310; timeout++) { 525 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) { 526 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 527 DELAY(10); 528 err = ATA_IDX_INB(ch, ATA_ERROR); 529 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 530 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 531 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 532 if (bootverbose) 533 device_printf(dev, 534 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 535 stat0, err, lsb, msb); 536 if (stat0 == err && lsb == err && msb == err && 537 timeout > (stat0 & ATA_S_BUSY ? 100 : 10)) 538 mask &= ~0x01; 539 if (!(stat0 & ATA_S_BUSY)) { 540 if ((err & 0x7f) == ATA_E_ILI) { 541 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 542 ch->devices |= ATA_ATAPI_MASTER; 543 } 544 else if (stat0 & ATA_S_READY) { 545 ch->devices |= ATA_ATA_MASTER; 546 } 547 } 548 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 549 stat0 |= ATA_S_BUSY; 550 } 551 } 552 } 553 554 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) && 555 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) { 556 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 557 DELAY(10); 558 err = ATA_IDX_INB(ch, ATA_ERROR); 559 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 560 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 561 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 562 if (bootverbose) 563 device_printf(dev, 564 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 565 stat1, err, lsb, msb); 566 if (stat1 == err && lsb == err && msb == err && 567 timeout > (stat1 & ATA_S_BUSY ? 100 : 10)) 568 mask &= ~0x02; 569 if (!(stat1 & ATA_S_BUSY)) { 570 if ((err & 0x7f) == ATA_E_ILI) { 571 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 572 ch->devices |= ATA_ATAPI_SLAVE; 573 } 574 else if (stat1 & ATA_S_READY) { 575 ch->devices |= ATA_ATA_SLAVE; 576 } 577 } 578 else if ((stat1 & 0x0f) && err == lsb && err == msb) { 579 stat1 |= ATA_S_BUSY; 580 } 581 } 582 } 583 584 if (mask == 0x00) /* nothing to wait for */ 585 break; 586 if (mask == 0x01) /* wait for master only */ 587 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10)) 588 break; 589 if (mask == 0x02) /* wait for slave only */ 590 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10)) 591 break; 592 if (mask == 0x03) { /* wait for both master & slave */ 593 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 594 break; 595 if ((stat0 == 0xff) && (timeout > 20)) 596 mask &= ~0x01; 597 if ((stat1 == 0xff) && (timeout > 20)) 598 mask &= ~0x02; 599 } 600 ata_udelay(100000); 601 } 602 603 if (bootverbose) 604 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n", 605 stat0, stat1, ch->devices, 606 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 607 } 608 609 /* must be called with ATA channel locked and state_mtx held */ 610 int 611 ata_generic_status(device_t dev) 612 { 613 struct ata_channel *ch = device_get_softc(dev); 614 615 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 616 DELAY(100); 617 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 618 return 0; 619 } 620 return 1; 621 } 622 623 static int 624 ata_wait(struct ata_channel *ch, struct ata_device *atadev, u_int8_t mask) 625 { 626 u_int8_t status; 627 int timeout = 0; 628 629 DELAY(1); 630 631 /* wait at max 1 second for device to get !BUSY */ 632 while (timeout < 1000000) { 633 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 634 635 /* if drive fails status, reselect the drive and try again */ 636 if (status == 0xff) { 637 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 638 timeout += 1000; 639 DELAY(1000); 640 continue; 641 } 642 643 /* are we done ? */ 644 if (!(status & ATA_S_BUSY)) 645 break; 646 647 if (timeout > 1000) { 648 timeout += 1000; 649 DELAY(1000); 650 } 651 else { 652 timeout += 10; 653 DELAY(10); 654 } 655 } 656 if (timeout >= 1000000) 657 return -2; 658 if (!mask) 659 return (status & ATA_S_ERROR); 660 661 DELAY(1); 662 663 /* wait 50 msec for bits wanted */ 664 timeout = 5000; 665 while (timeout--) { 666 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 667 if ((status & mask) == mask) 668 return (status & ATA_S_ERROR); 669 DELAY(10); 670 } 671 return -3; 672 } 673 674 int 675 ata_generic_command(struct ata_request *request) 676 { 677 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 678 struct ata_device *atadev = device_get_softc(request->dev); 679 680 /* select device */ 681 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 682 683 /* ready to issue command ? */ 684 if (ata_wait(ch, atadev, 0) < 0) { 685 device_printf(request->dev, "timeout waiting to issue command\n"); 686 return -1; 687 } 688 689 /* enable interrupt */ 690 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 691 692 if (request->flags & ATA_R_ATAPI) { 693 int timeout = 5000; 694 695 /* issue packet command to controller */ 696 if (request->flags & ATA_R_DMA) { 697 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA); 698 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0); 699 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0); 700 } 701 else { 702 ATA_IDX_OUTB(ch, ATA_FEATURE, 0); 703 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize); 704 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8); 705 } 706 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD); 707 708 /* command interrupt device ? just return and wait for interrupt */ 709 if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR) 710 return 0; 711 712 /* wait for ready to write ATAPI command block */ 713 while (timeout--) { 714 int reason = ATA_IDX_INB(ch, ATA_IREASON); 715 int status = ATA_IDX_INB(ch, ATA_STATUS); 716 717 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 718 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 719 break; 720 DELAY(20); 721 } 722 if (timeout <= 0) { 723 device_printf(request->dev, "timeout waiting for ATAPI ready\n"); 724 request->result = EIO; 725 return -1; 726 } 727 728 /* this seems to be needed for some (slow) devices */ 729 DELAY(10); 730 731 /* output command block */ 732 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 733 (atadev->param.config & ATA_PROTO_MASK) == 734 ATA_PROTO_ATAPI_12 ? 6 : 8); 735 } 736 else { 737 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 738 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8); 739 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 740 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8); 741 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 742 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24); 743 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 744 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32); 745 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 746 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40); 747 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 748 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit); 749 } 750 else { 751 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 752 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 753 if (atadev->flags & ATA_D_USE_CHS) { 754 int heads, sectors; 755 756 if (atadev->param.atavalid & ATA_FLAG_54_58) { 757 heads = atadev->param.current_heads; 758 sectors = atadev->param.current_sectors; 759 } 760 else { 761 heads = atadev->param.heads; 762 sectors = atadev->param.sectors; 763 } 764 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 765 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 766 (request->u.ata.lba / (sectors * heads))); 767 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 768 (request->u.ata.lba / (sectors * heads)) >> 8); 769 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit | 770 (((request->u.ata.lba% (sectors * heads)) / 771 sectors) & 0xf)); 772 } 773 else { 774 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 775 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 776 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 777 ATA_IDX_OUTB(ch, ATA_DRIVE, 778 ATA_D_IBM | ATA_D_LBA | atadev->unit | 779 ((request->u.ata.lba >> 24) & 0x0f)); 780 } 781 } 782 783 /* issue command to controller */ 784 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 785 } 786 787 return 0; 788 } 789 790 static void 791 ata_pio_read(struct ata_request *request, int length) 792 { 793 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 794 int size = min(request->transfersize, length); 795 int resid; 796 797 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 798 ATA_IDX_INSW_STRM(ch, ATA_DATA, 799 (void*)((uintptr_t)request->data+request->donecount), 800 size / sizeof(int16_t)); 801 else 802 ATA_IDX_INSL_STRM(ch, ATA_DATA, 803 (void*)((uintptr_t)request->data+request->donecount), 804 size / sizeof(int32_t)); 805 806 if (request->transfersize < length) { 807 device_printf(request->dev, "WARNING - %s read data overrun %d>%d\n", 808 ata_cmd2str(request), length, request->transfersize); 809 for (resid = request->transfersize; resid < length; 810 resid += sizeof(int16_t)) 811 ATA_IDX_INW(ch, ATA_DATA); 812 } 813 } 814 815 static void 816 ata_pio_write(struct ata_request *request, int length) 817 { 818 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 819 int size = min(request->transfersize, length); 820 int resid; 821 822 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 823 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 824 (void*)((uintptr_t)request->data+request->donecount), 825 size / sizeof(int16_t)); 826 else 827 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 828 (void*)((uintptr_t)request->data+request->donecount), 829 size / sizeof(int32_t)); 830 831 if (request->transfersize < length) { 832 device_printf(request->dev, "WARNING - %s write data underrun %d>%d\n", 833 ata_cmd2str(request), length, request->transfersize); 834 for (resid = request->transfersize; resid < length; 835 resid += sizeof(int16_t)) 836 ATA_IDX_OUTW(ch, ATA_DATA, 0); 837 } 838 } 839