xref: /freebsd/sys/dev/ata/ata-lowlevel.c (revision acd3428b7d3e94cef0e1881c868cb4b131d4ff41)
1 /*-
2  * Copyright (c) 1998 - 2006 S�ren Schmidt <sos@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer,
10  *    without modification, immediately at the beginning of the file.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include "opt_ata.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/endian.h>
35 #include <sys/ata.h>
36 #include <sys/conf.h>
37 #include <sys/ctype.h>
38 #include <sys/bus.h>
39 #include <sys/sema.h>
40 #include <sys/taskqueue.h>
41 #include <vm/uma.h>
42 #include <machine/bus.h>
43 #include <sys/rman.h>
44 #include <dev/ata/ata-all.h>
45 #include <dev/ata/ata-pci.h>
46 #include <ata_if.h>
47 
48 /* prototypes */
49 static int ata_generic_status(device_t dev);
50 static int ata_wait(struct ata_channel *ch, struct ata_device *, u_int8_t);
51 static void ata_pio_read(struct ata_request *, int);
52 static void ata_pio_write(struct ata_request *, int);
53 
54 /*
55  * low level ATA functions
56  */
57 void
58 ata_generic_hw(device_t dev)
59 {
60     struct ata_channel *ch = device_get_softc(dev);
61 
62     ch->hw.begin_transaction = ata_begin_transaction;
63     ch->hw.end_transaction = ata_end_transaction;
64     ch->hw.status = ata_generic_status;
65     ch->hw.command = ata_generic_command;
66 }
67 
68 /* must be called with ATA channel locked and state_mtx held */
69 int
70 ata_begin_transaction(struct ata_request *request)
71 {
72     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
73     struct ata_device *atadev = device_get_softc(request->dev);
74     int dummy, error;
75 
76     ATA_DEBUG_RQ(request, "begin transaction");
77 
78     /* disable ATAPI DMA writes if HW doesn't support it */
79     if ((ch->flags & ATA_ATAPI_DMA_RO) &&
80 	((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
81 	 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
82 	request->flags &= ~ATA_R_DMA;
83 
84     /* check for 48 bit access and convert if needed */
85     ata_modify_if_48bit(request);
86 
87     switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
88 
89     /* ATA PIO data transfer and control commands */
90     default:
91 	{
92 	/* record command direction here as our request might be gone later */
93 	int write = (request->flags & ATA_R_WRITE);
94 
95 	    /* issue command */
96 	    if (ch->hw.command(request)) {
97 		device_printf(request->dev, "error issuing %s command\n",
98 			   ata_cmd2str(request));
99 		request->result = EIO;
100 		goto begin_finished;
101 	    }
102 
103 	    /* device reset doesn't interrupt */
104 	    if (request->u.ata.command == ATA_DEVICE_RESET) {
105 		int timeout = 1000000;
106 		do {
107 		    DELAY(10);
108 		    request->status = ATA_IDX_INB(ch, ATA_STATUS);
109 		} while (request->status & ATA_S_BUSY && timeout--);
110 		if (request->status & ATA_S_ERROR)
111 		    request->error = ATA_IDX_INB(ch, ATA_ERROR);
112 		goto begin_finished;
113 	    }
114 
115 	    /* if write command output the data */
116 	    if (write) {
117 		if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) {
118 		    device_printf(request->dev,
119 				  "timeout waiting for write DRQ\n");
120 		    request->result = EIO;
121 		    goto begin_finished;
122 		}
123 		ata_pio_write(request, request->transfersize);
124 	    }
125 	}
126 	goto begin_continue;
127 
128     /* ATA DMA data transfer commands */
129     case ATA_R_DMA:
130 	/* check sanity, setup SG list and DMA engine */
131 	if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
132 				   request->flags & ATA_R_READ, ch->dma->sg,
133 				   &dummy))) {
134 	    device_printf(request->dev, "setting up DMA failed\n");
135 	    request->result = error;
136 	    goto begin_finished;
137 	}
138 
139 	/* issue command */
140 	if (ch->hw.command(request)) {
141 	    device_printf(request->dev, "error issuing %s command\n",
142 		       ata_cmd2str(request));
143 	    request->result = EIO;
144 	    goto begin_finished;
145 	}
146 
147 	/* start DMA engine */
148 	if (ch->dma->start && ch->dma->start(request->dev)) {
149 	    device_printf(request->dev, "error starting DMA\n");
150 	    request->result = EIO;
151 	    goto begin_finished;
152 	}
153 	goto begin_continue;
154 
155     /* ATAPI PIO commands */
156     case ATA_R_ATAPI:
157 	/* is this just a POLL DSC command ? */
158 	if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
159 	    ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
160 	    DELAY(10);
161 	    if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
162 		request->result = EBUSY;
163 	    goto begin_finished;
164 	}
165 
166 	/* start ATAPI operation */
167 	if (ch->hw.command(request)) {
168 	    device_printf(request->dev, "error issuing ATA PACKET command\n");
169 	    request->result = EIO;
170 	    goto begin_finished;
171 	}
172 	goto begin_continue;
173 
174    /* ATAPI DMA commands */
175     case ATA_R_ATAPI|ATA_R_DMA:
176 	/* is this just a POLL DSC command ? */
177 	if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
178 	    ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
179 	    DELAY(10);
180 	    if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
181 		request->result = EBUSY;
182 	    goto begin_finished;
183 	}
184 
185 	/* check sanity, setup SG list and DMA engine */
186 	if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
187 				   request->flags & ATA_R_READ, ch->dma->sg,
188 				   &dummy))) {
189 	    device_printf(request->dev, "setting up DMA failed\n");
190 	    request->result = error;
191 	    goto begin_finished;
192 	}
193 
194 	/* start ATAPI operation */
195 	if (ch->hw.command(request)) {
196 	    device_printf(request->dev, "error issuing ATA PACKET command\n");
197 	    request->result = EIO;
198 	    goto begin_finished;
199 	}
200 
201 	/* start DMA engine */
202 	if (ch->dma->start && ch->dma->start(request->dev)) {
203 	    request->result = EIO;
204 	    goto begin_finished;
205 	}
206 	goto begin_continue;
207     }
208     /* NOT REACHED */
209     printf("ata_begin_transaction OOPS!!!\n");
210 
211 begin_finished:
212     if (ch->dma && ch->dma->flags & ATA_DMA_LOADED)
213 	ch->dma->unload(ch->dev);
214     return ATA_OP_FINISHED;
215 
216 begin_continue:
217     callout_reset(&request->callout, request->timeout * hz,
218 		  (timeout_t*)ata_timeout, request);
219     return ATA_OP_CONTINUES;
220 }
221 
222 /* must be called with ATA channel locked and state_mtx held */
223 int
224 ata_end_transaction(struct ata_request *request)
225 {
226     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
227     struct ata_device *atadev = device_get_softc(request->dev);
228     int length;
229 
230     ATA_DEBUG_RQ(request, "end transaction");
231 
232     /* clear interrupt and get status */
233     request->status = ATA_IDX_INB(ch, ATA_STATUS);
234 
235     switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
236 
237     /* ATA PIO data transfer and control commands */
238     default:
239 
240 	/* on timeouts we have no data or anything so just return */
241 	if (request->flags & ATA_R_TIMEOUT)
242 	    goto end_finished;
243 
244 	/* on control commands read back registers to the request struct */
245 	if (request->flags & ATA_R_CONTROL) {
246 	    if (atadev->flags & ATA_D_48BIT_ACTIVE) {
247 		ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB);
248 		request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8);
249 		request->u.ata.lba =
250 		    ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) |
251 		    ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) |
252 		    ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40);
253 
254 		ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
255 		request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT);
256 		request->u.ata.lba |=
257 		    (ATA_IDX_INB(ch, ATA_SECTOR) |
258 		     (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
259 		     (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16));
260 	    }
261 	    else {
262 		request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
263 		request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
264 				     (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
265 				     (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) |
266 				     ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24);
267 	    }
268 	}
269 
270 	/* if we got an error we are done with the HW */
271 	if (request->status & ATA_S_ERROR) {
272 	    request->error = ATA_IDX_INB(ch, ATA_ERROR);
273 	    goto end_finished;
274 	}
275 
276 	/* are we moving data ? */
277 	if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
278 
279 	    /* if read data get it */
280 	    if (request->flags & ATA_R_READ) {
281 		int flags = ATA_S_DRQ;
282 
283 		if (request->u.ata.command != ATA_ATAPI_IDENTIFY)
284 		    flags |= ATA_S_READY;
285 		if (ata_wait(ch, atadev, flags) < 0) {
286 		    device_printf(request->dev,
287 				  "timeout waiting for read DRQ\n");
288 		    request->result = EIO;
289 		    goto end_finished;
290 		}
291 		ata_pio_read(request, request->transfersize);
292 	    }
293 
294 	    /* update how far we've gotten */
295 	    request->donecount += request->transfersize;
296 
297 	    /* do we need a scoop more ? */
298 	    if (request->bytecount > request->donecount) {
299 
300 		/* set this transfer size according to HW capabilities */
301 		request->transfersize =
302 		    min((request->bytecount - request->donecount),
303 			request->transfersize);
304 
305 		/* if data write command, output the data */
306 		if (request->flags & ATA_R_WRITE) {
307 
308 		    /* if we get an error here we are done with the HW */
309 		    if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) {
310 			device_printf(request->dev,
311 				      "timeout waiting for write DRQ\n");
312 			request->status = ATA_IDX_INB(ch, ATA_STATUS);
313 			goto end_finished;
314 		    }
315 
316 		    /* output data and return waiting for new interrupt */
317 		    ata_pio_write(request, request->transfersize);
318 		    goto end_continue;
319 		}
320 
321 		/* if data read command, return & wait for interrupt */
322 		if (request->flags & ATA_R_READ)
323 		    goto end_continue;
324 	    }
325 	}
326 	/* done with HW */
327 	goto end_finished;
328 
329     /* ATA DMA data transfer commands */
330     case ATA_R_DMA:
331 
332 	/* stop DMA engine and get status */
333 	if (ch->dma->stop)
334 	    request->dmastat = ch->dma->stop(request->dev);
335 
336 	/* did we get error or data */
337 	if (request->status & ATA_S_ERROR)
338 	    request->error = ATA_IDX_INB(ch, ATA_ERROR);
339 	else if (request->dmastat & ATA_BMSTAT_ERROR)
340 	    request->status |= ATA_S_ERROR;
341 	else if (!(request->flags & ATA_R_TIMEOUT))
342 	    request->donecount = request->bytecount;
343 
344 	/* release SG list etc */
345 	ch->dma->unload(ch->dev);
346 
347 	/* done with HW */
348 	goto end_finished;
349 
350     /* ATAPI PIO commands */
351     case ATA_R_ATAPI:
352 	length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
353 
354 	/* on timeouts we have no data or anything so just return */
355 	if (request->flags & ATA_R_TIMEOUT)
356 	    goto end_finished;
357 
358 	switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
359 		(request->status & ATA_S_DRQ)) {
360 
361 	case ATAPI_P_CMDOUT:
362 	    /* this seems to be needed for some (slow) devices */
363 	    DELAY(10);
364 
365 	    if (!(request->status & ATA_S_DRQ)) {
366 		device_printf(request->dev, "command interrupt without DRQ\n");
367 		request->status = ATA_S_ERROR;
368 		goto end_finished;
369 	    }
370 	    ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
371 			       (atadev->param.config &
372 				ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8);
373 	    /* return wait for interrupt */
374 	    goto end_continue;
375 
376 	case ATAPI_P_WRITE:
377 	    if (request->flags & ATA_R_READ) {
378 		request->status = ATA_S_ERROR;
379 		device_printf(request->dev,
380 			      "%s trying to write on read buffer\n",
381 			   ata_cmd2str(request));
382 		goto end_finished;
383 		break;
384 	    }
385 	    ata_pio_write(request, length);
386 	    request->donecount += length;
387 
388 	    /* set next transfer size according to HW capabilities */
389 	    request->transfersize = min((request->bytecount-request->donecount),
390 					request->transfersize);
391 	    /* return wait for interrupt */
392 	    goto end_continue;
393 
394 	case ATAPI_P_READ:
395 	    if (request->flags & ATA_R_WRITE) {
396 		request->status = ATA_S_ERROR;
397 		device_printf(request->dev,
398 			      "%s trying to read on write buffer\n",
399 			   ata_cmd2str(request));
400 		goto end_finished;
401 	    }
402 	    ata_pio_read(request, length);
403 	    request->donecount += length;
404 
405 	    /* set next transfer size according to HW capabilities */
406 	    request->transfersize = min((request->bytecount-request->donecount),
407 					request->transfersize);
408 	    /* return wait for interrupt */
409 	    goto end_continue;
410 
411 	case ATAPI_P_DONEDRQ:
412 	    device_printf(request->dev,
413 			  "WARNING - %s DONEDRQ non conformant device\n",
414 			  ata_cmd2str(request));
415 	    if (request->flags & ATA_R_READ) {
416 		ata_pio_read(request, length);
417 		request->donecount += length;
418 	    }
419 	    else if (request->flags & ATA_R_WRITE) {
420 		ata_pio_write(request, length);
421 		request->donecount += length;
422 	    }
423 	    else
424 		request->status = ATA_S_ERROR;
425 	    /* FALLTHROUGH */
426 
427 	case ATAPI_P_ABORT:
428 	case ATAPI_P_DONE:
429 	    if (request->status & (ATA_S_ERROR | ATA_S_DWF))
430 		request->error = ATA_IDX_INB(ch, ATA_ERROR);
431 	    goto end_finished;
432 
433 	default:
434 	    device_printf(request->dev, "unknown transfer phase\n");
435 	    request->status = ATA_S_ERROR;
436 	}
437 
438 	/* done with HW */
439 	goto end_finished;
440 
441     /* ATAPI DMA commands */
442     case ATA_R_ATAPI|ATA_R_DMA:
443 
444 	/* stop DMA engine and get status */
445 	if (ch->dma->stop)
446 	    request->dmastat = ch->dma->stop(request->dev);
447 
448 	/* did we get error or data */
449 	if (request->status & (ATA_S_ERROR | ATA_S_DWF))
450 	    request->error = ATA_IDX_INB(ch, ATA_ERROR);
451 	else if (request->dmastat & ATA_BMSTAT_ERROR)
452 	    request->status |= ATA_S_ERROR;
453 	else if (!(request->flags & ATA_R_TIMEOUT))
454 	    request->donecount = request->bytecount;
455 
456 	/* release SG list etc */
457 	ch->dma->unload(ch->dev);
458 
459 	/* done with HW */
460 	goto end_finished;
461     }
462     /* NOT REACHED */
463     printf("ata_end_transaction OOPS!!\n");
464 
465 end_finished:
466     callout_stop(&request->callout);
467     return ATA_OP_FINISHED;
468 
469 end_continue:
470     return ATA_OP_CONTINUES;
471 }
472 
473 /* must be called with ATA channel locked and state_mtx held */
474 void
475 ata_generic_reset(device_t dev)
476 {
477     struct ata_channel *ch = device_get_softc(dev);
478 
479     u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0;
480     u_int8_t err = 0, lsb = 0, msb = 0;
481     int mask = 0, timeout;
482 
483     /* do we have any signs of ATA/ATAPI HW being present ? */
484     ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER);
485     DELAY(10);
486     ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
487     if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) {
488 	stat0 = ATA_S_BUSY;
489 	mask |= 0x01;
490     }
491 
492     /* in some setups we dont want to test for a slave */
493     if (!(ch->flags & ATA_NO_SLAVE)) {
494 	ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_SLAVE);
495 	DELAY(10);
496 	ostat1 = ATA_IDX_INB(ch, ATA_STATUS);
497 	if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) {
498 	    stat1 = ATA_S_BUSY;
499 	    mask |= 0x02;
500 	}
501     }
502 
503     if (bootverbose)
504 	device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n",
505 		      mask, ostat0, ostat1);
506 
507     /* if nothing showed up there is no need to get any further */
508     /* XXX SOS is that too strong?, we just might loose devices here */
509     ch->devices = 0;
510     if (!mask)
511 	return;
512 
513     /* reset (both) devices on this channel */
514     ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER);
515     DELAY(10);
516     ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET);
517     ata_udelay(10000);
518     ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS);
519     ata_udelay(100000);
520     ATA_IDX_INB(ch, ATA_ERROR);
521 
522     /* wait for BUSY to go inactive */
523     for (timeout = 0; timeout < 310; timeout++) {
524 	if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) {
525 	    ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
526 	    DELAY(10);
527 	    err = ATA_IDX_INB(ch, ATA_ERROR);
528 	    lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
529 	    msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
530 	    stat0 = ATA_IDX_INB(ch, ATA_STATUS);
531 	    if (bootverbose)
532 		device_printf(dev,
533 			      "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
534 			      stat0, err, lsb, msb);
535 	    if (stat0 == err && lsb == err && msb == err &&
536 		timeout > (stat0 & ATA_S_BUSY ? 100 : 10))
537 		mask &= ~0x01;
538 	    if (!(stat0 & ATA_S_BUSY)) {
539 		if ((err & 0x7f) == ATA_E_ILI) {
540 		    if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
541 			ch->devices |= ATA_ATAPI_MASTER;
542 		    }
543 		    else if (stat0 & ATA_S_READY) {
544 			ch->devices |= ATA_ATA_MASTER;
545 		    }
546 		}
547 		else if ((stat0 & 0x0f) && err == lsb && err == msb) {
548 		    stat0 |= ATA_S_BUSY;
549 		}
550 	    }
551 	}
552 
553 	if ((mask & 0x02) && (stat1 & ATA_S_BUSY) &&
554 	    !((mask & 0x01) && (stat0 & ATA_S_BUSY))) {
555 	    ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
556 	    DELAY(10);
557 	    err = ATA_IDX_INB(ch, ATA_ERROR);
558 	    lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
559 	    msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
560 	    stat1 = ATA_IDX_INB(ch, ATA_STATUS);
561 	    if (bootverbose)
562 		device_printf(dev,
563 			      "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
564 			      stat1, err, lsb, msb);
565 	    if (stat1 == err && lsb == err && msb == err &&
566 		timeout > (stat1 & ATA_S_BUSY ? 100 : 10))
567 		mask &= ~0x02;
568 	    if (!(stat1 & ATA_S_BUSY)) {
569 		if ((err & 0x7f) == ATA_E_ILI) {
570 		    if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
571 			ch->devices |= ATA_ATAPI_SLAVE;
572 		    }
573 		    else if (stat1 & ATA_S_READY) {
574 			ch->devices |= ATA_ATA_SLAVE;
575 		    }
576 		}
577 		else if ((stat1 & 0x0f) && err == lsb && err == msb) {
578 		    stat1 |= ATA_S_BUSY;
579 		}
580 	    }
581 	}
582 
583 	if (mask == 0x00)       /* nothing to wait for */
584 	    break;
585 	if (mask == 0x01)       /* wait for master only */
586 	    if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10))
587 		break;
588 	if (mask == 0x02)       /* wait for slave only */
589 	    if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10))
590 		break;
591 	if (mask == 0x03) {     /* wait for both master & slave */
592 	    if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY))
593 		break;
594 	    if ((stat0 == 0xff) && (timeout > 20))
595 		mask &= ~0x01;
596 	    if ((stat1 == 0xff) && (timeout > 20))
597 		mask &= ~0x02;
598 	}
599 	ata_udelay(100000);
600     }
601 
602     if (bootverbose)
603 	device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n",
604 		      stat0, stat1, ch->devices,
605 		      "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
606 }
607 
608 /* must be called with ATA channel locked and state_mtx held */
609 int
610 ata_generic_status(device_t dev)
611 {
612     struct ata_channel *ch = device_get_softc(dev);
613 
614     if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
615 	DELAY(100);
616 	if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
617 	    return 0;
618     }
619     return 1;
620 }
621 
622 static int
623 ata_wait(struct ata_channel *ch, struct ata_device *atadev, u_int8_t mask)
624 {
625     u_int8_t status;
626     int timeout = 0;
627 
628     DELAY(1);
629 
630     /* wait at max 1 second for device to get !BUSY */
631     while (timeout < 1000000) {
632 	status = ATA_IDX_INB(ch, ATA_ALTSTAT);
633 
634 	/* if drive fails status, reselect the drive and try again */
635 	if (status == 0xff) {
636 	    ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
637 	    timeout += 1000;
638 	    DELAY(1000);
639 	    continue;
640 	}
641 
642 	/* are we done ? */
643 	if (!(status & ATA_S_BUSY))
644 	    break;
645 
646 	if (timeout > 1000) {
647 	    timeout += 1000;
648 	    DELAY(1000);
649 	}
650 	else {
651 	    timeout += 10;
652 	    DELAY(10);
653 	}
654     }
655     if (timeout >= 1000000)
656 	return -2;
657     if (!mask)
658 	return (status & ATA_S_ERROR);
659 
660     DELAY(1);
661 
662     /* wait 50 msec for bits wanted */
663     timeout = 5000;
664     while (timeout--) {
665 	status = ATA_IDX_INB(ch, ATA_ALTSTAT);
666 	if ((status & mask) == mask)
667 	    return (status & ATA_S_ERROR);
668 	DELAY(10);
669     }
670     return -3;
671 }
672 
673 int
674 ata_generic_command(struct ata_request *request)
675 {
676     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
677     struct ata_device *atadev = device_get_softc(request->dev);
678 
679     /* select device */
680     ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit);
681 
682     /* ready to issue command ? */
683     if (ata_wait(ch, atadev, 0) < 0) {
684 	device_printf(request->dev, "timeout waiting to issue command\n");
685 	return -1;
686     }
687 
688     /* enable interrupt */
689     ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
690 
691     if (request->flags & ATA_R_ATAPI) {
692 	int timeout = 5000;
693 
694 	/* issue packet command to controller */
695 	if (request->flags & ATA_R_DMA) {
696 	    ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA);
697 	    ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0);
698 	    ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0);
699 	}
700 	else {
701 	    ATA_IDX_OUTB(ch, ATA_FEATURE, 0);
702 	    ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize);
703 	    ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8);
704 	}
705 	ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD);
706 
707 	/* command interrupt device ? just return and wait for interrupt */
708 	if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR)
709 	    return 0;
710 
711 	/* wait for ready to write ATAPI command block */
712 	while (timeout--) {
713 	    int reason = ATA_IDX_INB(ch, ATA_IREASON);
714 	    int status = ATA_IDX_INB(ch, ATA_STATUS);
715 
716 	    if (((reason & (ATA_I_CMD | ATA_I_IN)) |
717 		 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
718 		break;
719 	    DELAY(20);
720 	}
721 	if (timeout <= 0) {
722 	    device_printf(request->dev, "timeout waiting for ATAPI ready\n");
723 	    request->result = EIO;
724 	    return -1;
725 	}
726 
727 	/* this seems to be needed for some (slow) devices */
728 	DELAY(10);
729 
730 	/* output command block */
731 	ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
732 			   (atadev->param.config & ATA_PROTO_MASK) ==
733 			   ATA_PROTO_ATAPI_12 ? 6 : 8);
734     }
735     else {
736 	if (atadev->flags & ATA_D_48BIT_ACTIVE) {
737 	    ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8);
738 	    ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
739 	    ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8);
740 	    ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
741 	    ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24);
742 	    ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
743 	    ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32);
744 	    ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
745 	    ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40);
746 	    ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
747 	    ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit);
748 	}
749 	else {
750 	    ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
751 	    ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
752 	    if (atadev->flags & ATA_D_USE_CHS) {
753 		int heads, sectors;
754 
755 		if (atadev->param.atavalid & ATA_FLAG_54_58) {
756 		    heads = atadev->param.current_heads;
757 		    sectors = atadev->param.current_sectors;
758 		}
759 		else {
760 		    heads = atadev->param.heads;
761 		    sectors = atadev->param.sectors;
762 		}
763 		ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
764 		ATA_IDX_OUTB(ch, ATA_CYL_LSB,
765 			     (request->u.ata.lba / (sectors * heads)));
766 		ATA_IDX_OUTB(ch, ATA_CYL_MSB,
767 			     (request->u.ata.lba / (sectors * heads)) >> 8);
768 		ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit |
769 			     (((request->u.ata.lba% (sectors * heads)) /
770 			       sectors) & 0xf));
771 	    }
772 	    else {
773 		ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
774 		ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
775 		ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
776 		ATA_IDX_OUTB(ch, ATA_DRIVE,
777 			     ATA_D_IBM | ATA_D_LBA | atadev->unit |
778 			     ((request->u.ata.lba >> 24) & 0x0f));
779 	    }
780 	}
781 
782 	/* issue command to controller */
783 	ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
784     }
785 
786     return 0;
787 }
788 
789 static void
790 ata_pio_read(struct ata_request *request, int length)
791 {
792     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
793     int size = min(request->transfersize, length);
794     int resid;
795 
796     if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
797 	ATA_IDX_INSW_STRM(ch, ATA_DATA,
798 			  (void*)((uintptr_t)request->data+request->donecount),
799 			  size / sizeof(int16_t));
800     else
801 	ATA_IDX_INSL_STRM(ch, ATA_DATA,
802 			  (void*)((uintptr_t)request->data+request->donecount),
803 			  size / sizeof(int32_t));
804 
805     if (request->transfersize < length) {
806 	device_printf(request->dev, "WARNING - %s read data overrun %d>%d\n",
807 		   ata_cmd2str(request), length, request->transfersize);
808 	for (resid = request->transfersize; resid < length;
809 	     resid += sizeof(int16_t))
810 	    ATA_IDX_INW(ch, ATA_DATA);
811     }
812 }
813 
814 static void
815 ata_pio_write(struct ata_request *request, int length)
816 {
817     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
818     int size = min(request->transfersize, length);
819     int resid;
820 
821     if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
822 	ATA_IDX_OUTSW_STRM(ch, ATA_DATA,
823 			   (void*)((uintptr_t)request->data+request->donecount),
824 			   size / sizeof(int16_t));
825     else
826 	ATA_IDX_OUTSL_STRM(ch, ATA_DATA,
827 			   (void*)((uintptr_t)request->data+request->donecount),
828 			   size / sizeof(int32_t));
829 
830     if (request->transfersize < length) {
831 	device_printf(request->dev, "WARNING - %s write data underrun %d>%d\n",
832 		   ata_cmd2str(request), length, request->transfersize);
833 	for (resid = request->transfersize; resid < length;
834 	     resid += sizeof(int16_t))
835 	    ATA_IDX_OUTW(ch, ATA_DATA, 0);
836     }
837 }
838