1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/endian.h> 35 #include <sys/ata.h> 36 #include <sys/conf.h> 37 #include <sys/ctype.h> 38 #include <sys/bus.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/ata/ata-all.h> 45 #include <dev/ata/ata-pci.h> 46 #include <ata_if.h> 47 48 /* prototypes */ 49 static int ata_generic_status(device_t dev); 50 static int ata_wait(struct ata_channel *ch, int unit, u_int8_t); 51 static void ata_pio_read(struct ata_request *, int); 52 static void ata_pio_write(struct ata_request *, int); 53 static void ata_tf_read(struct ata_request *); 54 static void ata_tf_write(struct ata_request *); 55 56 /* 57 * low level ATA functions 58 */ 59 void 60 ata_generic_hw(device_t dev) 61 { 62 struct ata_channel *ch = device_get_softc(dev); 63 64 ch->hw.begin_transaction = ata_begin_transaction; 65 ch->hw.end_transaction = ata_end_transaction; 66 ch->hw.status = ata_generic_status; 67 ch->hw.softreset = NULL; 68 ch->hw.command = ata_generic_command; 69 ch->hw.tf_read = ata_tf_read; 70 ch->hw.tf_write = ata_tf_write; 71 ch->hw.pm_read = NULL; 72 ch->hw.pm_write = NULL; 73 } 74 75 /* must be called with ATA channel locked and state_mtx held */ 76 int 77 ata_begin_transaction(struct ata_request *request) 78 { 79 struct ata_channel *ch = device_get_softc(request->parent); 80 int dummy, error; 81 82 ATA_DEBUG_RQ(request, "begin transaction"); 83 84 /* disable ATAPI DMA writes if HW doesn't support it */ 85 if ((ch->flags & ATA_NO_ATAPI_DMA) && 86 (request->flags & ATA_R_ATAPI) == ATA_R_ATAPI) 87 request->flags &= ~ATA_R_DMA; 88 if ((ch->flags & ATA_ATAPI_DMA_RO) && 89 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 90 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 91 request->flags &= ~ATA_R_DMA; 92 93 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 94 95 /* ATA PIO data transfer and control commands */ 96 default: 97 { 98 /* record command direction here as our request might be gone later */ 99 int write = (request->flags & ATA_R_WRITE); 100 101 /* issue command */ 102 if (ch->hw.command(request)) { 103 device_printf(request->parent, "error issuing %s command\n", 104 ata_cmd2str(request)); 105 request->result = EIO; 106 goto begin_finished; 107 } 108 109 /* device reset doesn't interrupt */ 110 if (request->u.ata.command == ATA_DEVICE_RESET) { 111 112 int timeout = 1000000; 113 do { 114 DELAY(10); 115 request->status = ATA_IDX_INB(ch, ATA_STATUS); 116 } while (request->status & ATA_S_BUSY && timeout--); 117 if (request->status & ATA_S_ERROR) 118 request->error = ATA_IDX_INB(ch, ATA_ERROR); 119 goto begin_finished; 120 } 121 122 /* if write command output the data */ 123 if (write) { 124 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) { 125 device_printf(request->parent, 126 "timeout waiting for write DRQ\n"); 127 request->result = EIO; 128 goto begin_finished; 129 } 130 ata_pio_write(request, request->transfersize); 131 } 132 } 133 goto begin_continue; 134 135 /* ATA DMA data transfer commands */ 136 case ATA_R_DMA: 137 /* check sanity, setup SG list and DMA engine */ 138 if ((error = ch->dma.load(request, NULL, &dummy))) { 139 device_printf(request->parent, "setting up DMA failed\n"); 140 request->result = error; 141 goto begin_finished; 142 } 143 144 /* start DMA engine if necessary */ 145 if ((ch->flags & ATA_DMA_BEFORE_CMD) && 146 ch->dma.start && ch->dma.start(request)) { 147 device_printf(request->parent, "error starting DMA\n"); 148 request->result = EIO; 149 goto begin_finished; 150 } 151 152 /* issue command */ 153 if (ch->hw.command(request)) { 154 device_printf(request->parent, "error issuing %s command\n", 155 ata_cmd2str(request)); 156 request->result = EIO; 157 goto begin_finished; 158 } 159 160 /* start DMA engine */ 161 if (!(ch->flags & ATA_DMA_BEFORE_CMD) && 162 ch->dma.start && ch->dma.start(request)) { 163 device_printf(request->parent, "error starting DMA\n"); 164 request->result = EIO; 165 goto begin_finished; 166 } 167 goto begin_continue; 168 169 /* ATAPI PIO commands */ 170 case ATA_R_ATAPI: 171 /* is this just a POLL DSC command ? */ 172 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 173 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit)); 174 DELAY(10); 175 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 176 request->result = EBUSY; 177 goto begin_finished; 178 } 179 180 /* start ATAPI operation */ 181 if (ch->hw.command(request)) { 182 device_printf(request->parent, "error issuing ATA PACKET command\n"); 183 request->result = EIO; 184 goto begin_finished; 185 } 186 goto begin_continue; 187 188 /* ATAPI DMA commands */ 189 case ATA_R_ATAPI|ATA_R_DMA: 190 /* is this just a POLL DSC command ? */ 191 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 192 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit)); 193 DELAY(10); 194 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 195 request->result = EBUSY; 196 goto begin_finished; 197 } 198 199 /* check sanity, setup SG list and DMA engine */ 200 if ((error = ch->dma.load(request, NULL, &dummy))) { 201 device_printf(request->parent, "setting up DMA failed\n"); 202 request->result = error; 203 goto begin_finished; 204 } 205 206 /* start ATAPI operation */ 207 if (ch->hw.command(request)) { 208 device_printf(request->parent, "error issuing ATA PACKET command\n"); 209 request->result = EIO; 210 goto begin_finished; 211 } 212 213 /* start DMA engine */ 214 if (ch->dma.start && ch->dma.start(request)) { 215 request->result = EIO; 216 goto begin_finished; 217 } 218 goto begin_continue; 219 } 220 /* NOT REACHED */ 221 printf("ata_begin_transaction OOPS!!!\n"); 222 223 begin_finished: 224 if (ch->dma.unload) { 225 ch->dma.unload(request); 226 } 227 return ATA_OP_FINISHED; 228 229 begin_continue: 230 callout_reset(&request->callout, request->timeout * hz, 231 (timeout_t*)ata_timeout, request); 232 return ATA_OP_CONTINUES; 233 } 234 235 /* must be called with ATA channel locked and state_mtx held */ 236 int 237 ata_end_transaction(struct ata_request *request) 238 { 239 struct ata_channel *ch = device_get_softc(request->parent); 240 int length; 241 242 ATA_DEBUG_RQ(request, "end transaction"); 243 244 /* clear interrupt and get status */ 245 request->status = ATA_IDX_INB(ch, ATA_STATUS); 246 247 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 248 249 /* ATA PIO data transfer and control commands */ 250 default: 251 252 /* on timeouts we have no data or anything so just return */ 253 if (request->flags & ATA_R_TIMEOUT) 254 goto end_finished; 255 256 /* on control commands read back registers to the request struct */ 257 if (request->flags & ATA_R_CONTROL) { 258 ch->hw.tf_read(request); 259 } 260 261 /* if we got an error we are done with the HW */ 262 if (request->status & ATA_S_ERROR) { 263 request->error = ATA_IDX_INB(ch, ATA_ERROR); 264 goto end_finished; 265 } 266 267 /* are we moving data ? */ 268 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 269 270 /* if read data get it */ 271 if (request->flags & ATA_R_READ) { 272 int flags = ATA_S_DRQ; 273 274 if (request->u.ata.command != ATA_ATAPI_IDENTIFY) 275 flags |= ATA_S_READY; 276 if (ata_wait(ch, request->unit, flags) < 0) { 277 device_printf(request->parent, 278 "timeout waiting for read DRQ\n"); 279 request->result = EIO; 280 goto end_finished; 281 } 282 ata_pio_read(request, request->transfersize); 283 } 284 285 /* update how far we've gotten */ 286 request->donecount += request->transfersize; 287 288 /* do we need a scoop more ? */ 289 if (request->bytecount > request->donecount) { 290 291 /* set this transfer size according to HW capabilities */ 292 request->transfersize = 293 min((request->bytecount - request->donecount), 294 request->transfersize); 295 296 /* if data write command, output the data */ 297 if (request->flags & ATA_R_WRITE) { 298 299 /* if we get an error here we are done with the HW */ 300 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) { 301 device_printf(request->parent, 302 "timeout waiting for write DRQ\n"); 303 request->status = ATA_IDX_INB(ch, ATA_STATUS); 304 goto end_finished; 305 } 306 307 /* output data and return waiting for new interrupt */ 308 ata_pio_write(request, request->transfersize); 309 goto end_continue; 310 } 311 312 /* if data read command, return & wait for interrupt */ 313 if (request->flags & ATA_R_READ) 314 goto end_continue; 315 } 316 } 317 /* done with HW */ 318 goto end_finished; 319 320 /* ATA DMA data transfer commands */ 321 case ATA_R_DMA: 322 323 /* stop DMA engine and get status */ 324 if (ch->dma.stop) 325 request->dma->status = ch->dma.stop(request); 326 327 /* did we get error or data */ 328 if (request->status & ATA_S_ERROR) 329 request->error = ATA_IDX_INB(ch, ATA_ERROR); 330 else if (request->dma->status & ATA_BMSTAT_ERROR) 331 request->status |= ATA_S_ERROR; 332 else if (!(request->flags & ATA_R_TIMEOUT)) 333 request->donecount = request->bytecount; 334 335 /* release SG list etc */ 336 ch->dma.unload(request); 337 338 /* done with HW */ 339 goto end_finished; 340 341 /* ATAPI PIO commands */ 342 case ATA_R_ATAPI: 343 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 344 345 /* on timeouts we have no data or anything so just return */ 346 if (request->flags & ATA_R_TIMEOUT) 347 goto end_finished; 348 349 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 350 (request->status & ATA_S_DRQ)) { 351 352 case ATAPI_P_CMDOUT: 353 /* this seems to be needed for some (slow) devices */ 354 DELAY(10); 355 356 if (!(request->status & ATA_S_DRQ)) { 357 device_printf(request->parent, "command interrupt without DRQ\n"); 358 request->status = ATA_S_ERROR; 359 goto end_finished; 360 } 361 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 362 (request->flags & ATA_R_ATAPI16) ? 8 : 6); 363 /* return wait for interrupt */ 364 goto end_continue; 365 366 case ATAPI_P_WRITE: 367 if (request->flags & ATA_R_READ) { 368 request->status = ATA_S_ERROR; 369 device_printf(request->parent, 370 "%s trying to write on read buffer\n", 371 ata_cmd2str(request)); 372 goto end_finished; 373 } 374 ata_pio_write(request, length); 375 request->donecount += length; 376 377 /* set next transfer size according to HW capabilities */ 378 request->transfersize = min((request->bytecount-request->donecount), 379 request->transfersize); 380 /* return wait for interrupt */ 381 goto end_continue; 382 383 case ATAPI_P_READ: 384 if (request->flags & ATA_R_WRITE) { 385 request->status = ATA_S_ERROR; 386 device_printf(request->parent, 387 "%s trying to read on write buffer\n", 388 ata_cmd2str(request)); 389 goto end_finished; 390 } 391 ata_pio_read(request, length); 392 request->donecount += length; 393 394 /* set next transfer size according to HW capabilities */ 395 request->transfersize = min((request->bytecount-request->donecount), 396 request->transfersize); 397 /* return wait for interrupt */ 398 goto end_continue; 399 400 case ATAPI_P_DONEDRQ: 401 device_printf(request->parent, 402 "WARNING - %s DONEDRQ non conformant device\n", 403 ata_cmd2str(request)); 404 if (request->flags & ATA_R_READ) { 405 ata_pio_read(request, length); 406 request->donecount += length; 407 } 408 else if (request->flags & ATA_R_WRITE) { 409 ata_pio_write(request, length); 410 request->donecount += length; 411 } 412 else 413 request->status = ATA_S_ERROR; 414 /* FALLTHROUGH */ 415 416 case ATAPI_P_ABORT: 417 case ATAPI_P_DONE: 418 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 419 request->error = ATA_IDX_INB(ch, ATA_ERROR); 420 goto end_finished; 421 422 default: 423 device_printf(request->parent, "unknown transfer phase\n"); 424 request->status = ATA_S_ERROR; 425 } 426 427 /* done with HW */ 428 goto end_finished; 429 430 /* ATAPI DMA commands */ 431 case ATA_R_ATAPI|ATA_R_DMA: 432 433 /* stop DMA engine and get status */ 434 if (ch->dma.stop) 435 request->dma->status = ch->dma.stop(request); 436 437 /* did we get error or data */ 438 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 439 request->error = ATA_IDX_INB(ch, ATA_ERROR); 440 else if (request->dma->status & ATA_BMSTAT_ERROR) 441 request->status |= ATA_S_ERROR; 442 else if (!(request->flags & ATA_R_TIMEOUT)) 443 request->donecount = request->bytecount; 444 445 /* release SG list etc */ 446 ch->dma.unload(request); 447 448 /* done with HW */ 449 goto end_finished; 450 } 451 /* NOT REACHED */ 452 printf("ata_end_transaction OOPS!!\n"); 453 454 end_finished: 455 callout_stop(&request->callout); 456 return ATA_OP_FINISHED; 457 458 end_continue: 459 return ATA_OP_CONTINUES; 460 } 461 462 /* must be called with ATA channel locked and state_mtx held */ 463 void 464 ata_generic_reset(device_t dev) 465 { 466 struct ata_channel *ch = device_get_softc(dev); 467 468 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0; 469 u_int8_t err = 0, lsb = 0, msb = 0; 470 int mask = 0, timeout; 471 472 /* do we have any signs of ATA/ATAPI HW being present ? */ 473 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 474 DELAY(10); 475 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 476 if (((ostat0 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) && 477 ostat0 != 0xa5) { 478 stat0 = ATA_S_BUSY; 479 mask |= 0x01; 480 } 481 482 /* in some setups we dont want to test for a slave */ 483 if (!(ch->flags & ATA_NO_SLAVE)) { 484 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_SLAVE)); 485 DELAY(10); 486 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 487 if (((ostat1 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) && 488 ostat1 != 0xa5) { 489 stat1 = ATA_S_BUSY; 490 mask |= 0x02; 491 } 492 } 493 494 if (bootverbose) 495 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 496 mask, ostat0, ostat1); 497 498 /* if nothing showed up there is no need to get any further */ 499 /* XXX SOS is that too strong?, we just might loose devices here */ 500 ch->devices = 0; 501 if (!mask) 502 return; 503 504 /* reset (both) devices on this channel */ 505 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 506 DELAY(10); 507 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 508 ata_udelay(10000); 509 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 510 ata_udelay(100000); 511 ATA_IDX_INB(ch, ATA_ERROR); 512 513 /* wait for BUSY to go inactive */ 514 for (timeout = 0; timeout < 310; timeout++) { 515 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) { 516 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_MASTER)); 517 DELAY(10); 518 if (ch->flags & ATA_STATUS_IS_LONG) 519 stat0 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff; 520 else 521 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 522 err = ATA_IDX_INB(ch, ATA_ERROR); 523 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 524 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 525 if (bootverbose) 526 device_printf(dev, 527 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 528 stat0, err, lsb, msb); 529 if (stat0 == err && lsb == err && msb == err && 530 timeout > (stat0 & ATA_S_BUSY ? 100 : 10)) 531 mask &= ~0x01; 532 if (!(stat0 & ATA_S_BUSY)) { 533 if ((err & 0x7f) == ATA_E_ILI) { 534 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 535 ch->devices |= ATA_ATAPI_MASTER; 536 } 537 else if (lsb == 0 && msb == 0 && (stat0 & ATA_S_READY)) { 538 ch->devices |= ATA_ATA_MASTER; 539 } 540 } 541 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 542 stat0 |= ATA_S_BUSY; 543 } 544 } 545 } 546 547 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) && 548 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) { 549 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_SLAVE)); 550 DELAY(10); 551 if (ch->flags & ATA_STATUS_IS_LONG) 552 stat1 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff; 553 else 554 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 555 err = ATA_IDX_INB(ch, ATA_ERROR); 556 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 557 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 558 if (bootverbose) 559 device_printf(dev, 560 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 561 stat1, err, lsb, msb); 562 if (stat1 == err && lsb == err && msb == err && 563 timeout > (stat1 & ATA_S_BUSY ? 100 : 10)) 564 mask &= ~0x02; 565 if (!(stat1 & ATA_S_BUSY)) { 566 if ((err & 0x7f) == ATA_E_ILI) { 567 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 568 ch->devices |= ATA_ATAPI_SLAVE; 569 } 570 else if (lsb == 0 && msb == 0 && (stat1 & ATA_S_READY)) { 571 ch->devices |= ATA_ATA_SLAVE; 572 } 573 } 574 else if ((stat1 & 0x0f) && err == lsb && err == msb) { 575 stat1 |= ATA_S_BUSY; 576 } 577 } 578 } 579 580 if ((ch->flags & ATA_KNOWN_PRESENCE) == 0 && 581 timeout > ((mask == 0x03) ? 20 : 10)) { 582 if ((mask & 0x01) && stat0 == 0xff) 583 mask &= ~0x01; 584 if ((mask & 0x02) && stat1 == 0xff) 585 mask &= ~0x02; 586 } 587 if (((mask & 0x01) == 0 || !(stat0 & ATA_S_BUSY)) && 588 ((mask & 0x02) == 0 || !(stat1 & ATA_S_BUSY))) 589 break; 590 ata_udelay(100000); 591 } 592 593 if (bootverbose) 594 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%x\n", 595 stat0, stat1, ch->devices); 596 } 597 598 /* must be called with ATA channel locked and state_mtx held */ 599 int 600 ata_generic_status(device_t dev) 601 { 602 struct ata_channel *ch = device_get_softc(dev); 603 604 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 605 DELAY(100); 606 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 607 return 0; 608 } 609 return 1; 610 } 611 612 static int 613 ata_wait(struct ata_channel *ch, int unit, u_int8_t mask) 614 { 615 u_int8_t status; 616 int timeout = 0; 617 618 DELAY(1); 619 620 /* wait at max 1 second for device to get !BUSY */ 621 while (timeout < 1000000) { 622 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 623 624 /* if drive fails status, reselect the drive and try again */ 625 if (status == 0xff) { 626 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(unit)); 627 timeout += 1000; 628 DELAY(1000); 629 continue; 630 } 631 632 /* are we done ? */ 633 if (!(status & ATA_S_BUSY)) 634 break; 635 636 if (timeout > 1000) { 637 timeout += 1000; 638 DELAY(1000); 639 } 640 else { 641 timeout += 10; 642 DELAY(10); 643 } 644 } 645 if (timeout >= 1000000) 646 return -2; 647 if (!mask) 648 return (status & ATA_S_ERROR); 649 650 DELAY(1); 651 652 /* wait 50 msec for bits wanted */ 653 timeout = 5000; 654 while (timeout--) { 655 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 656 if ((status & mask) == mask) 657 return (status & ATA_S_ERROR); 658 DELAY(10); 659 } 660 return -3; 661 } 662 663 int 664 ata_generic_command(struct ata_request *request) 665 { 666 struct ata_channel *ch = device_get_softc(request->parent); 667 668 /* select device */ 669 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit)); 670 671 /* ready to issue command ? */ 672 if (ata_wait(ch, request->unit, 0) < 0) { 673 device_printf(request->parent, "timeout waiting to issue command\n"); 674 request->flags |= ATA_R_TIMEOUT; 675 return (-1); 676 } 677 678 /* enable interrupt */ 679 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 680 681 if (request->flags & ATA_R_ATAPI) { 682 int timeout = 5000; 683 int res; 684 685 /* issue packet command to controller */ 686 if (request->flags & ATA_R_DMA) { 687 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA); 688 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0); 689 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0); 690 } 691 else { 692 ATA_IDX_OUTB(ch, ATA_FEATURE, 0); 693 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize); 694 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8); 695 } 696 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD); 697 698 /* command interrupt device ? just return and wait for interrupt */ 699 if (request->flags & ATA_R_ATAPI_INTR) 700 return (0); 701 702 /* command processed ? */ 703 res = ata_wait(ch, request->unit, 0); 704 if (res != 0) { 705 if (res < 0) { 706 device_printf(request->parent, 707 "timeout waiting for PACKET command\n"); 708 request->flags |= ATA_R_TIMEOUT; 709 } 710 return (-1); 711 } 712 /* wait for ready to write ATAPI command block */ 713 while (timeout--) { 714 int reason = ATA_IDX_INB(ch, ATA_IREASON); 715 int status = ATA_IDX_INB(ch, ATA_STATUS); 716 717 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 718 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 719 break; 720 DELAY(20); 721 } 722 if (timeout <= 0) { 723 device_printf(request->parent, 724 "timeout waiting for ATAPI ready\n"); 725 request->flags |= ATA_R_TIMEOUT; 726 return (-1); 727 } 728 729 /* this seems to be needed for some (slow) devices */ 730 DELAY(10); 731 732 /* output command block */ 733 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 734 (request->flags & ATA_R_ATAPI16) ? 8 : 6); 735 } 736 else { 737 ch->hw.tf_write(request); 738 739 /* issue command to controller */ 740 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 741 } 742 return (0); 743 } 744 745 static void 746 ata_tf_read(struct ata_request *request) 747 { 748 struct ata_channel *ch = device_get_softc(request->parent); 749 750 if (request->flags & ATA_R_48BIT) { 751 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB); 752 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8); 753 request->u.ata.lba = 754 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) | 755 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) | 756 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40); 757 758 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 759 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT); 760 request->u.ata.lba |= 761 (ATA_IDX_INB(ch, ATA_SECTOR) | 762 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 763 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16)); 764 } 765 else { 766 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 767 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 768 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 769 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 770 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24); 771 } 772 } 773 774 static void 775 ata_tf_write(struct ata_request *request) 776 { 777 struct ata_channel *ch = device_get_softc(request->parent); 778 #ifndef ATA_CAM 779 struct ata_device *atadev = device_get_softc(request->dev); 780 #endif 781 782 if (request->flags & ATA_R_48BIT) { 783 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8); 784 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 785 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8); 786 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 787 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24); 788 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 789 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32); 790 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 791 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40); 792 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 793 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 794 } 795 else { 796 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 797 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 798 #ifndef ATA_CAM 799 if (atadev->flags & ATA_D_USE_CHS) { 800 int heads, sectors; 801 802 if (atadev->param.atavalid & ATA_FLAG_54_58) { 803 heads = atadev->param.current_heads; 804 sectors = atadev->param.current_sectors; 805 } 806 else { 807 heads = atadev->param.heads; 808 sectors = atadev->param.sectors; 809 } 810 811 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 812 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 813 (request->u.ata.lba / (sectors * heads))); 814 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 815 (request->u.ata.lba / (sectors * heads)) >> 8); 816 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 817 (((request->u.ata.lba% (sectors * heads)) / 818 sectors) & 0xf)); 819 } 820 else { 821 #endif 822 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 823 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 824 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 825 ATA_IDX_OUTB(ch, ATA_DRIVE, 826 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 827 ((request->u.ata.lba >> 24) & 0x0f)); 828 #ifndef ATA_CAM 829 } 830 #endif 831 } 832 } 833 834 static void 835 ata_pio_read(struct ata_request *request, int length) 836 { 837 struct ata_channel *ch = device_get_softc(request->parent); 838 uint8_t *addr; 839 int size = min(request->transfersize, length); 840 int resid; 841 uint8_t buf[2]; 842 843 addr = (uint8_t *)request->data + request->donecount; 844 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)) || 845 ((uintptr_t)addr % sizeof(int32_t))) { 846 ATA_IDX_INSW_STRM(ch, ATA_DATA, (void*)addr, size / sizeof(int16_t)); 847 if (size & 1) { 848 ATA_IDX_INSW_STRM(ch, ATA_DATA, (void*)buf, 1); 849 (addr + (size & ~1))[0] = buf[0]; 850 } 851 } else 852 ATA_IDX_INSL_STRM(ch, ATA_DATA, (void*)addr, size / sizeof(int32_t)); 853 854 if (request->transfersize < length) { 855 device_printf(request->parent, "WARNING - %s read data overrun %d>%d\n", 856 ata_cmd2str(request), length, request->transfersize); 857 for (resid = request->transfersize + (size & 1); resid < length; 858 resid += sizeof(int16_t)) 859 ATA_IDX_INW(ch, ATA_DATA); 860 } 861 } 862 863 static void 864 ata_pio_write(struct ata_request *request, int length) 865 { 866 struct ata_channel *ch = device_get_softc(request->parent); 867 uint8_t *addr; 868 int size = min(request->transfersize, length); 869 int resid; 870 uint8_t buf[2]; 871 872 addr = (uint8_t *)request->data + request->donecount; 873 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)) || 874 ((uintptr_t)addr % sizeof(int32_t))) { 875 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (void*)addr, size / sizeof(int16_t)); 876 if (size & 1) { 877 buf[0] = (addr + (size & ~1))[0]; 878 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (void*)buf, 1); 879 } 880 } else 881 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, (void*)addr, size / sizeof(int32_t)); 882 883 if (request->transfersize < length) { 884 device_printf(request->parent, "WARNING - %s write data underrun %d>%d\n", 885 ata_cmd2str(request), length, request->transfersize); 886 for (resid = request->transfersize + (size & 1); resid < length; 887 resid += sizeof(int16_t)) 888 ATA_IDX_OUTW(ch, ATA_DATA, 0); 889 } 890 } 891