1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/endian.h> 35 #include <sys/ata.h> 36 #include <sys/conf.h> 37 #include <sys/ctype.h> 38 #include <sys/bus.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/ata/ata-all.h> 45 #include <dev/ata/ata-pci.h> 46 #include <ata_if.h> 47 48 /* prototypes */ 49 static int ata_generic_status(device_t dev); 50 static int ata_wait(struct ata_channel *ch, int unit, u_int8_t); 51 static void ata_pio_read(struct ata_request *, int); 52 static void ata_pio_write(struct ata_request *, int); 53 static void ata_tf_read(struct ata_request *); 54 static void ata_tf_write(struct ata_request *); 55 56 /* 57 * low level ATA functions 58 */ 59 void 60 ata_generic_hw(device_t dev) 61 { 62 struct ata_channel *ch = device_get_softc(dev); 63 64 ch->hw.begin_transaction = ata_begin_transaction; 65 ch->hw.end_transaction = ata_end_transaction; 66 ch->hw.status = ata_generic_status; 67 ch->hw.softreset = NULL; 68 ch->hw.command = ata_generic_command; 69 ch->hw.tf_read = ata_tf_read; 70 ch->hw.tf_write = ata_tf_write; 71 ch->hw.pm_read = NULL; 72 ch->hw.pm_write = NULL; 73 } 74 75 /* must be called with ATA channel locked and state_mtx held */ 76 int 77 ata_begin_transaction(struct ata_request *request) 78 { 79 struct ata_channel *ch = device_get_softc(request->parent); 80 int dummy, error; 81 82 ATA_DEBUG_RQ(request, "begin transaction"); 83 84 /* disable ATAPI DMA writes if HW doesn't support it */ 85 if ((ch->flags & ATA_NO_ATAPI_DMA) && 86 (request->flags & ATA_R_ATAPI) == ATA_R_ATAPI) 87 request->flags &= ~ATA_R_DMA; 88 if ((ch->flags & ATA_ATAPI_DMA_RO) && 89 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 90 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 91 request->flags &= ~ATA_R_DMA; 92 93 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 94 95 /* ATA PIO data transfer and control commands */ 96 default: 97 { 98 /* record command direction here as our request might be gone later */ 99 int write = (request->flags & ATA_R_WRITE); 100 101 /* issue command */ 102 if (ch->hw.command(request)) { 103 device_printf(request->parent, "error issuing %s command\n", 104 ata_cmd2str(request)); 105 request->result = EIO; 106 goto begin_finished; 107 } 108 109 /* device reset doesn't interrupt */ 110 if (request->u.ata.command == ATA_DEVICE_RESET) { 111 112 int timeout = 1000000; 113 do { 114 DELAY(10); 115 request->status = ATA_IDX_INB(ch, ATA_STATUS); 116 } while (request->status & ATA_S_BUSY && timeout--); 117 if (request->status & ATA_S_ERROR) 118 request->error = ATA_IDX_INB(ch, ATA_ERROR); 119 goto begin_finished; 120 } 121 122 /* if write command output the data */ 123 if (write) { 124 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) { 125 device_printf(request->parent, 126 "timeout waiting for write DRQ\n"); 127 request->result = EIO; 128 goto begin_finished; 129 } 130 ata_pio_write(request, request->transfersize); 131 } 132 } 133 goto begin_continue; 134 135 /* ATA DMA data transfer commands */ 136 case ATA_R_DMA: 137 /* check sanity, setup SG list and DMA engine */ 138 if ((error = ch->dma.load(request, NULL, &dummy))) { 139 device_printf(request->parent, "setting up DMA failed\n"); 140 request->result = error; 141 goto begin_finished; 142 } 143 144 /* start DMA engine if necessary */ 145 if ((ch->flags & ATA_DMA_BEFORE_CMD) && 146 ch->dma.start && ch->dma.start(request)) { 147 device_printf(request->parent, "error starting DMA\n"); 148 request->result = EIO; 149 goto begin_finished; 150 } 151 152 /* issue command */ 153 if (ch->hw.command(request)) { 154 device_printf(request->parent, "error issuing %s command\n", 155 ata_cmd2str(request)); 156 request->result = EIO; 157 goto begin_finished; 158 } 159 160 /* start DMA engine */ 161 if (!(ch->flags & ATA_DMA_BEFORE_CMD) && 162 ch->dma.start && ch->dma.start(request)) { 163 device_printf(request->parent, "error starting DMA\n"); 164 request->result = EIO; 165 goto begin_finished; 166 } 167 goto begin_continue; 168 169 /* ATAPI PIO commands */ 170 case ATA_R_ATAPI: 171 /* is this just a POLL DSC command ? */ 172 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 173 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit)); 174 DELAY(10); 175 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 176 request->result = EBUSY; 177 goto begin_finished; 178 } 179 180 /* start ATAPI operation */ 181 if (ch->hw.command(request)) { 182 device_printf(request->parent, "error issuing ATA PACKET command\n"); 183 request->result = EIO; 184 goto begin_finished; 185 } 186 goto begin_continue; 187 188 /* ATAPI DMA commands */ 189 case ATA_R_ATAPI|ATA_R_DMA: 190 /* is this just a POLL DSC command ? */ 191 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 192 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit)); 193 DELAY(10); 194 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 195 request->result = EBUSY; 196 goto begin_finished; 197 } 198 199 /* check sanity, setup SG list and DMA engine */ 200 if ((error = ch->dma.load(request, NULL, &dummy))) { 201 device_printf(request->parent, "setting up DMA failed\n"); 202 request->result = error; 203 goto begin_finished; 204 } 205 206 /* start ATAPI operation */ 207 if (ch->hw.command(request)) { 208 device_printf(request->parent, "error issuing ATA PACKET command\n"); 209 request->result = EIO; 210 goto begin_finished; 211 } 212 213 /* start DMA engine */ 214 if (ch->dma.start && ch->dma.start(request)) { 215 request->result = EIO; 216 goto begin_finished; 217 } 218 goto begin_continue; 219 } 220 /* NOT REACHED */ 221 printf("ata_begin_transaction OOPS!!!\n"); 222 223 begin_finished: 224 if (ch->dma.unload) { 225 ch->dma.unload(request); 226 } 227 return ATA_OP_FINISHED; 228 229 begin_continue: 230 callout_reset(&request->callout, request->timeout * hz, 231 (timeout_t*)ata_timeout, request); 232 return ATA_OP_CONTINUES; 233 } 234 235 /* must be called with ATA channel locked and state_mtx held */ 236 int 237 ata_end_transaction(struct ata_request *request) 238 { 239 struct ata_channel *ch = device_get_softc(request->parent); 240 int length; 241 242 ATA_DEBUG_RQ(request, "end transaction"); 243 244 /* clear interrupt and get status */ 245 request->status = ATA_IDX_INB(ch, ATA_STATUS); 246 247 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 248 249 /* ATA PIO data transfer and control commands */ 250 default: 251 252 /* on timeouts we have no data or anything so just return */ 253 if (request->flags & ATA_R_TIMEOUT) 254 goto end_finished; 255 256 /* on control commands read back registers to the request struct */ 257 if (request->flags & ATA_R_CONTROL) { 258 ch->hw.tf_read(request); 259 } 260 261 /* if we got an error we are done with the HW */ 262 if (request->status & ATA_S_ERROR) { 263 request->error = ATA_IDX_INB(ch, ATA_ERROR); 264 goto end_finished; 265 } 266 267 /* are we moving data ? */ 268 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 269 270 /* if read data get it */ 271 if (request->flags & ATA_R_READ) { 272 int flags = ATA_S_DRQ; 273 274 if (request->u.ata.command != ATA_ATAPI_IDENTIFY) 275 flags |= ATA_S_READY; 276 if (ata_wait(ch, request->unit, flags) < 0) { 277 device_printf(request->parent, 278 "timeout waiting for read DRQ\n"); 279 request->result = EIO; 280 goto end_finished; 281 } 282 ata_pio_read(request, request->transfersize); 283 } 284 285 /* update how far we've gotten */ 286 request->donecount += request->transfersize; 287 288 /* do we need a scoop more ? */ 289 if (request->bytecount > request->donecount) { 290 291 /* set this transfer size according to HW capabilities */ 292 request->transfersize = 293 min((request->bytecount - request->donecount), 294 request->transfersize); 295 296 /* if data write command, output the data */ 297 if (request->flags & ATA_R_WRITE) { 298 299 /* if we get an error here we are done with the HW */ 300 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) { 301 device_printf(request->parent, 302 "timeout waiting for write DRQ\n"); 303 request->status = ATA_IDX_INB(ch, ATA_STATUS); 304 goto end_finished; 305 } 306 307 /* output data and return waiting for new interrupt */ 308 ata_pio_write(request, request->transfersize); 309 goto end_continue; 310 } 311 312 /* if data read command, return & wait for interrupt */ 313 if (request->flags & ATA_R_READ) 314 goto end_continue; 315 } 316 } 317 /* done with HW */ 318 goto end_finished; 319 320 /* ATA DMA data transfer commands */ 321 case ATA_R_DMA: 322 323 /* stop DMA engine and get status */ 324 if (ch->dma.stop) 325 request->dma->status = ch->dma.stop(request); 326 327 /* did we get error or data */ 328 if (request->status & ATA_S_ERROR) 329 request->error = ATA_IDX_INB(ch, ATA_ERROR); 330 else if (request->dma->status & ATA_BMSTAT_ERROR) 331 request->status |= ATA_S_ERROR; 332 else if (!(request->flags & ATA_R_TIMEOUT)) 333 request->donecount = request->bytecount; 334 335 /* release SG list etc */ 336 ch->dma.unload(request); 337 338 /* done with HW */ 339 goto end_finished; 340 341 /* ATAPI PIO commands */ 342 case ATA_R_ATAPI: 343 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 344 345 /* on timeouts we have no data or anything so just return */ 346 if (request->flags & ATA_R_TIMEOUT) 347 goto end_finished; 348 349 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 350 (request->status & ATA_S_DRQ)) { 351 352 case ATAPI_P_CMDOUT: 353 /* this seems to be needed for some (slow) devices */ 354 DELAY(10); 355 356 if (!(request->status & ATA_S_DRQ)) { 357 device_printf(request->parent, "command interrupt without DRQ\n"); 358 request->status = ATA_S_ERROR; 359 goto end_finished; 360 } 361 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 362 (request->flags & ATA_R_ATAPI16) ? 8 : 6); 363 /* return wait for interrupt */ 364 goto end_continue; 365 366 case ATAPI_P_WRITE: 367 if (request->flags & ATA_R_READ) { 368 request->status = ATA_S_ERROR; 369 device_printf(request->parent, 370 "%s trying to write on read buffer\n", 371 ata_cmd2str(request)); 372 goto end_finished; 373 break; 374 } 375 ata_pio_write(request, length); 376 request->donecount += length; 377 378 /* set next transfer size according to HW capabilities */ 379 request->transfersize = min((request->bytecount-request->donecount), 380 request->transfersize); 381 /* return wait for interrupt */ 382 goto end_continue; 383 384 case ATAPI_P_READ: 385 if (request->flags & ATA_R_WRITE) { 386 request->status = ATA_S_ERROR; 387 device_printf(request->parent, 388 "%s trying to read on write buffer\n", 389 ata_cmd2str(request)); 390 goto end_finished; 391 } 392 ata_pio_read(request, length); 393 request->donecount += length; 394 395 /* set next transfer size according to HW capabilities */ 396 request->transfersize = min((request->bytecount-request->donecount), 397 request->transfersize); 398 /* return wait for interrupt */ 399 goto end_continue; 400 401 case ATAPI_P_DONEDRQ: 402 device_printf(request->parent, 403 "WARNING - %s DONEDRQ non conformant device\n", 404 ata_cmd2str(request)); 405 if (request->flags & ATA_R_READ) { 406 ata_pio_read(request, length); 407 request->donecount += length; 408 } 409 else if (request->flags & ATA_R_WRITE) { 410 ata_pio_write(request, length); 411 request->donecount += length; 412 } 413 else 414 request->status = ATA_S_ERROR; 415 /* FALLTHROUGH */ 416 417 case ATAPI_P_ABORT: 418 case ATAPI_P_DONE: 419 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 420 request->error = ATA_IDX_INB(ch, ATA_ERROR); 421 goto end_finished; 422 423 default: 424 device_printf(request->parent, "unknown transfer phase\n"); 425 request->status = ATA_S_ERROR; 426 } 427 428 /* done with HW */ 429 goto end_finished; 430 431 /* ATAPI DMA commands */ 432 case ATA_R_ATAPI|ATA_R_DMA: 433 434 /* stop DMA engine and get status */ 435 if (ch->dma.stop) 436 request->dma->status = ch->dma.stop(request); 437 438 /* did we get error or data */ 439 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 440 request->error = ATA_IDX_INB(ch, ATA_ERROR); 441 else if (request->dma->status & ATA_BMSTAT_ERROR) 442 request->status |= ATA_S_ERROR; 443 else if (!(request->flags & ATA_R_TIMEOUT)) 444 request->donecount = request->bytecount; 445 446 /* release SG list etc */ 447 ch->dma.unload(request); 448 449 /* done with HW */ 450 goto end_finished; 451 } 452 /* NOT REACHED */ 453 printf("ata_end_transaction OOPS!!\n"); 454 455 end_finished: 456 callout_stop(&request->callout); 457 return ATA_OP_FINISHED; 458 459 end_continue: 460 return ATA_OP_CONTINUES; 461 } 462 463 /* must be called with ATA channel locked and state_mtx held */ 464 void 465 ata_generic_reset(device_t dev) 466 { 467 struct ata_channel *ch = device_get_softc(dev); 468 469 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0; 470 u_int8_t err = 0, lsb = 0, msb = 0; 471 int mask = 0, timeout; 472 473 /* do we have any signs of ATA/ATAPI HW being present ? */ 474 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 475 DELAY(10); 476 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 477 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 478 stat0 = ATA_S_BUSY; 479 mask |= 0x01; 480 } 481 482 /* in some setups we dont want to test for a slave */ 483 if (!(ch->flags & ATA_NO_SLAVE)) { 484 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_SLAVE)); 485 DELAY(10); 486 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 487 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 488 stat1 = ATA_S_BUSY; 489 mask |= 0x02; 490 } 491 } 492 493 if (bootverbose) 494 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 495 mask, ostat0, ostat1); 496 497 /* if nothing showed up there is no need to get any further */ 498 /* XXX SOS is that too strong?, we just might loose devices here */ 499 ch->devices = 0; 500 if (!mask) 501 return; 502 503 /* reset (both) devices on this channel */ 504 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 505 DELAY(10); 506 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 507 ata_udelay(10000); 508 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 509 ata_udelay(100000); 510 ATA_IDX_INB(ch, ATA_ERROR); 511 512 /* wait for BUSY to go inactive */ 513 for (timeout = 0; timeout < 310; timeout++) { 514 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) { 515 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_MASTER)); 516 DELAY(10); 517 err = ATA_IDX_INB(ch, ATA_ERROR); 518 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 519 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 520 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 521 if (bootverbose) 522 device_printf(dev, 523 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 524 stat0, err, lsb, msb); 525 if (stat0 == err && lsb == err && msb == err && 526 timeout > (stat0 & ATA_S_BUSY ? 100 : 10)) 527 mask &= ~0x01; 528 if (!(stat0 & ATA_S_BUSY)) { 529 if ((err & 0x7f) == ATA_E_ILI) { 530 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 531 ch->devices |= ATA_ATAPI_MASTER; 532 } 533 else if (stat0 & ATA_S_READY) { 534 ch->devices |= ATA_ATA_MASTER; 535 } 536 } 537 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 538 stat0 |= ATA_S_BUSY; 539 } 540 } 541 } 542 543 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) && 544 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) { 545 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_SLAVE)); 546 DELAY(10); 547 err = ATA_IDX_INB(ch, ATA_ERROR); 548 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 549 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 550 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 551 if (bootverbose) 552 device_printf(dev, 553 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 554 stat1, err, lsb, msb); 555 if (stat1 == err && lsb == err && msb == err && 556 timeout > (stat1 & ATA_S_BUSY ? 100 : 10)) 557 mask &= ~0x02; 558 if (!(stat1 & ATA_S_BUSY)) { 559 if ((err & 0x7f) == ATA_E_ILI) { 560 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 561 ch->devices |= ATA_ATAPI_SLAVE; 562 } 563 else if (stat1 & ATA_S_READY) { 564 ch->devices |= ATA_ATA_SLAVE; 565 } 566 } 567 else if ((stat1 & 0x0f) && err == lsb && err == msb) { 568 stat1 |= ATA_S_BUSY; 569 } 570 } 571 } 572 573 if (mask == 0x00) /* nothing to wait for */ 574 break; 575 if (mask == 0x01) /* wait for master only */ 576 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10)) 577 break; 578 if (mask == 0x02) /* wait for slave only */ 579 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10)) 580 break; 581 if (mask == 0x03) { /* wait for both master & slave */ 582 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 583 break; 584 if ((stat0 == 0xff) && (timeout > 20)) 585 mask &= ~0x01; 586 if ((stat1 == 0xff) && (timeout > 20)) 587 mask &= ~0x02; 588 } 589 ata_udelay(100000); 590 } 591 592 if (bootverbose) 593 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%x\n", 594 stat0, stat1, ch->devices); 595 } 596 597 /* must be called with ATA channel locked and state_mtx held */ 598 int 599 ata_generic_status(device_t dev) 600 { 601 struct ata_channel *ch = device_get_softc(dev); 602 603 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 604 DELAY(100); 605 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 606 return 0; 607 } 608 return 1; 609 } 610 611 static int 612 ata_wait(struct ata_channel *ch, int unit, u_int8_t mask) 613 { 614 u_int8_t status; 615 int timeout = 0; 616 617 DELAY(1); 618 619 /* wait at max 1 second for device to get !BUSY */ 620 while (timeout < 1000000) { 621 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 622 623 /* if drive fails status, reselect the drive and try again */ 624 if (status == 0xff) { 625 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(unit)); 626 timeout += 1000; 627 DELAY(1000); 628 continue; 629 } 630 631 /* are we done ? */ 632 if (!(status & ATA_S_BUSY)) 633 break; 634 635 if (timeout > 1000) { 636 timeout += 1000; 637 DELAY(1000); 638 } 639 else { 640 timeout += 10; 641 DELAY(10); 642 } 643 } 644 if (timeout >= 1000000) 645 return -2; 646 if (!mask) 647 return (status & ATA_S_ERROR); 648 649 DELAY(1); 650 651 /* wait 50 msec for bits wanted */ 652 timeout = 5000; 653 while (timeout--) { 654 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 655 if ((status & mask) == mask) 656 return (status & ATA_S_ERROR); 657 DELAY(10); 658 } 659 return -3; 660 } 661 662 int 663 ata_generic_command(struct ata_request *request) 664 { 665 struct ata_channel *ch = device_get_softc(request->parent); 666 667 /* select device */ 668 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit)); 669 670 /* ready to issue command ? */ 671 if (ata_wait(ch, request->unit, 0) < 0) { 672 device_printf(request->parent, "timeout waiting to issue command\n"); 673 return -1; 674 } 675 676 /* enable interrupt */ 677 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 678 679 if (request->flags & ATA_R_ATAPI) { 680 int timeout = 5000; 681 int res; 682 683 /* issue packet command to controller */ 684 if (request->flags & ATA_R_DMA) { 685 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA); 686 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0); 687 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0); 688 } 689 else { 690 ATA_IDX_OUTB(ch, ATA_FEATURE, 0); 691 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize); 692 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8); 693 } 694 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD); 695 696 /* command interrupt device ? just return and wait for interrupt */ 697 if (request->flags & ATA_R_ATAPI_INTR) 698 return 0; 699 700 /* command processed ? */ 701 res = ata_wait(ch, request->unit, 0); 702 if (res != 0) { 703 if (res < 0) 704 device_printf(request->parent, "timeout waiting for PACKET command\n"); 705 return (-1); 706 } 707 /* wait for ready to write ATAPI command block */ 708 while (timeout--) { 709 int reason = ATA_IDX_INB(ch, ATA_IREASON); 710 int status = ATA_IDX_INB(ch, ATA_STATUS); 711 712 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 713 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 714 break; 715 DELAY(20); 716 } 717 if (timeout <= 0) { 718 device_printf(request->parent, "timeout waiting for ATAPI ready\n"); 719 request->result = EIO; 720 return -1; 721 } 722 723 /* this seems to be needed for some (slow) devices */ 724 DELAY(10); 725 726 /* output command block */ 727 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 728 (request->flags & ATA_R_ATAPI16) ? 8 : 6); 729 } 730 else { 731 ch->hw.tf_write(request); 732 733 /* issue command to controller */ 734 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 735 } 736 return 0; 737 } 738 739 static void 740 ata_tf_read(struct ata_request *request) 741 { 742 struct ata_channel *ch = device_get_softc(request->parent); 743 744 if (request->flags & ATA_R_48BIT) { 745 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB); 746 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8); 747 request->u.ata.lba = 748 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) | 749 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) | 750 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40); 751 752 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 753 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT); 754 request->u.ata.lba |= 755 (ATA_IDX_INB(ch, ATA_SECTOR) | 756 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 757 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16)); 758 } 759 else { 760 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 761 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 762 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 763 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 764 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24); 765 } 766 } 767 768 static void 769 ata_tf_write(struct ata_request *request) 770 { 771 struct ata_channel *ch = device_get_softc(request->parent); 772 #ifndef ATA_CAM 773 struct ata_device *atadev = device_get_softc(request->dev); 774 #endif 775 776 if (request->flags & ATA_R_48BIT) { 777 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8); 778 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 779 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8); 780 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 781 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24); 782 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 783 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32); 784 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 785 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40); 786 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 787 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 788 } 789 else { 790 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 791 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 792 #ifndef ATA_CAM 793 if (atadev->flags & ATA_D_USE_CHS) { 794 int heads, sectors; 795 796 if (atadev->param.atavalid & ATA_FLAG_54_58) { 797 heads = atadev->param.current_heads; 798 sectors = atadev->param.current_sectors; 799 } 800 else { 801 heads = atadev->param.heads; 802 sectors = atadev->param.sectors; 803 } 804 805 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 806 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 807 (request->u.ata.lba / (sectors * heads))); 808 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 809 (request->u.ata.lba / (sectors * heads)) >> 8); 810 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 811 (((request->u.ata.lba% (sectors * heads)) / 812 sectors) & 0xf)); 813 } 814 else { 815 #endif 816 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 817 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 818 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 819 ATA_IDX_OUTB(ch, ATA_DRIVE, 820 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 821 ((request->u.ata.lba >> 24) & 0x0f)); 822 #ifndef ATA_CAM 823 } 824 #endif 825 } 826 } 827 828 static void 829 ata_pio_read(struct ata_request *request, int length) 830 { 831 struct ata_channel *ch = device_get_softc(request->parent); 832 int size = min(request->transfersize, length); 833 int resid; 834 835 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 836 ATA_IDX_INSW_STRM(ch, ATA_DATA, 837 (void*)((uintptr_t)request->data+request->donecount), 838 size / sizeof(int16_t)); 839 else 840 ATA_IDX_INSL_STRM(ch, ATA_DATA, 841 (void*)((uintptr_t)request->data+request->donecount), 842 size / sizeof(int32_t)); 843 844 if (request->transfersize < length) { 845 device_printf(request->parent, "WARNING - %s read data overrun %d>%d\n", 846 ata_cmd2str(request), length, request->transfersize); 847 for (resid = request->transfersize; resid < length; 848 resid += sizeof(int16_t)) 849 ATA_IDX_INW(ch, ATA_DATA); 850 } 851 } 852 853 static void 854 ata_pio_write(struct ata_request *request, int length) 855 { 856 struct ata_channel *ch = device_get_softc(request->parent); 857 int size = min(request->transfersize, length); 858 int resid; 859 860 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 861 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 862 (void*)((uintptr_t)request->data+request->donecount), 863 size / sizeof(int16_t)); 864 else 865 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 866 (void*)((uintptr_t)request->data+request->donecount), 867 size / sizeof(int32_t)); 868 869 if (request->transfersize < length) { 870 device_printf(request->parent, "WARNING - %s write data underrun %d>%d\n", 871 ata_cmd2str(request), length, request->transfersize); 872 for (resid = request->transfersize; resid < length; 873 resid += sizeof(int16_t)) 874 ATA_IDX_OUTW(ch, ATA_DATA, 0); 875 } 876 } 877