1 /*- 2 * Copyright (c) 1998 - 2005 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_ata.h" 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/endian.h> 37 #include <sys/ata.h> 38 #include <sys/conf.h> 39 #include <sys/ctype.h> 40 #include <sys/bus.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/bus.h> 45 #include <sys/rman.h> 46 #include <dev/ata/ata-all.h> 47 #include <dev/ata/ata-commands.h> 48 #include <dev/ata/ata-pci.h> 49 #include <ata_if.h> 50 51 /* prototypes */ 52 static int ata_begin_transaction(struct ata_request *); 53 static int ata_end_transaction(struct ata_request *); 54 static int ata_wait(struct ata_channel *ch, struct ata_device *, u_int8_t); 55 static void ata_pio_read(struct ata_request *, int); 56 static void ata_pio_write(struct ata_request *, int); 57 58 /* 59 * low level ATA functions 60 */ 61 void 62 ata_generic_hw(device_t dev) 63 { 64 struct ata_channel *ch = device_get_softc(dev); 65 66 ch->hw.begin_transaction = ata_begin_transaction; 67 ch->hw.end_transaction = ata_end_transaction; 68 ch->hw.command = ata_generic_command; 69 } 70 71 /* must be called with ATA channel locked and state_mtx held */ 72 static int 73 ata_begin_transaction(struct ata_request *request) 74 { 75 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 76 struct ata_device *atadev = device_get_softc(request->dev); 77 int dummy; 78 79 ATA_DEBUG_RQ(request, "begin transaction"); 80 81 /* disable ATAPI DMA writes if HW doesn't support it */ 82 if ((ch->flags & ATA_ATAPI_DMA_RO) && 83 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 84 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 85 request->flags &= ~ATA_R_DMA; 86 87 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 88 89 /* ATA PIO data transfer and control commands */ 90 default: 91 { 92 /* record command direction here as our request might be gone later */ 93 int write = (request->flags & ATA_R_WRITE); 94 95 /* issue command */ 96 if (ch->hw.command(request)) { 97 device_printf(request->dev, "error issueing %s command\n", 98 ata_cmd2str(request)); 99 request->result = EIO; 100 goto begin_finished; 101 } 102 103 /* device reset doesn't interrupt */ 104 if (request->u.ata.command == ATA_DEVICE_RESET) { 105 int timeout = 1000000; 106 do { 107 DELAY(10); 108 request->status = ATA_IDX_INB(ch, ATA_STATUS); 109 } while (request->status & ATA_S_BUSY && timeout--); 110 if (request->status & ATA_S_ERROR) 111 request->error = ATA_IDX_INB(ch, ATA_ERROR); 112 goto begin_finished; 113 } 114 115 /* if write command output the data */ 116 if (write) { 117 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) { 118 device_printf(request->dev,"timeout waiting for write DRQ"); 119 request->result = EIO; 120 goto begin_finished; 121 } 122 ata_pio_write(request, request->transfersize); 123 } 124 } 125 goto begin_continue; 126 127 /* ATA DMA data transfer commands */ 128 case ATA_R_DMA: 129 /* check sanity, setup SG list and DMA engine */ 130 if (ch->dma->load(ch->dev, request->data, request->bytecount, 131 request->flags & ATA_R_READ, ch->dma->sg, &dummy)) { 132 device_printf(request->dev, "setting up DMA failed\n"); 133 request->result = EIO; 134 goto begin_finished; 135 } 136 137 /* issue command */ 138 if (ch->hw.command(request)) { 139 device_printf(request->dev, "error issueing %s command\n", 140 ata_cmd2str(request)); 141 request->result = EIO; 142 goto begin_finished; 143 } 144 145 /* start DMA engine */ 146 if (ch->dma->start && ch->dma->start(request->dev)) { 147 device_printf(request->dev, "error starting DMA\n"); 148 request->result = EIO; 149 goto begin_finished; 150 } 151 goto begin_continue; 152 153 /* ATAPI PIO commands */ 154 case ATA_R_ATAPI: 155 /* is this just a POLL DSC command ? */ 156 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 157 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 158 DELAY(10); 159 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 160 request->result = EBUSY; 161 goto begin_finished; 162 } 163 164 /* start ATAPI operation */ 165 if (ch->hw.command(request)) { 166 device_printf(request->dev, "error issuing ATA PACKET command\n"); 167 request->result = EIO; 168 goto begin_finished; 169 } 170 goto begin_continue; 171 172 /* ATAPI DMA commands */ 173 case ATA_R_ATAPI|ATA_R_DMA: 174 /* is this just a POLL DSC command ? */ 175 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 176 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 177 DELAY(10); 178 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 179 request->result = EBUSY; 180 goto begin_finished; 181 } 182 183 /* check sanity, setup SG list and DMA engine */ 184 if (ch->dma->load(ch->dev, request->data, request->bytecount, 185 request->flags & ATA_R_READ, ch->dma->sg, &dummy)) { 186 device_printf(request->dev, "setting up DMA failed\n"); 187 request->result = EIO; 188 goto begin_finished; 189 } 190 191 /* start ATAPI operation */ 192 if (ch->hw.command(request)) { 193 device_printf(request->dev, "error issuing ATA PACKET command\n"); 194 request->result = EIO; 195 goto begin_finished; 196 } 197 198 /* start DMA engine */ 199 if (ch->dma->start && ch->dma->start(request->dev)) { 200 request->result = EIO; 201 goto begin_finished; 202 } 203 goto begin_continue; 204 } 205 /* NOT REACHED */ 206 printf("ata_begin_transaction OOPS!!!\n"); 207 208 begin_finished: 209 if (ch->dma && ch->dma->flags & ATA_DMA_LOADED) 210 ch->dma->unload(ch->dev); 211 return ATA_OP_FINISHED; 212 213 begin_continue: 214 callout_reset(&request->callout, request->timeout * hz, 215 (timeout_t*)ata_timeout, request); 216 return ATA_OP_CONTINUES; 217 } 218 219 /* must be called with ATA channel locked and state_mtx held */ 220 static int 221 ata_end_transaction(struct ata_request *request) 222 { 223 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 224 struct ata_device *atadev = device_get_softc(request->dev); 225 int length; 226 227 ATA_DEBUG_RQ(request, "end transaction"); 228 229 /* clear interrupt and get status */ 230 request->status = ATA_IDX_INB(ch, ATA_STATUS); 231 232 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 233 234 /* ATA PIO data transfer and control commands */ 235 default: 236 237 /* on timeouts we have no data or anything so just return */ 238 if (request->flags & ATA_R_TIMEOUT) 239 goto end_finished; 240 241 /* on control commands read back registers to the request struct */ 242 if (request->flags & ATA_R_CONTROL) { 243 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 244 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB); 245 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8); 246 request->u.ata.lba = 247 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) | 248 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) | 249 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40); 250 251 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 252 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT); 253 request->u.ata.lba |= 254 (ATA_IDX_INB(ch, ATA_SECTOR) | 255 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 256 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16)); 257 } 258 else { 259 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 260 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 261 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 262 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 263 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24); 264 } 265 } 266 267 /* if we got an error we are done with the HW */ 268 if (request->status & ATA_S_ERROR) { 269 request->error = ATA_IDX_INB(ch, ATA_ERROR); 270 goto end_finished; 271 } 272 273 /* are we moving data ? */ 274 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 275 276 /* if read data get it */ 277 if (request->flags & ATA_R_READ) { 278 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) { 279 device_printf(request->dev, "timeout waiting for read DRQ"); 280 request->result = EIO; 281 goto end_finished; 282 } 283 ata_pio_read(request, request->transfersize); 284 } 285 286 /* update how far we've gotten */ 287 request->donecount += request->transfersize; 288 289 /* do we need a scoop more ? */ 290 if (request->bytecount > request->donecount) { 291 292 /* set this transfer size according to HW capabilities */ 293 request->transfersize = 294 min((request->bytecount - request->donecount), 295 request->transfersize); 296 297 /* if data write command, output the data */ 298 if (request->flags & ATA_R_WRITE) { 299 300 /* if we get an error here we are done with the HW */ 301 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) { 302 device_printf(request->dev, 303 "timeout waiting for write DRQ"); 304 request->status = ATA_IDX_INB(ch, ATA_STATUS); 305 goto end_finished; 306 } 307 308 /* output data and return waiting for new interrupt */ 309 ata_pio_write(request, request->transfersize); 310 goto end_continue; 311 } 312 313 /* if data read command, return & wait for interrupt */ 314 if (request->flags & ATA_R_READ) 315 goto end_continue; 316 } 317 } 318 /* done with HW */ 319 goto end_finished; 320 321 /* ATA DMA data transfer commands */ 322 case ATA_R_DMA: 323 324 /* stop DMA engine and get status */ 325 if (ch->dma->stop) 326 request->dmastat = ch->dma->stop(request->dev); 327 328 /* did we get error or data */ 329 if (request->status & ATA_S_ERROR) 330 request->error = ATA_IDX_INB(ch, ATA_ERROR); 331 else if (request->dmastat & ATA_BMSTAT_ERROR) 332 request->status |= ATA_S_ERROR; 333 else if (!(request->flags & ATA_R_TIMEOUT)) 334 request->donecount = request->bytecount; 335 336 /* release SG list etc */ 337 ch->dma->unload(ch->dev); 338 339 /* done with HW */ 340 goto end_finished; 341 342 /* ATAPI PIO commands */ 343 case ATA_R_ATAPI: 344 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 345 346 /* on timeouts we have no data or anything so just return */ 347 if (request->flags & ATA_R_TIMEOUT) 348 goto end_finished; 349 350 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 351 (request->status & ATA_S_DRQ)) { 352 353 case ATAPI_P_CMDOUT: 354 /* this seems to be needed for some (slow) devices */ 355 DELAY(10); 356 357 if (!(request->status & ATA_S_DRQ)) { 358 device_printf(request->dev, "command interrupt without DRQ\n"); 359 request->status = ATA_S_ERROR; 360 goto end_finished; 361 } 362 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 363 (atadev->param.config & 364 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); 365 /* return wait for interrupt */ 366 goto end_continue; 367 368 case ATAPI_P_WRITE: 369 if (request->flags & ATA_R_READ) { 370 request->status = ATA_S_ERROR; 371 device_printf(request->dev, 372 "%s trying to write on read buffer\n", 373 ata_cmd2str(request)); 374 goto end_finished; 375 break; 376 } 377 ata_pio_write(request, length); 378 request->donecount += length; 379 380 /* set next transfer size according to HW capabilities */ 381 request->transfersize = min((request->bytecount-request->donecount), 382 request->transfersize); 383 /* return wait for interrupt */ 384 goto end_continue; 385 386 case ATAPI_P_READ: 387 if (request->flags & ATA_R_WRITE) { 388 request->status = ATA_S_ERROR; 389 device_printf(request->dev, 390 "%s trying to read on write buffer\n", 391 ata_cmd2str(request)); 392 goto end_finished; 393 } 394 ata_pio_read(request, length); 395 request->donecount += length; 396 397 /* set next transfer size according to HW capabilities */ 398 request->transfersize = min((request->bytecount-request->donecount), 399 request->transfersize); 400 /* return wait for interrupt */ 401 goto end_continue; 402 403 case ATAPI_P_DONEDRQ: 404 device_printf(request->dev, 405 "WARNING - %s DONEDRQ non conformant device\n", 406 ata_cmd2str(request)); 407 if (request->flags & ATA_R_READ) { 408 ata_pio_read(request, length); 409 request->donecount += length; 410 } 411 else if (request->flags & ATA_R_WRITE) { 412 ata_pio_write(request, length); 413 request->donecount += length; 414 } 415 else 416 request->status = ATA_S_ERROR; 417 /* FALLTHROUGH */ 418 419 case ATAPI_P_ABORT: 420 case ATAPI_P_DONE: 421 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 422 request->error = ATA_IDX_INB(ch, ATA_ERROR); 423 goto end_finished; 424 425 default: 426 device_printf(request->dev, "unknown transfer phase\n"); 427 request->status = ATA_S_ERROR; 428 } 429 430 /* done with HW */ 431 goto end_finished; 432 433 /* ATAPI DMA commands */ 434 case ATA_R_ATAPI|ATA_R_DMA: 435 436 /* stop DMA engine and get status */ 437 if (ch->dma->stop) 438 request->dmastat = ch->dma->stop(request->dev); 439 440 /* did we get error or data */ 441 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 442 request->error = ATA_IDX_INB(ch, ATA_ERROR); 443 else if (request->dmastat & ATA_BMSTAT_ERROR) 444 request->status |= ATA_S_ERROR; 445 else if (!(request->flags & ATA_R_TIMEOUT)) 446 request->donecount = request->bytecount; 447 448 /* release SG list etc */ 449 ch->dma->unload(ch->dev); 450 451 /* done with HW */ 452 goto end_finished; 453 } 454 /* NOT REACHED */ 455 printf("ata_end_transaction OOPS!!\n"); 456 457 end_finished: 458 callout_stop(&request->callout); 459 return ATA_OP_FINISHED; 460 461 end_continue: 462 return ATA_OP_CONTINUES; 463 } 464 465 /* must be called with ATA channel locked */ 466 void 467 ata_generic_reset(device_t dev) 468 { 469 struct ata_channel *ch = device_get_softc(dev); 470 471 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0; 472 u_int8_t err = 0, lsb = 0, msb = 0; 473 int mask = 0, timeout; 474 475 /* do we have any signs of ATA/ATAPI HW being present ? */ 476 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER); 477 DELAY(10); 478 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 479 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 480 stat0 = ATA_S_BUSY; 481 mask |= 0x01; 482 } 483 484 /* in some setups we dont want to test for a slave */ 485 if (!(ch->flags & ATA_NO_SLAVE)) { 486 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_SLAVE); 487 DELAY(10); 488 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 489 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 490 stat1 = ATA_S_BUSY; 491 mask |= 0x02; 492 } 493 } 494 495 if (bootverbose) 496 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 497 mask, ostat0, ostat1); 498 499 /* if nothing showed up there is no need to get any further */ 500 /* XXX SOS is that too strong?, we just might loose devices here */ 501 ch->devices = 0; 502 if (!mask) 503 return; 504 505 /* reset (both) devices on this channel */ 506 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER); 507 DELAY(10); 508 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 509 ata_udelay(10000); 510 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 511 ata_udelay(100000); 512 ATA_IDX_INB(ch, ATA_ERROR); 513 514 /* wait for BUSY to go inactive */ 515 for (timeout = 0; timeout < 310; timeout++) { 516 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) { 517 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 518 DELAY(10); 519 err = ATA_IDX_INB(ch, ATA_ERROR); 520 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 521 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 522 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 523 if (bootverbose) 524 device_printf(dev, 525 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 526 stat0, err, lsb, msb); 527 if (stat0 == err && lsb == err && msb == err && 528 timeout > (stat0 & ATA_S_BUSY ? 100 : 10)) 529 mask &= ~0x01; 530 if (!(stat0 & ATA_S_BUSY)) { 531 if ((err & 0x7f) == ATA_E_ILI) { 532 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 533 ch->devices |= ATA_ATAPI_MASTER; 534 } 535 else if (stat0 & ATA_S_READY) { 536 ch->devices |= ATA_ATA_MASTER; 537 } 538 } 539 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 540 stat0 |= ATA_S_BUSY; 541 } 542 } 543 } 544 545 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) && 546 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) { 547 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 548 DELAY(10); 549 err = ATA_IDX_INB(ch, ATA_ERROR); 550 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 551 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 552 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 553 if (bootverbose) 554 device_printf(dev, 555 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 556 stat1, err, lsb, msb); 557 if (stat1 == err && lsb == err && msb == err && 558 timeout > (stat1 & ATA_S_BUSY ? 100 : 10)) 559 mask &= ~0x02; 560 if (!(stat1 & ATA_S_BUSY)) { 561 if ((err & 0x7f) == ATA_E_ILI) { 562 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 563 ch->devices |= ATA_ATAPI_SLAVE; 564 } 565 else if (stat1 & ATA_S_READY) { 566 ch->devices |= ATA_ATA_SLAVE; 567 } 568 } 569 else if ((stat1 & 0x0f) && err == lsb && err == msb) { 570 stat1 |= ATA_S_BUSY; 571 } 572 } 573 } 574 575 if (mask == 0x00) /* nothing to wait for */ 576 break; 577 if (mask == 0x01) /* wait for master only */ 578 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10)) 579 break; 580 if (mask == 0x02) /* wait for slave only */ 581 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10)) 582 break; 583 if (mask == 0x03) { /* wait for both master & slave */ 584 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 585 break; 586 if ((stat0 == 0xff) && (timeout > 20)) 587 mask &= ~0x01; 588 if ((stat1 == 0xff) && (timeout > 20)) 589 mask &= ~0x02; 590 } 591 ata_udelay(100000); 592 } 593 594 if (bootverbose) 595 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n", 596 stat0, stat1, ch->devices, 597 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 598 } 599 600 static int 601 ata_wait(struct ata_channel *ch, struct ata_device *atadev, u_int8_t mask) 602 { 603 u_int8_t status; 604 int timeout = 0; 605 606 DELAY(1); 607 608 /* wait at max 1 second for device to get !BUSY */ 609 while (timeout < 1000000) { 610 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 611 612 /* if drive fails status, reselect the drive and try again */ 613 if (status == 0xff) { 614 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 615 timeout += 1000; 616 DELAY(1000); 617 continue; 618 } 619 620 /* are we done ? */ 621 if (!(status & ATA_S_BUSY)) 622 break; 623 624 if (timeout > 1000) { 625 timeout += 1000; 626 DELAY(1000); 627 } 628 else { 629 timeout += 10; 630 DELAY(10); 631 } 632 } 633 if (timeout >= 1000000) 634 return -2; 635 if (!mask) 636 return (status & ATA_S_ERROR); 637 638 DELAY(1); 639 640 /* wait 50 msec for bits wanted */ 641 timeout = 5000; 642 while (timeout--) { 643 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 644 if ((status & mask) == mask) 645 return (status & ATA_S_ERROR); 646 DELAY(10); 647 } 648 return -3; 649 } 650 651 int 652 ata_generic_command(struct ata_request *request) 653 { 654 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 655 struct ata_device *atadev = device_get_softc(request->dev); 656 657 /* select device */ 658 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 659 660 /* ready to issue command ? */ 661 if (ata_wait(ch, atadev, 0) < 0) { 662 device_printf(request->dev, "timeout waiting to issue command\n"); 663 return -1; 664 } 665 666 /* enable interrupt */ 667 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 668 669 if (request->flags & ATA_R_ATAPI) { 670 int timeout = 5000; 671 672 /* issue packet command to controller */ 673 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize); 674 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8); 675 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD); 676 677 /* command interrupt device ? just return and wait for interrupt */ 678 if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR) 679 return 0; 680 681 /* wait for ready to write ATAPI command block */ 682 while (timeout--) { 683 int reason = ATA_IDX_INB(ch, ATA_IREASON); 684 int status = ATA_IDX_INB(ch, ATA_STATUS); 685 686 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 687 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 688 break; 689 DELAY(20); 690 } 691 if (timeout <= 0) { 692 device_printf(request->dev,"timeout waiting for ATAPI ready\n"); 693 request->result = EIO; 694 return -1; 695 } 696 697 /* this seems to be needed for some (slow) devices */ 698 DELAY(10); 699 700 /* output command block */ 701 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 702 (atadev->param.config & ATA_PROTO_MASK) == 703 ATA_PROTO_ATAPI_12 ? 6 : 8); 704 } 705 else { 706 u_int8_t command = ata_modify_if_48bit(request); 707 708 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 709 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8); 710 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 711 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8); 712 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 713 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24); 714 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 715 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32); 716 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 717 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40); 718 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 719 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit); 720 } 721 else { 722 command = request->u.ata.command; 723 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 724 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 725 if (atadev->flags & ATA_D_USE_CHS) { 726 int heads, sectors; 727 728 if (atadev->param.atavalid & ATA_FLAG_54_58) { 729 heads = atadev->param.current_heads; 730 sectors = atadev->param.current_sectors; 731 } 732 else { 733 heads = atadev->param.heads; 734 sectors = atadev->param.sectors; 735 } 736 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 737 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 738 (request->u.ata.lba / (sectors * heads))); 739 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 740 (request->u.ata.lba / (sectors * heads)) >> 8); 741 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit | 742 (((request->u.ata.lba% (sectors * heads)) / 743 sectors) & 0xf)); 744 } 745 else { 746 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 747 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 748 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 749 ATA_IDX_OUTB(ch, ATA_DRIVE, 750 ATA_D_IBM | ATA_D_LBA | atadev->unit | 751 ((request->u.ata.lba >> 24) & 0x0f)); 752 } 753 } 754 755 /* issue command to controller */ 756 ATA_IDX_OUTB(ch, ATA_COMMAND, command); 757 } 758 759 return 0; 760 } 761 762 static void 763 ata_pio_read(struct ata_request *request, int length) 764 { 765 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 766 int size = min(request->transfersize, length); 767 int resid; 768 769 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 770 ATA_IDX_INSW_STRM(ch, ATA_DATA, 771 (void*)((uintptr_t)request->data+request->donecount), 772 size / sizeof(int16_t)); 773 else 774 ATA_IDX_INSL_STRM(ch, ATA_DATA, 775 (void*)((uintptr_t)request->data+request->donecount), 776 size / sizeof(int32_t)); 777 778 if (request->transfersize < length) { 779 device_printf(request->dev, "WARNING - %s read data overrun %d>%d\n", 780 ata_cmd2str(request), length, request->transfersize); 781 for (resid = request->transfersize; resid < length; 782 resid += sizeof(int16_t)) 783 ATA_IDX_INW(ch, ATA_DATA); 784 } 785 } 786 787 static void 788 ata_pio_write(struct ata_request *request, int length) 789 { 790 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 791 int size = min(request->transfersize, length); 792 int resid; 793 794 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 795 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 796 (void*)((uintptr_t)request->data+request->donecount), 797 size / sizeof(int16_t)); 798 else 799 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 800 (void*)((uintptr_t)request->data+request->donecount), 801 size / sizeof(int32_t)); 802 803 if (request->transfersize < length) { 804 device_printf(request->dev, "WARNING - %s write data underrun %d>%d\n", 805 ata_cmd2str(request), length, request->transfersize); 806 for (resid = request->transfersize; resid < length; 807 resid += sizeof(int16_t)) 808 ATA_IDX_OUTW(ch, ATA_DATA, 0); 809 } 810 } 811