1 /*- 2 * Copyright (c) 1998 - 2004 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_ata.h" 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/ata.h> 36 #include <sys/kernel.h> 37 #include <sys/conf.h> 38 #include <sys/bus.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/ata/ata-all.h> 45 46 /* prototypes */ 47 static int ata_generic_transaction(struct ata_request *); 48 static void ata_generic_interrupt(void *); 49 static void ata_generic_reset(struct ata_channel *); 50 static int ata_wait(struct ata_device *, u_int8_t); 51 static void ata_pio_read(struct ata_request *, int); 52 static void ata_pio_write(struct ata_request *, int); 53 54 /* local vars */ 55 static int atadebug = 0; 56 57 /* 58 * low level ATA functions 59 */ 60 void 61 ata_generic_hw(struct ata_channel *ch) 62 { 63 ch->hw.reset = ata_generic_reset; 64 ch->hw.transaction = ata_generic_transaction; 65 ch->hw.interrupt = ata_generic_interrupt; 66 ch->hw.command = ata_generic_command; 67 } 68 69 /* must be called with ATA channel locked */ 70 static int 71 ata_generic_transaction(struct ata_request *request) 72 { 73 struct ata_channel *ch = request->device->channel; 74 75 /* safetybelt for HW that went away */ 76 if (!request->device->param || request->device->channel->flags&ATA_HWGONE) { 77 request->retries = 0; 78 request->result = ENXIO; 79 return ATA_OP_FINISHED; 80 } 81 82 ATA_DEBUG_RQ(request, "transaction"); 83 84 /* disable ATAPI DMA writes if HW doesn't support it */ 85 if ((ch->flags & ATA_ATAPI_DMA_RO) && 86 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 87 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 88 request->flags &= ~ATA_R_DMA; 89 90 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 91 92 /* ATA PIO data transfer and control commands */ 93 default: 94 { 95 /* record command direction here as our request might be gone later */ 96 int write = (request->flags & ATA_R_WRITE); 97 98 /* issue command */ 99 if (ch->hw.command(request->device, request->u.ata.command, 100 request->u.ata.lba, request->u.ata.count, 101 request->u.ata.feature)) { 102 ata_prtdev(request->device, "error issueing %s command\n", 103 ata_cmd2str(request)); 104 request->result = EIO; 105 break; 106 } 107 108 /* device reset doesn't interrupt */ 109 if (request->u.ata.command == ATA_ATAPI_RESET) { 110 int timeout = 1000000; 111 do { 112 DELAY(10); 113 request->status = ATA_IDX_INB(ch, ATA_STATUS); 114 } while (request->status & ATA_S_BUSY && timeout--); 115 if (timeout) 116 printf("ATAPI_RESET time = %dus\n", (1000000-timeout)*10); 117 else 118 printf("ATAPI_RESET timeout\n"); 119 120 if (request->status & ATA_S_ERROR) 121 request->error = ATA_IDX_INB(ch, ATA_ERROR); 122 break; 123 } 124 125 /* if write command output the data */ 126 if (write) { 127 if (ata_wait(request->device, 128 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 129 ata_prtdev(request->device,"timeout waiting for write DRQ"); 130 request->result = EIO; 131 break; 132 } 133 ata_pio_write(request, request->transfersize); 134 } 135 } 136 137 /* record the request as running and return for interrupt */ 138 ch->running = request; 139 return ATA_OP_CONTINUES; 140 141 /* ATA DMA data transfer commands */ 142 case ATA_R_DMA: 143 /* check sanity, setup SG list and DMA engine */ 144 if (ch->dma->load(request->device, request->data, request->bytecount, 145 request->flags & ATA_R_READ)) { 146 ata_prtdev(request->device, "setting up DMA failed\n"); 147 request->result = EIO; 148 break; 149 } 150 151 /* issue command */ 152 if (ch->hw.command(request->device, request->u.ata.command, 153 request->u.ata.lba, request->u.ata.count, 154 request->u.ata.feature)) { 155 ata_prtdev(request->device, "error issueing %s command\n", 156 ata_cmd2str(request)); 157 request->result = EIO; 158 break; 159 } 160 161 /* start DMA engine */ 162 if (ch->dma->start(ch)) { 163 ata_prtdev(request->device, "error starting DMA\n"); 164 request->result = EIO; 165 break; 166 } 167 168 /* record the request as running and return for interrupt */ 169 ch->running = request; 170 return ATA_OP_CONTINUES; 171 172 /* ATAPI PIO commands */ 173 case ATA_R_ATAPI: 174 /* is this just a POLL DSC command ? */ 175 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 176 ATA_IDX_OUTB(ch, ATA_DRIVE, 177 ATA_D_IBM | request->device->unit); 178 DELAY(10); 179 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC)) 180 request->result = EBUSY; 181 break; 182 } 183 184 /* start ATAPI operation */ 185 if (ch->hw.command(request->device, ATA_PACKET_CMD, 186 request->transfersize << 8, 0, 0)) { 187 ata_prtdev(request->device, "error issuing ATA PACKET command\n"); 188 request->result = EIO; 189 break; 190 } 191 192 /* command interrupt device ? just return and wait for interrupt */ 193 if ((request->device->param->config & ATA_DRQ_MASK) == ATA_DRQ_INTR) { 194 ch->running = request; 195 return ATA_OP_CONTINUES; 196 } 197 198 /* wait for ready to write ATAPI command block */ 199 { 200 int timeout = 5000; /* might be less for fast devices */ 201 while (timeout--) { 202 int reason = ATA_IDX_INB(ch, ATA_IREASON); 203 int status = ATA_IDX_INB(ch, ATA_STATUS); 204 205 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 206 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 207 break; 208 DELAY(20); 209 } 210 if (timeout <= 0) { 211 ata_prtdev(request->device, 212 "timeout waiting for ATAPI ready\n"); 213 request->result = EIO; 214 break; 215 } 216 } 217 218 /* this seems to be needed for some (slow) devices */ 219 DELAY(10); 220 221 /* output actual command block */ 222 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 223 (int16_t *)request->u.atapi.ccb, 224 (request->device->param->config & ATA_PROTO_MASK) == 225 ATA_PROTO_ATAPI_12 ? 6 : 8); 226 227 /* record the request as running and return for interrupt */ 228 ch->running = request; 229 return ATA_OP_CONTINUES; 230 231 case ATA_R_ATAPI|ATA_R_DMA: 232 /* is this just a POLL DSC command ? */ 233 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 234 ATA_IDX_OUTB(ch, ATA_DRIVE, 235 ATA_D_IBM | request->device->unit); 236 DELAY(10); 237 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC)) 238 request->result = EBUSY; 239 break; 240 } 241 242 /* check sanity, setup SG list and DMA engine */ 243 if (ch->dma->load(request->device, 244 request->data, 245 request->bytecount, 246 request->flags & ATA_R_READ)) { 247 ata_prtdev(request->device, "setting up DMA failed\n"); 248 request->result = EIO; 249 break; 250 } 251 252 /* start ATAPI operation */ 253 if (ch->hw.command(request->device, ATA_PACKET_CMD, 0, 0, ATA_F_DMA)) { 254 ata_prtdev(request->device, "error issuing ATAPI packet command\n"); 255 request->result = EIO; 256 break; 257 } 258 259 /* wait for ready to write ATAPI command block */ 260 { 261 int timeout = 5000; /* might be less for fast devices */ 262 while (timeout--) { 263 int reason = ATA_IDX_INB(ch, ATA_IREASON); 264 int status = ATA_IDX_INB(ch, ATA_STATUS); 265 266 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 267 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 268 break; 269 DELAY(20); 270 } 271 if (timeout <= 0) { 272 ata_prtdev(request->device,"timeout waiting for ATAPI ready\n"); 273 request->result = EIO; 274 break; 275 } 276 } 277 278 /* this seems to be needed for some (slow) devices */ 279 DELAY(10); 280 281 /* output actual command block */ 282 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 283 (int16_t *)request->u.atapi.ccb, 284 (request->device->param->config & ATA_PROTO_MASK) == 285 ATA_PROTO_ATAPI_12 ? 6 : 8); 286 287 /* start DMA engine */ 288 if (ch->dma->start(ch)) { 289 request->result = EIO; 290 break; 291 } 292 293 /* record the request as running and return for interrupt */ 294 ch->running = request; 295 return ATA_OP_CONTINUES; 296 } 297 298 /* request finish here */ 299 if (ch->dma && ch->dma->flags & ATA_DMA_LOADED) 300 ch->dma->unload(ch); 301 return ATA_OP_FINISHED; 302 } 303 304 static void 305 ata_generic_interrupt(void *data) 306 { 307 struct ata_channel *ch = (struct ata_channel *)data; 308 struct ata_request *request = ch->running; 309 int length; 310 311 /* ignore this interrupt if there is no running request */ 312 if (!request) 313 return; 314 315 ATA_DEBUG_RQ(request, "interrupt"); 316 317 /* ignore interrupt if device is busy */ 318 if (!(request->flags & ATA_R_TIMEOUT) && 319 ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 320 DELAY(100); 321 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DRQ)) 322 return; 323 } 324 325 ATA_DEBUG_RQ(request, "interrupt accepted"); 326 327 /* clear interrupt and get status */ 328 request->status = ATA_IDX_INB(ch, ATA_STATUS); 329 330 /* register interrupt */ 331 if (!(request->flags & ATA_R_TIMEOUT)) 332 request->flags |= ATA_R_INTR_SEEN; 333 334 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 335 336 /* ATA PIO data transfer and control commands */ 337 default: 338 339 /* on control commands read back registers to the request struct */ 340 if (request->flags & ATA_R_CONTROL) { 341 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 342 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 343 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 344 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16); 345 } 346 347 /* if we got an error we are done with the HW */ 348 if (request->status & ATA_S_ERROR) { 349 request->error = ATA_IDX_INB(ch, ATA_ERROR); 350 break; 351 } 352 353 /* are we moving data ? */ 354 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 355 356 /* if read data get it */ 357 if (request->flags & ATA_R_READ) 358 ata_pio_read(request, request->transfersize); 359 360 /* update how far we've gotten */ 361 request->donecount += request->transfersize; 362 363 /* do we need a scoop more ? */ 364 if (request->bytecount > request->donecount) { 365 366 /* set this transfer size according to HW capabilities */ 367 request->transfersize = 368 min((request->bytecount - request->donecount), 369 request->transfersize); 370 371 /* clear interrupt seen flag as we need to wait again */ 372 request->flags &= ~ATA_R_INTR_SEEN; 373 374 /* if data write command, output the data */ 375 if (request->flags & ATA_R_WRITE) { 376 377 /* if we get an error here we are done with the HW */ 378 if (ata_wait(request->device, 379 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 380 ata_prtdev(request->device, 381 "timeout waiting for write DRQ"); 382 request->status = ATA_IDX_INB(ch, ATA_STATUS); 383 break; 384 } 385 386 /* output data and return waiting for new interrupt */ 387 ata_pio_write(request, request->transfersize); 388 return; 389 } 390 391 /* if data read command, return & wait for interrupt */ 392 if (request->flags & ATA_R_READ) 393 return; 394 } 395 } 396 /* done with HW */ 397 break; 398 399 /* ATA DMA data transfer commands */ 400 case ATA_R_DMA: 401 402 /* stop DMA engine and get status */ 403 if (ch->dma->stop) 404 request->dmastat = ch->dma->stop(ch); 405 406 /* did we get error or data */ 407 if (request->status & ATA_S_ERROR) 408 request->error = ATA_IDX_INB(ch, ATA_ERROR); 409 else if (request->dmastat & ATA_BMSTAT_ERROR) 410 request->status |= ATA_S_ERROR; 411 else 412 request->donecount = request->bytecount; 413 414 /* release SG list etc */ 415 ch->dma->unload(ch); 416 417 /* done with HW */ 418 break; 419 420 /* ATAPI PIO commands */ 421 case ATA_R_ATAPI: 422 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 423 424 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 425 (request->status & ATA_S_DRQ)) { 426 427 case ATAPI_P_CMDOUT: 428 /* this seems to be needed for some (slow) devices */ 429 DELAY(10); 430 431 if (!(request->status & ATA_S_DRQ)) { 432 ata_prtdev(request->device, "command interrupt without DRQ\n"); 433 request->status = ATA_S_ERROR; 434 break; 435 } 436 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 437 (request->device->param->config & 438 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); 439 /* return wait for interrupt */ 440 return; 441 442 case ATAPI_P_WRITE: 443 if (request->flags & ATA_R_READ) { 444 request->status = ATA_S_ERROR; 445 ata_prtdev(request->device, 446 "%s trying to write on read buffer\n", 447 ata_cmd2str(request)); 448 break; 449 } 450 ata_pio_write(request, length); 451 request->donecount += length; 452 453 /* set next transfer size according to HW capabilities */ 454 request->transfersize = min((request->bytecount-request->donecount), 455 request->transfersize); 456 /* return wait for interrupt */ 457 return; 458 459 case ATAPI_P_READ: 460 if (request->flags & ATA_R_WRITE) { 461 request->status = ATA_S_ERROR; 462 ata_prtdev(request->device, 463 "%s trying to read on write buffer\n", 464 ata_cmd2str(request)); 465 break; 466 } 467 ata_pio_read(request, length); 468 request->donecount += length; 469 470 /* set next transfer size according to HW capabilities */ 471 request->transfersize = min((request->bytecount-request->donecount), 472 request->transfersize); 473 /* return wait for interrupt */ 474 return; 475 476 case ATAPI_P_DONEDRQ: 477 ata_prtdev(request->device, 478 "WARNING - %s DONEDRQ non conformant device\n", 479 ata_cmd2str(request)); 480 if (request->flags & ATA_R_READ) { 481 ata_pio_read(request, length); 482 request->donecount += length; 483 } 484 else if (request->flags & ATA_R_WRITE) { 485 ata_pio_write(request, length); 486 request->donecount += length; 487 } 488 else 489 request->status = ATA_S_ERROR; 490 /* FALLTHROUGH */ 491 492 case ATAPI_P_ABORT: 493 case ATAPI_P_DONE: 494 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 495 request->error = ATA_IDX_INB(ch, ATA_ERROR); 496 break; 497 498 default: 499 ata_prtdev(request->device, "unknown transfer phase\n"); 500 request->status = ATA_S_ERROR; 501 } 502 503 /* done with HW */ 504 break; 505 506 /* ATAPI DMA commands */ 507 case ATA_R_ATAPI|ATA_R_DMA: 508 509 /* stop the engine and get engine status */ 510 if (ch->dma->stop) 511 request->dmastat = ch->dma->stop(ch); 512 513 /* did we get error or data */ 514 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 515 request->error = ATA_IDX_INB(ch, ATA_ERROR); 516 else if (request->dmastat & ATA_BMSTAT_ERROR) 517 request->status |= ATA_S_ERROR; 518 else 519 request->donecount = request->bytecount; 520 521 /* release SG list etc */ 522 ch->dma->unload(ch); 523 524 /* done with HW */ 525 break; 526 } 527 528 /* finished running this request schedule completition */ 529 ch->running = NULL; 530 ata_finish(request); 531 } 532 533 /* must be called with ATA channel locked */ 534 static void 535 ata_generic_reset(struct ata_channel *ch) 536 { 537 u_int8_t err, lsb, msb, ostat0, ostat1; 538 u_int8_t stat0 = 0, stat1 = 0; 539 int mask = 0, timeout; 540 541 /* if DMA functionality present stop it */ 542 if (ch->dma) { 543 if (ch->dma->stop) 544 ch->dma->stop(ch); 545 if (ch->dma->flags & ATA_DMA_LOADED) 546 ch->dma->unload(ch); 547 } 548 549 /* reset host end of channel (if supported) */ 550 if (ch->reset) 551 ch->reset(ch); 552 553 /* do we have any signs of ATA/ATAPI HW being present ? */ 554 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 555 DELAY(10); 556 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 557 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 558 stat0 = ATA_S_BUSY; 559 mask |= 0x01; 560 } 561 562 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 563 DELAY(10); 564 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 565 566 /* in some setups we dont want to test for a slave */ 567 if (!(ch->flags & ATA_NO_SLAVE)) { 568 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 569 stat1 = ATA_S_BUSY; 570 mask |= 0x02; 571 } 572 } 573 574 if (bootverbose) 575 ata_printf(ch, -1, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 576 mask, ostat0, ostat1); 577 578 /* if nothing showed up there is no need to get any further */ 579 /* SOS is that too strong?, we just might loose devices here XXX */ 580 ch->devices = 0; 581 if (!mask) 582 return; 583 584 /* reset (both) devices on this channel */ 585 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 586 DELAY(10); 587 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS | ATA_A_RESET); 588 DELAY(10000); 589 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS); 590 DELAY(100000); 591 ATA_IDX_INB(ch, ATA_ERROR); 592 593 /* wait for BUSY to go inactive */ 594 for (timeout = 0; timeout < 310; timeout++) { 595 if (stat0 & ATA_S_BUSY) { 596 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 597 DELAY(10); 598 err = ATA_IDX_INB(ch, ATA_ERROR); 599 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 600 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 601 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 602 if (bootverbose) 603 ata_printf(ch, ATA_MASTER, 604 "stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 605 stat0, err, lsb, msb); 606 if (!(stat0 & ATA_S_BUSY)) { 607 if ((err & 0x7f) == ATA_E_ILI) { 608 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 609 ch->devices |= ATA_ATAPI_MASTER; 610 } 611 else if (stat0 & ATA_S_READY) { 612 ch->devices |= ATA_ATA_MASTER; 613 } 614 } 615 else if ((stat0 & 0x4f) && err == lsb && err == msb) { 616 stat0 |= ATA_S_BUSY; 617 } 618 } 619 } 620 if (!((mask == 0x03) && (stat0 & ATA_S_BUSY)) && (stat1 & ATA_S_BUSY)) { 621 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 622 DELAY(10); 623 err = ATA_IDX_INB(ch, ATA_ERROR); 624 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 625 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 626 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 627 if (bootverbose) 628 ata_printf(ch, ATA_SLAVE, 629 " stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 630 stat1, err, lsb, msb); 631 if (!(stat1 & ATA_S_BUSY)) { 632 if ((err & 0x7f) == ATA_E_ILI) { 633 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 634 ch->devices |= ATA_ATAPI_SLAVE; 635 } 636 else if (stat1 & ATA_S_READY) { 637 ch->devices |= ATA_ATA_SLAVE; 638 } 639 } 640 else if ((stat1 & 0x4f) && err == lsb && err == msb) { 641 stat1 |= ATA_S_BUSY; 642 } 643 } 644 } 645 if (mask == 0x01) /* wait for master only */ 646 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 5)) 647 break; 648 if (mask == 0x02) /* wait for slave only */ 649 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 5)) 650 break; 651 if (mask == 0x03) { /* wait for both master & slave */ 652 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 653 break; 654 if (stat0 == 0xff && timeout > 5) 655 mask &= ~0x01; 656 if (stat1 == 0xff && timeout > 5) 657 mask &= ~0x02; 658 } 659 DELAY(100000); 660 } 661 662 if (bootverbose) 663 ata_printf(ch, -1, 664 "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n", 665 stat0, stat1, ch->devices, 666 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 667 } 668 669 static int 670 ata_wait(struct ata_device *atadev, u_int8_t mask) 671 { 672 u_int8_t status; 673 int timeout = 0; 674 675 DELAY(1); 676 677 /* wait 5 seconds for device to get !BUSY */ 678 while (timeout < 5000000) { 679 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 680 681 /* if drive fails status, reselect the drive just to be sure */ 682 if (status == 0xff) { 683 ata_prtdev(atadev, "WARNING no status, reselecting device\n"); 684 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit); 685 DELAY(10); 686 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 687 if (status == 0xff) 688 return -1; 689 } 690 691 /* are we done ? */ 692 if (!(status & ATA_S_BUSY)) 693 break; 694 695 if (timeout > 1000) { 696 timeout += 1000; 697 DELAY(1000); 698 } 699 else { 700 timeout += 10; 701 DELAY(10); 702 } 703 } 704 if (timeout >= 5000000) 705 return -1; 706 if (!mask) 707 return (status & ATA_S_ERROR); 708 709 DELAY(1); 710 711 /* wait 50 msec for bits wanted */ 712 timeout = 5000; 713 while (timeout--) { 714 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 715 if ((status & mask) == mask) 716 return (status & ATA_S_ERROR); 717 DELAY (10); 718 } 719 return -1; 720 } 721 722 int 723 ata_generic_command(struct ata_device *atadev, u_int8_t command, 724 u_int64_t lba, u_int16_t count, u_int16_t feature) 725 { 726 if (atadebug) 727 ata_prtdev(atadev, "ata_command: addr=%04lx, command=%02x, " 728 "lba=%jd, count=%d, feature=%d\n", 729 rman_get_start(atadev->channel->r_io[ATA_DATA].res), 730 command, (intmax_t)lba, count, feature); 731 732 /* select device */ 733 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit); 734 735 /* ready to issue command ? */ 736 if (ata_wait(atadev, 0) < 0) { 737 ata_prtdev(atadev, "timeout sending command=%02x\n", command); 738 return -1; 739 } 740 741 /* enable interrupt */ 742 ATA_IDX_OUTB(atadev->channel, ATA_ALTSTAT, ATA_A_4BIT); 743 744 /* only use 48bit addressing if needed (avoid bugs and overhead) */ 745 if ((lba > 268435455 || count > 256) && atadev->param && 746 atadev->param->support.command2 & ATA_SUPPORT_ADDRESS48) { 747 748 /* translate command into 48bit version */ 749 switch (command) { 750 case ATA_READ: 751 command = ATA_READ48; break; 752 case ATA_READ_MUL: 753 command = ATA_READ_MUL48; break; 754 case ATA_READ_DMA: 755 command = ATA_READ_DMA48; break; 756 case ATA_READ_DMA_QUEUED: 757 command = ATA_READ_DMA_QUEUED48; break; 758 case ATA_WRITE: 759 command = ATA_WRITE48; break; 760 case ATA_WRITE_MUL: 761 command = ATA_WRITE_MUL48; break; 762 case ATA_WRITE_DMA: 763 command = ATA_WRITE_DMA48; break; 764 case ATA_WRITE_DMA_QUEUED: 765 command = ATA_WRITE_DMA_QUEUED48; break; 766 case ATA_FLUSHCACHE: 767 command = ATA_FLUSHCACHE48; break; 768 default: 769 ata_prtdev(atadev, "can't translate cmd to 48bit version\n"); 770 return -1; 771 } 772 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, (feature>>8) & 0xff); 773 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature & 0xff); 774 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, (count>>8) & 0xff); 775 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count & 0xff); 776 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, (lba>>24) & 0xff); 777 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff); 778 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>32) & 0xff); 779 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff); 780 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>40) & 0xff); 781 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff); 782 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_LBA | atadev->unit); 783 atadev->channel->flags |= ATA_48BIT_ACTIVE; 784 } 785 else { 786 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature); 787 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count); 788 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff); 789 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff); 790 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff); 791 if (atadev->flags & ATA_D_USE_CHS) 792 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, 793 ATA_D_IBM | atadev->unit | ((lba>>24) & 0xf)); 794 else 795 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, 796 ATA_D_IBM | ATA_D_LBA | atadev->unit|((lba>>24)&0xf)); 797 atadev->channel->flags &= ~ATA_48BIT_ACTIVE; 798 } 799 800 /* issue command to controller */ 801 ATA_IDX_OUTB(atadev->channel, ATA_CMD, command); 802 803 return 0; 804 } 805 806 static void 807 ata_pio_read(struct ata_request *request, int length) 808 { 809 int size = min(request->transfersize, length); 810 struct ata_channel *ch = request->device->channel; 811 int resid; 812 813 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 814 ATA_IDX_INSW_STRM(ch, ATA_DATA, 815 (void*)((uintptr_t)request->data+request->donecount), 816 size / sizeof(int16_t)); 817 else 818 ATA_IDX_INSL_STRM(ch, ATA_DATA, 819 (void*)((uintptr_t)request->data+request->donecount), 820 size / sizeof(int32_t)); 821 822 if (request->transfersize < length) { 823 ata_prtdev(request->device, "WARNING - %s read data overrun %d>%d\n", 824 ata_cmd2str(request), length, request->transfersize); 825 for (resid = request->transfersize; resid < length; 826 resid += sizeof(int16_t)) 827 ATA_IDX_INW(ch, ATA_DATA); 828 } 829 } 830 831 static void 832 ata_pio_write(struct ata_request *request, int length) 833 { 834 int size = min(request->transfersize, length); 835 struct ata_channel *ch = request->device->channel; 836 int resid; 837 838 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 839 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 840 (void*)((uintptr_t)request->data+request->donecount), 841 size / sizeof(int16_t)); 842 else 843 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 844 (void*)((uintptr_t)request->data+request->donecount), 845 size / sizeof(int32_t)); 846 847 if (request->transfersize < length) { 848 ata_prtdev(request->device, "WARNING - %s write data underrun %d>%d\n", 849 ata_cmd2str(request), length, request->transfersize); 850 for (resid = request->transfersize; resid < length; 851 resid += sizeof(int16_t)) 852 ATA_IDX_OUTW(ch, ATA_DATA, 0); 853 } 854 } 855