1 /*- 2 * Copyright (c) 1998 - 2004 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_ata.h" 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/ata.h> 36 #include <sys/kernel.h> 37 #include <sys/conf.h> 38 #include <sys/bus.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/ata/ata-all.h> 45 46 /* prototypes */ 47 static int ata_begin_transaction(struct ata_request *); 48 static int ata_end_transaction(struct ata_request *); 49 static void ata_generic_reset(struct ata_channel *); 50 static int ata_wait(struct ata_device *, u_int8_t); 51 static void ata_pio_read(struct ata_request *, int); 52 static void ata_pio_write(struct ata_request *, int); 53 54 /* local vars */ 55 static int atadebug = 0; 56 57 /* 58 * low level ATA functions 59 */ 60 void 61 ata_generic_hw(struct ata_channel *ch) 62 { 63 ch->hw.begin_transaction = ata_begin_transaction; 64 ch->hw.end_transaction = ata_end_transaction; 65 ch->hw.reset = ata_generic_reset; 66 ch->hw.command = ata_generic_command; 67 } 68 69 /* must be called with ATA channel locked */ 70 static int 71 ata_begin_transaction(struct ata_request *request) 72 { 73 struct ata_channel *ch = request->device->channel; 74 75 /* safetybelt for HW that went away */ 76 if (!request->device->param || request->device->channel->flags&ATA_HWGONE) { 77 request->retries = 0; 78 request->result = ENXIO; 79 return ATA_OP_FINISHED; 80 } 81 82 ATA_DEBUG_RQ(request, "begin transaction"); 83 84 /* disable ATAPI DMA writes if HW doesn't support it */ 85 if ((ch->flags & ATA_ATAPI_DMA_RO) && 86 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 87 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 88 request->flags &= ~ATA_R_DMA; 89 90 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 91 92 /* ATA PIO data transfer and control commands */ 93 default: 94 { 95 /* record command direction here as our request might be gone later */ 96 int write = (request->flags & ATA_R_WRITE); 97 98 /* issue command */ 99 if (ch->hw.command(request->device, request->u.ata.command, 100 request->u.ata.lba, request->u.ata.count, 101 request->u.ata.feature)) { 102 ata_prtdev(request->device, "error issueing %s command\n", 103 ata_cmd2str(request)); 104 request->result = EIO; 105 break; 106 } 107 108 /* device reset doesn't interrupt */ 109 if (request->u.ata.command == ATA_ATAPI_RESET) { 110 int timeout = 1000000; 111 do { 112 DELAY(10); 113 request->status = ATA_IDX_INB(ch, ATA_STATUS); 114 } while (request->status & ATA_S_BUSY && timeout--); 115 if (request->status & ATA_S_ERROR) 116 request->error = ATA_IDX_INB(ch, ATA_ERROR); 117 break; 118 } 119 120 /* if write command output the data */ 121 if (write) { 122 if (ata_wait(request->device, 123 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 124 ata_prtdev(request->device,"timeout waiting for write DRQ"); 125 request->result = EIO; 126 break; 127 } 128 ata_pio_write(request, request->transfersize); 129 } 130 } 131 return ATA_OP_CONTINUES; 132 133 /* ATA DMA data transfer commands */ 134 case ATA_R_DMA: 135 /* check sanity, setup SG list and DMA engine */ 136 if (ch->dma->load(request->device, request->data, request->bytecount, 137 request->flags & ATA_R_READ)) { 138 ata_prtdev(request->device, "setting up DMA failed\n"); 139 request->result = EIO; 140 break; 141 } 142 143 /* issue command */ 144 if (ch->hw.command(request->device, request->u.ata.command, 145 request->u.ata.lba, request->u.ata.count, 146 request->u.ata.feature)) { 147 ata_prtdev(request->device, "error issueing %s command\n", 148 ata_cmd2str(request)); 149 request->result = EIO; 150 break; 151 } 152 153 /* start DMA engine */ 154 if (ch->dma->start(ch)) { 155 ata_prtdev(request->device, "error starting DMA\n"); 156 request->result = EIO; 157 break; 158 } 159 return ATA_OP_CONTINUES; 160 161 /* ATAPI PIO commands */ 162 case ATA_R_ATAPI: 163 /* is this just a POLL DSC command ? */ 164 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 165 ATA_IDX_OUTB(ch, ATA_DRIVE, 166 ATA_D_IBM | request->device->unit); 167 DELAY(10); 168 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC)) 169 request->result = EBUSY; 170 break; 171 } 172 173 /* start ATAPI operation */ 174 if (ch->hw.command(request->device, ATA_PACKET_CMD, 175 request->transfersize << 8, 0, 0)) { 176 ata_prtdev(request->device, "error issuing ATA PACKET command\n"); 177 request->result = EIO; 178 break; 179 } 180 181 /* command interrupt device ? just return and wait for interrupt */ 182 if ((request->device->param->config & ATA_DRQ_MASK) == ATA_DRQ_INTR) 183 return ATA_OP_CONTINUES; 184 185 /* wait for ready to write ATAPI command block */ 186 { 187 int timeout = 5000; /* might be less for fast devices */ 188 while (timeout--) { 189 int reason = ATA_IDX_INB(ch, ATA_IREASON); 190 int status = ATA_IDX_INB(ch, ATA_STATUS); 191 192 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 193 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 194 break; 195 DELAY(20); 196 } 197 if (timeout <= 0) { 198 ata_prtdev(request->device, 199 "timeout waiting for ATAPI ready\n"); 200 request->result = EIO; 201 break; 202 } 203 } 204 205 /* this seems to be needed for some (slow) devices */ 206 DELAY(10); 207 208 /* output actual command block */ 209 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 210 (int16_t *)request->u.atapi.ccb, 211 (request->device->param->config & ATA_PROTO_MASK) == 212 ATA_PROTO_ATAPI_12 ? 6 : 8); 213 return ATA_OP_CONTINUES; 214 215 case ATA_R_ATAPI|ATA_R_DMA: 216 /* is this just a POLL DSC command ? */ 217 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 218 ATA_IDX_OUTB(ch, ATA_DRIVE, 219 ATA_D_IBM | request->device->unit); 220 DELAY(10); 221 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC)) 222 request->result = EBUSY; 223 break; 224 } 225 226 /* check sanity, setup SG list and DMA engine */ 227 if (ch->dma->load(request->device, 228 request->data, 229 request->bytecount, 230 request->flags & ATA_R_READ)) { 231 ata_prtdev(request->device, "setting up DMA failed\n"); 232 request->result = EIO; 233 break; 234 } 235 236 /* start ATAPI operation */ 237 if (ch->hw.command(request->device, ATA_PACKET_CMD, 0, 0, ATA_F_DMA)) { 238 ata_prtdev(request->device, "error issuing ATAPI packet command\n"); 239 request->result = EIO; 240 break; 241 } 242 243 /* wait for ready to write ATAPI command block */ 244 { 245 int timeout = 5000; /* might be less for fast devices */ 246 while (timeout--) { 247 int reason = ATA_IDX_INB(ch, ATA_IREASON); 248 int status = ATA_IDX_INB(ch, ATA_STATUS); 249 250 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 251 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 252 break; 253 DELAY(20); 254 } 255 if (timeout <= 0) { 256 ata_prtdev(request->device,"timeout waiting for ATAPI ready\n"); 257 request->result = EIO; 258 break; 259 } 260 } 261 262 /* this seems to be needed for some (slow) devices */ 263 DELAY(10); 264 265 /* output actual command block */ 266 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 267 (int16_t *)request->u.atapi.ccb, 268 (request->device->param->config & ATA_PROTO_MASK) == 269 ATA_PROTO_ATAPI_12 ? 6 : 8); 270 271 /* start DMA engine */ 272 if (ch->dma->start(ch)) { 273 request->result = EIO; 274 break; 275 } 276 return ATA_OP_CONTINUES; 277 } 278 279 /* request finish here */ 280 if (ch->dma && ch->dma->flags & ATA_DMA_LOADED) 281 ch->dma->unload(ch); 282 return ATA_OP_FINISHED; 283 } 284 285 static int 286 ata_end_transaction(struct ata_request *request) 287 { 288 struct ata_channel *ch = request->device->channel; 289 int length; 290 291 ATA_DEBUG_RQ(request, "end transaction"); 292 293 /* clear interrupt and get status */ 294 request->status = ATA_IDX_INB(ch, ATA_STATUS); 295 296 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 297 298 /* ATA PIO data transfer and control commands */ 299 default: 300 301 /* on control commands read back registers to the request struct */ 302 if (request->flags & ATA_R_CONTROL) { 303 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 304 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 305 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 306 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 307 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0x0f) << 24); 308 } 309 310 /* if we got an error we are done with the HW */ 311 if (request->status & ATA_S_ERROR) { 312 request->error = ATA_IDX_INB(ch, ATA_ERROR); 313 return ATA_OP_FINISHED; 314 } 315 316 /* are we moving data ? */ 317 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 318 319 /* if read data get it */ 320 if (request->flags & ATA_R_READ) 321 ata_pio_read(request, request->transfersize); 322 323 /* update how far we've gotten */ 324 request->donecount += request->transfersize; 325 326 /* do we need a scoop more ? */ 327 if (request->bytecount > request->donecount) { 328 329 /* set this transfer size according to HW capabilities */ 330 request->transfersize = 331 min((request->bytecount - request->donecount), 332 request->transfersize); 333 334 /* clear interrupt seen flag as we need to wait again */ 335 request->flags &= ~ATA_R_INTR_SEEN; 336 337 /* if data write command, output the data */ 338 if (request->flags & ATA_R_WRITE) { 339 340 /* if we get an error here we are done with the HW */ 341 if (ata_wait(request->device, 342 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 343 ata_prtdev(request->device, 344 "timeout waiting for write DRQ"); 345 request->status = ATA_IDX_INB(ch, ATA_STATUS); 346 return ATA_OP_FINISHED; 347 } 348 349 /* output data and return waiting for new interrupt */ 350 ata_pio_write(request, request->transfersize); 351 return ATA_OP_CONTINUES; 352 } 353 354 /* if data read command, return & wait for interrupt */ 355 if (request->flags & ATA_R_READ) 356 return ATA_OP_CONTINUES; 357 } 358 } 359 /* done with HW */ 360 return ATA_OP_FINISHED; 361 362 /* ATA DMA data transfer commands */ 363 case ATA_R_DMA: 364 365 /* stop DMA engine and get status */ 366 if (ch->dma->stop) 367 request->dmastat = ch->dma->stop(ch); 368 369 /* did we get error or data */ 370 if (request->status & ATA_S_ERROR) 371 request->error = ATA_IDX_INB(ch, ATA_ERROR); 372 else if (request->dmastat & ATA_BMSTAT_ERROR) 373 request->status |= ATA_S_ERROR; 374 else 375 request->donecount = request->bytecount; 376 377 /* release SG list etc */ 378 ch->dma->unload(ch); 379 380 /* done with HW */ 381 return ATA_OP_FINISHED; 382 383 /* ATAPI PIO commands */ 384 case ATA_R_ATAPI: 385 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 386 387 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 388 (request->status & ATA_S_DRQ)) { 389 390 case ATAPI_P_CMDOUT: 391 /* this seems to be needed for some (slow) devices */ 392 DELAY(10); 393 394 if (!(request->status & ATA_S_DRQ)) { 395 ata_prtdev(request->device, "command interrupt without DRQ\n"); 396 request->status = ATA_S_ERROR; 397 return ATA_OP_FINISHED; 398 } 399 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 400 (request->device->param->config & 401 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); 402 /* return wait for interrupt */ 403 return ATA_OP_CONTINUES; 404 405 case ATAPI_P_WRITE: 406 if (request->flags & ATA_R_READ) { 407 request->status = ATA_S_ERROR; 408 ata_prtdev(request->device, 409 "%s trying to write on read buffer\n", 410 ata_cmd2str(request)); 411 return ATA_OP_FINISHED; 412 } 413 ata_pio_write(request, length); 414 request->donecount += length; 415 416 /* set next transfer size according to HW capabilities */ 417 request->transfersize = min((request->bytecount-request->donecount), 418 request->transfersize); 419 /* return wait for interrupt */ 420 return ATA_OP_CONTINUES; 421 422 case ATAPI_P_READ: 423 if (request->flags & ATA_R_WRITE) { 424 request->status = ATA_S_ERROR; 425 ata_prtdev(request->device, 426 "%s trying to read on write buffer\n", 427 ata_cmd2str(request)); 428 return ATA_OP_FINISHED; 429 } 430 ata_pio_read(request, length); 431 request->donecount += length; 432 433 /* set next transfer size according to HW capabilities */ 434 request->transfersize = min((request->bytecount-request->donecount), 435 request->transfersize); 436 /* return wait for interrupt */ 437 return ATA_OP_CONTINUES; 438 439 case ATAPI_P_DONEDRQ: 440 ata_prtdev(request->device, 441 "WARNING - %s DONEDRQ non conformant device\n", 442 ata_cmd2str(request)); 443 if (request->flags & ATA_R_READ) { 444 ata_pio_read(request, length); 445 request->donecount += length; 446 } 447 else if (request->flags & ATA_R_WRITE) { 448 ata_pio_write(request, length); 449 request->donecount += length; 450 } 451 else 452 request->status = ATA_S_ERROR; 453 /* FALLTHROUGH */ 454 455 case ATAPI_P_ABORT: 456 case ATAPI_P_DONE: 457 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 458 request->error = ATA_IDX_INB(ch, ATA_ERROR); 459 return ATA_OP_FINISHED; 460 461 default: 462 ata_prtdev(request->device, "unknown transfer phase\n"); 463 request->status = ATA_S_ERROR; 464 } 465 466 /* done with HW */ 467 return ATA_OP_FINISHED; 468 469 /* ATAPI DMA commands */ 470 case ATA_R_ATAPI|ATA_R_DMA: 471 472 /* stop the engine and get engine status */ 473 if (ch->dma->stop) 474 request->dmastat = ch->dma->stop(ch); 475 476 /* did we get error or data */ 477 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 478 request->error = ATA_IDX_INB(ch, ATA_ERROR); 479 else if (request->dmastat & ATA_BMSTAT_ERROR) 480 request->status |= ATA_S_ERROR; 481 else 482 request->donecount = request->bytecount; 483 484 /* release SG list etc */ 485 ch->dma->unload(ch); 486 487 /* done with HW */ 488 return ATA_OP_FINISHED; 489 } 490 } 491 492 /* must be called with ATA channel locked */ 493 static void 494 ata_generic_reset(struct ata_channel *ch) 495 { 496 u_int8_t err = 0, lsb = 0, msb = 0, ostat0, ostat1; 497 u_int8_t stat0 = 0, stat1 = 0; 498 int mask = 0, timeout; 499 500 /* if DMA functionality present stop it */ 501 if (ch->dma) { 502 if (ch->dma->stop) 503 ch->dma->stop(ch); 504 if (ch->dma->flags & ATA_DMA_LOADED) 505 ch->dma->unload(ch); 506 } 507 508 /* reset host end of channel (if supported) */ 509 if (ch->reset) 510 ch->reset(ch); 511 512 /* do we have any signs of ATA/ATAPI HW being present ? */ 513 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 514 DELAY(10); 515 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 516 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 517 stat0 = ATA_S_BUSY; 518 mask |= 0x01; 519 } 520 521 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 522 DELAY(10); 523 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 524 525 /* in some setups we dont want to test for a slave */ 526 if (!(ch->flags & ATA_NO_SLAVE)) { 527 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 528 stat1 = ATA_S_BUSY; 529 mask |= 0x02; 530 } 531 } 532 533 if (bootverbose) 534 ata_printf(ch, -1, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 535 mask, ostat0, ostat1); 536 537 /* if nothing showed up there is no need to get any further */ 538 /* SOS is that too strong?, we just might loose devices here XXX */ 539 ch->devices = 0; 540 if (!mask) 541 return; 542 543 /* reset (both) devices on this channel */ 544 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 545 DELAY(10); 546 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS | ATA_A_RESET); 547 ata_udelay(10000); 548 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS); 549 ata_udelay(100000); 550 ATA_IDX_INB(ch, ATA_ERROR); 551 552 /* wait for BUSY to go inactive */ 553 for (timeout = 0; timeout < 310; timeout++) { 554 if (stat0 & ATA_S_BUSY) { 555 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 556 DELAY(10); 557 err = ATA_IDX_INB(ch, ATA_ERROR); 558 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 559 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 560 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 561 if (bootverbose) 562 ata_printf(ch, ATA_MASTER, 563 "stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 564 stat0, err, lsb, msb); 565 if (!(stat0 & ATA_S_BUSY)) { 566 if ((err & 0x7f) == ATA_E_ILI) { 567 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 568 ch->devices |= ATA_ATAPI_MASTER; 569 } 570 else if (stat0 & ATA_S_READY) { 571 ch->devices |= ATA_ATA_MASTER; 572 } 573 } 574 else if ((stat0 & 0x4f) && err == lsb && err == msb) { 575 stat0 |= ATA_S_BUSY; 576 } 577 } 578 } 579 if (!((mask == 0x03) && (stat0 & ATA_S_BUSY)) && (stat1 & ATA_S_BUSY)) { 580 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 581 DELAY(10); 582 err = ATA_IDX_INB(ch, ATA_ERROR); 583 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 584 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 585 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 586 if (bootverbose) 587 ata_printf(ch, ATA_SLAVE, 588 " stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 589 stat1, err, lsb, msb); 590 if (!(stat1 & ATA_S_BUSY)) { 591 if ((err & 0x7f) == ATA_E_ILI) { 592 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 593 ch->devices |= ATA_ATAPI_SLAVE; 594 } 595 else if (stat1 & ATA_S_READY) { 596 ch->devices |= ATA_ATA_SLAVE; 597 } 598 } 599 else if ((stat1 & 0x4f) && err == lsb && err == msb) { 600 stat1 |= ATA_S_BUSY; 601 } 602 } 603 } 604 if (mask == 0x01) /* wait for master only */ 605 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 5) || 606 (stat0 == err && lsb == err && msb == err && timeout > 5)) 607 break; 608 if (mask == 0x02) /* wait for slave only */ 609 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 5) || 610 (stat1 == err && lsb == err && msb == err && timeout > 5)) 611 break; 612 if (mask == 0x03) { /* wait for both master & slave */ 613 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 614 break; 615 if ((stat0 == 0xff && timeout > 5) || 616 (stat0 == err && lsb == err && msb == err && timeout > 5)) 617 mask &= ~0x01; 618 if ((stat1 == 0xff && timeout > 5) || 619 (stat1 == err && lsb == err && msb == err && timeout > 5)) 620 mask &= ~0x02; 621 } 622 ata_udelay(100000); 623 } 624 625 if (bootverbose) 626 ata_printf(ch, -1, 627 "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n", 628 stat0, stat1, ch->devices, 629 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 630 } 631 632 static int 633 ata_wait(struct ata_device *atadev, u_int8_t mask) 634 { 635 u_int8_t status; 636 int timeout = 0; 637 638 DELAY(1); 639 640 /* wait 5 seconds for device to get !BUSY */ 641 while (timeout < 5000000) { 642 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 643 644 /* if drive fails status, reselect the drive just to be sure */ 645 if (status == 0xff) { 646 ata_prtdev(atadev, "WARNING no status, reselecting device\n"); 647 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit); 648 DELAY(10); 649 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 650 if (status == 0xff) 651 return -1; 652 } 653 654 /* are we done ? */ 655 if (!(status & ATA_S_BUSY)) 656 break; 657 658 if (timeout > 1000) { 659 timeout += 1000; 660 DELAY(1000); 661 } 662 else { 663 timeout += 10; 664 DELAY(10); 665 } 666 } 667 if (timeout >= 5000000) 668 return -1; 669 if (!mask) 670 return (status & ATA_S_ERROR); 671 672 DELAY(1); 673 674 /* wait 50 msec for bits wanted */ 675 timeout = 5000; 676 while (timeout--) { 677 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 678 if ((status & mask) == mask) 679 return (status & ATA_S_ERROR); 680 DELAY (10); 681 } 682 return -1; 683 } 684 685 int 686 ata_generic_command(struct ata_device *atadev, u_int8_t command, 687 u_int64_t lba, u_int16_t count, u_int16_t feature) 688 { 689 if (atadebug) 690 ata_prtdev(atadev, "ata_command: addr=%04lx, command=%02x, " 691 "lba=%jd, count=%d, feature=%d\n", 692 rman_get_start(atadev->channel->r_io[ATA_DATA].res), 693 command, (intmax_t)lba, count, feature); 694 695 /* select device */ 696 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit); 697 698 /* ready to issue command ? */ 699 if (ata_wait(atadev, 0) < 0) { 700 ata_prtdev(atadev, "timeout sending command=%02x\n", command); 701 return -1; 702 } 703 704 /* enable interrupt */ 705 ATA_IDX_OUTB(atadev->channel, ATA_ALTSTAT, ATA_A_4BIT); 706 707 /* only use 48bit addressing if needed (avoid bugs and overhead) */ 708 if ((lba >= ATA_MAX_28BIT_LBA || count > 256) && atadev->param && 709 atadev->param->support.command2 & ATA_SUPPORT_ADDRESS48) { 710 711 /* translate command into 48bit version */ 712 switch (command) { 713 case ATA_READ: 714 command = ATA_READ48; break; 715 case ATA_READ_MUL: 716 command = ATA_READ_MUL48; break; 717 case ATA_READ_DMA: 718 command = ATA_READ_DMA48; break; 719 case ATA_READ_DMA_QUEUED: 720 command = ATA_READ_DMA_QUEUED48; break; 721 case ATA_WRITE: 722 command = ATA_WRITE48; break; 723 case ATA_WRITE_MUL: 724 command = ATA_WRITE_MUL48; break; 725 case ATA_WRITE_DMA: 726 command = ATA_WRITE_DMA48; break; 727 case ATA_WRITE_DMA_QUEUED: 728 command = ATA_WRITE_DMA_QUEUED48; break; 729 case ATA_FLUSHCACHE: 730 command = ATA_FLUSHCACHE48; break; 731 default: 732 ata_prtdev(atadev, "can't translate cmd to 48bit version\n"); 733 return -1; 734 } 735 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, (feature>>8) & 0xff); 736 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature & 0xff); 737 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, (count>>8) & 0xff); 738 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count & 0xff); 739 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, (lba>>24) & 0xff); 740 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff); 741 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>32) & 0xff); 742 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff); 743 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>40) & 0xff); 744 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff); 745 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_LBA | atadev->unit); 746 atadev->channel->flags |= ATA_48BIT_ACTIVE; 747 } 748 else { 749 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature); 750 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count); 751 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff); 752 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff); 753 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff); 754 if (atadev->flags & ATA_D_USE_CHS) 755 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, 756 ATA_D_IBM | atadev->unit | ((lba>>24) & 0xf)); 757 else 758 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, 759 ATA_D_IBM | ATA_D_LBA | atadev->unit|((lba>>24)&0xf)); 760 atadev->channel->flags &= ~ATA_48BIT_ACTIVE; 761 } 762 763 /* issue command to controller */ 764 ATA_IDX_OUTB(atadev->channel, ATA_CMD, command); 765 766 return 0; 767 } 768 769 static void 770 ata_pio_read(struct ata_request *request, int length) 771 { 772 int size = min(request->transfersize, length); 773 struct ata_channel *ch = request->device->channel; 774 int resid; 775 776 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 777 ATA_IDX_INSW_STRM(ch, ATA_DATA, 778 (void*)((uintptr_t)request->data+request->donecount), 779 size / sizeof(int16_t)); 780 else 781 ATA_IDX_INSL_STRM(ch, ATA_DATA, 782 (void*)((uintptr_t)request->data+request->donecount), 783 size / sizeof(int32_t)); 784 785 if (request->transfersize < length) { 786 ata_prtdev(request->device, "WARNING - %s read data overrun %d>%d\n", 787 ata_cmd2str(request), length, request->transfersize); 788 for (resid = request->transfersize; resid < length; 789 resid += sizeof(int16_t)) 790 ATA_IDX_INW(ch, ATA_DATA); 791 } 792 } 793 794 static void 795 ata_pio_write(struct ata_request *request, int length) 796 { 797 int size = min(request->transfersize, length); 798 struct ata_channel *ch = request->device->channel; 799 int resid; 800 801 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 802 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 803 (void*)((uintptr_t)request->data+request->donecount), 804 size / sizeof(int16_t)); 805 else 806 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 807 (void*)((uintptr_t)request->data+request->donecount), 808 size / sizeof(int32_t)); 809 810 if (request->transfersize < length) { 811 ata_prtdev(request->device, "WARNING - %s write data underrun %d>%d\n", 812 ata_cmd2str(request), length, request->transfersize); 813 for (resid = request->transfersize; resid < length; 814 resid += sizeof(int16_t)) 815 ATA_IDX_OUTW(ch, ATA_DATA, 0); 816 } 817 } 818