1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/endian.h> 35 #include <sys/ata.h> 36 #include <sys/conf.h> 37 #include <sys/ctype.h> 38 #include <sys/bus.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/ata/ata-all.h> 45 #include <dev/ata/ata-pci.h> 46 #include <ata_if.h> 47 48 /* prototypes */ 49 static int ata_generic_status(device_t dev); 50 static int ata_wait(struct ata_channel *ch, struct ata_device *, u_int8_t); 51 static void ata_pio_read(struct ata_request *, int); 52 static void ata_pio_write(struct ata_request *, int); 53 static void ata_tf_read(struct ata_request *); 54 static void ata_tf_write(struct ata_request *); 55 56 /* 57 * low level ATA functions 58 */ 59 void 60 ata_generic_hw(device_t dev) 61 { 62 struct ata_channel *ch = device_get_softc(dev); 63 64 ch->hw.begin_transaction = ata_begin_transaction; 65 ch->hw.end_transaction = ata_end_transaction; 66 ch->hw.status = ata_generic_status; 67 ch->hw.softreset = NULL; 68 ch->hw.command = ata_generic_command; 69 ch->hw.tf_read = ata_tf_read; 70 ch->hw.tf_write = ata_tf_write; 71 ch->hw.pm_read = NULL; 72 ch->hw.pm_write = NULL; 73 } 74 75 /* must be called with ATA channel locked and state_mtx held */ 76 int 77 ata_begin_transaction(struct ata_request *request) 78 { 79 struct ata_channel *ch = device_get_softc(request->parent); 80 struct ata_device *atadev = device_get_softc(request->dev); 81 int dummy, error; 82 83 ATA_DEBUG_RQ(request, "begin transaction"); 84 85 /* disable ATAPI DMA writes if HW doesn't support it */ 86 if ((ch->flags & ATA_ATAPI_DMA_RO) && 87 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 88 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 89 request->flags &= ~ATA_R_DMA; 90 91 /* check for 48 bit access and convert if needed */ 92 ata_modify_if_48bit(request); 93 94 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 95 96 /* ATA PIO data transfer and control commands */ 97 default: 98 { 99 /* record command direction here as our request might be gone later */ 100 int write = (request->flags & ATA_R_WRITE); 101 102 /* issue command */ 103 if (ch->hw.command(request)) { 104 device_printf(request->dev, "error issuing %s command\n", 105 ata_cmd2str(request)); 106 request->result = EIO; 107 goto begin_finished; 108 } 109 110 /* device reset doesn't interrupt */ 111 if (request->u.ata.command == ATA_DEVICE_RESET) { 112 113 int timeout = 1000000; 114 do { 115 DELAY(10); 116 request->status = ATA_IDX_INB(ch, ATA_STATUS); 117 } while (request->status & ATA_S_BUSY && timeout--); 118 if (request->status & ATA_S_ERROR) 119 request->error = ATA_IDX_INB(ch, ATA_ERROR); 120 goto begin_finished; 121 } 122 123 /* if write command output the data */ 124 if (write) { 125 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) { 126 device_printf(request->dev, 127 "timeout waiting for write DRQ\n"); 128 request->result = EIO; 129 goto begin_finished; 130 } 131 ata_pio_write(request, request->transfersize); 132 } 133 } 134 goto begin_continue; 135 136 /* ATA DMA data transfer commands */ 137 case ATA_R_DMA: 138 /* check sanity, setup SG list and DMA engine */ 139 if ((error = ch->dma.load(request, NULL, &dummy))) { 140 device_printf(request->dev, "setting up DMA failed\n"); 141 request->result = error; 142 goto begin_finished; 143 } 144 145 /* issue command */ 146 if (ch->hw.command(request)) { 147 device_printf(request->dev, "error issuing %s command\n", 148 ata_cmd2str(request)); 149 request->result = EIO; 150 goto begin_finished; 151 } 152 153 /* start DMA engine */ 154 if (ch->dma.start && ch->dma.start(request)) { 155 device_printf(request->dev, "error starting DMA\n"); 156 request->result = EIO; 157 goto begin_finished; 158 } 159 goto begin_continue; 160 161 /* ATAPI PIO commands */ 162 case ATA_R_ATAPI: 163 /* is this just a POLL DSC command ? */ 164 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 165 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit)); 166 DELAY(10); 167 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 168 request->result = EBUSY; 169 goto begin_finished; 170 } 171 172 /* start ATAPI operation */ 173 if (ch->hw.command(request)) { 174 device_printf(request->dev, "error issuing ATA PACKET command\n"); 175 request->result = EIO; 176 goto begin_finished; 177 } 178 goto begin_continue; 179 180 /* ATAPI DMA commands */ 181 case ATA_R_ATAPI|ATA_R_DMA: 182 /* is this just a POLL DSC command ? */ 183 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 184 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit)); 185 DELAY(10); 186 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 187 request->result = EBUSY; 188 goto begin_finished; 189 } 190 191 /* check sanity, setup SG list and DMA engine */ 192 if ((error = ch->dma.load(request, NULL, &dummy))) { 193 device_printf(request->dev, "setting up DMA failed\n"); 194 request->result = error; 195 goto begin_finished; 196 } 197 198 /* start ATAPI operation */ 199 if (ch->hw.command(request)) { 200 device_printf(request->dev, "error issuing ATA PACKET command\n"); 201 request->result = EIO; 202 goto begin_finished; 203 } 204 205 /* start DMA engine */ 206 if (ch->dma.start && ch->dma.start(request)) { 207 request->result = EIO; 208 goto begin_finished; 209 } 210 goto begin_continue; 211 } 212 /* NOT REACHED */ 213 printf("ata_begin_transaction OOPS!!!\n"); 214 215 begin_finished: 216 if (ch->dma.unload) { 217 ch->dma.unload(request); 218 } 219 return ATA_OP_FINISHED; 220 221 begin_continue: 222 callout_reset(&request->callout, request->timeout * hz, 223 (timeout_t*)ata_timeout, request); 224 return ATA_OP_CONTINUES; 225 } 226 227 /* must be called with ATA channel locked and state_mtx held */ 228 int 229 ata_end_transaction(struct ata_request *request) 230 { 231 struct ata_channel *ch = device_get_softc(request->parent); 232 struct ata_device *atadev = device_get_softc(request->dev); 233 int length; 234 235 ATA_DEBUG_RQ(request, "end transaction"); 236 237 /* clear interrupt and get status */ 238 request->status = ATA_IDX_INB(ch, ATA_STATUS); 239 240 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 241 242 /* ATA PIO data transfer and control commands */ 243 default: 244 245 /* on timeouts we have no data or anything so just return */ 246 if (request->flags & ATA_R_TIMEOUT) 247 goto end_finished; 248 249 /* on control commands read back registers to the request struct */ 250 if (request->flags & ATA_R_CONTROL) { 251 ch->hw.tf_read(request); 252 } 253 254 /* if we got an error we are done with the HW */ 255 if (request->status & ATA_S_ERROR) { 256 request->error = ATA_IDX_INB(ch, ATA_ERROR); 257 goto end_finished; 258 } 259 260 /* are we moving data ? */ 261 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 262 263 /* if read data get it */ 264 if (request->flags & ATA_R_READ) { 265 int flags = ATA_S_DRQ; 266 267 if (request->u.ata.command != ATA_ATAPI_IDENTIFY) 268 flags |= ATA_S_READY; 269 if (ata_wait(ch, atadev, flags) < 0) { 270 device_printf(request->dev, 271 "timeout waiting for read DRQ\n"); 272 request->result = EIO; 273 goto end_finished; 274 } 275 ata_pio_read(request, request->transfersize); 276 } 277 278 /* update how far we've gotten */ 279 request->donecount += request->transfersize; 280 281 /* do we need a scoop more ? */ 282 if (request->bytecount > request->donecount) { 283 284 /* set this transfer size according to HW capabilities */ 285 request->transfersize = 286 min((request->bytecount - request->donecount), 287 request->transfersize); 288 289 /* if data write command, output the data */ 290 if (request->flags & ATA_R_WRITE) { 291 292 /* if we get an error here we are done with the HW */ 293 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) { 294 device_printf(request->dev, 295 "timeout waiting for write DRQ\n"); 296 request->status = ATA_IDX_INB(ch, ATA_STATUS); 297 goto end_finished; 298 } 299 300 /* output data and return waiting for new interrupt */ 301 ata_pio_write(request, request->transfersize); 302 goto end_continue; 303 } 304 305 /* if data read command, return & wait for interrupt */ 306 if (request->flags & ATA_R_READ) 307 goto end_continue; 308 } 309 } 310 /* done with HW */ 311 goto end_finished; 312 313 /* ATA DMA data transfer commands */ 314 case ATA_R_DMA: 315 316 /* stop DMA engine and get status */ 317 if (ch->dma.stop) 318 request->dma->status = ch->dma.stop(request); 319 320 /* did we get error or data */ 321 if (request->status & ATA_S_ERROR) 322 request->error = ATA_IDX_INB(ch, ATA_ERROR); 323 else if (request->dma->status & ATA_BMSTAT_ERROR) 324 request->status |= ATA_S_ERROR; 325 else if (!(request->flags & ATA_R_TIMEOUT)) 326 request->donecount = request->bytecount; 327 328 /* release SG list etc */ 329 ch->dma.unload(request); 330 331 /* done with HW */ 332 goto end_finished; 333 334 /* ATAPI PIO commands */ 335 case ATA_R_ATAPI: 336 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 337 338 /* on timeouts we have no data or anything so just return */ 339 if (request->flags & ATA_R_TIMEOUT) 340 goto end_finished; 341 342 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 343 (request->status & ATA_S_DRQ)) { 344 345 case ATAPI_P_CMDOUT: 346 /* this seems to be needed for some (slow) devices */ 347 DELAY(10); 348 349 if (!(request->status & ATA_S_DRQ)) { 350 device_printf(request->dev, "command interrupt without DRQ\n"); 351 request->status = ATA_S_ERROR; 352 goto end_finished; 353 } 354 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 355 (atadev->param.config & 356 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); 357 /* return wait for interrupt */ 358 goto end_continue; 359 360 case ATAPI_P_WRITE: 361 if (request->flags & ATA_R_READ) { 362 request->status = ATA_S_ERROR; 363 device_printf(request->dev, 364 "%s trying to write on read buffer\n", 365 ata_cmd2str(request)); 366 goto end_finished; 367 break; 368 } 369 ata_pio_write(request, length); 370 request->donecount += length; 371 372 /* set next transfer size according to HW capabilities */ 373 request->transfersize = min((request->bytecount-request->donecount), 374 request->transfersize); 375 /* return wait for interrupt */ 376 goto end_continue; 377 378 case ATAPI_P_READ: 379 if (request->flags & ATA_R_WRITE) { 380 request->status = ATA_S_ERROR; 381 device_printf(request->dev, 382 "%s trying to read on write buffer\n", 383 ata_cmd2str(request)); 384 goto end_finished; 385 } 386 ata_pio_read(request, length); 387 request->donecount += length; 388 389 /* set next transfer size according to HW capabilities */ 390 request->transfersize = min((request->bytecount-request->donecount), 391 request->transfersize); 392 /* return wait for interrupt */ 393 goto end_continue; 394 395 case ATAPI_P_DONEDRQ: 396 device_printf(request->dev, 397 "WARNING - %s DONEDRQ non conformant device\n", 398 ata_cmd2str(request)); 399 if (request->flags & ATA_R_READ) { 400 ata_pio_read(request, length); 401 request->donecount += length; 402 } 403 else if (request->flags & ATA_R_WRITE) { 404 ata_pio_write(request, length); 405 request->donecount += length; 406 } 407 else 408 request->status = ATA_S_ERROR; 409 /* FALLTHROUGH */ 410 411 case ATAPI_P_ABORT: 412 case ATAPI_P_DONE: 413 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 414 request->error = ATA_IDX_INB(ch, ATA_ERROR); 415 goto end_finished; 416 417 default: 418 device_printf(request->dev, "unknown transfer phase\n"); 419 request->status = ATA_S_ERROR; 420 } 421 422 /* done with HW */ 423 goto end_finished; 424 425 /* ATAPI DMA commands */ 426 case ATA_R_ATAPI|ATA_R_DMA: 427 428 /* stop DMA engine and get status */ 429 if (ch->dma.stop) 430 request->dma->status = ch->dma.stop(request); 431 432 /* did we get error or data */ 433 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 434 request->error = ATA_IDX_INB(ch, ATA_ERROR); 435 else if (request->dma->status & ATA_BMSTAT_ERROR) 436 request->status |= ATA_S_ERROR; 437 else if (!(request->flags & ATA_R_TIMEOUT)) 438 request->donecount = request->bytecount; 439 440 /* release SG list etc */ 441 ch->dma.unload(request); 442 443 /* done with HW */ 444 goto end_finished; 445 } 446 /* NOT REACHED */ 447 printf("ata_end_transaction OOPS!!\n"); 448 449 end_finished: 450 callout_stop(&request->callout); 451 return ATA_OP_FINISHED; 452 453 end_continue: 454 return ATA_OP_CONTINUES; 455 } 456 457 /* must be called with ATA channel locked and state_mtx held */ 458 void 459 ata_generic_reset(device_t dev) 460 { 461 struct ata_channel *ch = device_get_softc(dev); 462 463 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0; 464 u_int8_t err = 0, lsb = 0, msb = 0; 465 int mask = 0, timeout; 466 467 /* do we have any signs of ATA/ATAPI HW being present ? */ 468 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 469 DELAY(10); 470 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 471 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 472 stat0 = ATA_S_BUSY; 473 mask |= 0x01; 474 } 475 476 /* in some setups we dont want to test for a slave */ 477 if (!(ch->flags & ATA_NO_SLAVE)) { 478 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_SLAVE)); 479 DELAY(10); 480 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 481 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 482 stat1 = ATA_S_BUSY; 483 mask |= 0x02; 484 } 485 } 486 487 if (bootverbose) 488 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 489 mask, ostat0, ostat1); 490 491 /* if nothing showed up there is no need to get any further */ 492 /* XXX SOS is that too strong?, we just might loose devices here */ 493 ch->devices = 0; 494 if (!mask) 495 return; 496 497 /* reset (both) devices on this channel */ 498 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 499 DELAY(10); 500 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 501 ata_udelay(10000); 502 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 503 ata_udelay(100000); 504 ATA_IDX_INB(ch, ATA_ERROR); 505 506 /* wait for BUSY to go inactive */ 507 for (timeout = 0; timeout < 310; timeout++) { 508 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) { 509 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_MASTER)); 510 DELAY(10); 511 err = ATA_IDX_INB(ch, ATA_ERROR); 512 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 513 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 514 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 515 if (bootverbose) 516 device_printf(dev, 517 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 518 stat0, err, lsb, msb); 519 if (stat0 == err && lsb == err && msb == err && 520 timeout > (stat0 & ATA_S_BUSY ? 100 : 10)) 521 mask &= ~0x01; 522 if (!(stat0 & ATA_S_BUSY)) { 523 if ((err & 0x7f) == ATA_E_ILI) { 524 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 525 ch->devices |= ATA_ATAPI_MASTER; 526 } 527 else if (stat0 & ATA_S_READY) { 528 ch->devices |= ATA_ATA_MASTER; 529 } 530 } 531 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 532 stat0 |= ATA_S_BUSY; 533 } 534 } 535 } 536 537 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) && 538 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) { 539 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_SLAVE)); 540 DELAY(10); 541 err = ATA_IDX_INB(ch, ATA_ERROR); 542 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 543 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 544 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 545 if (bootverbose) 546 device_printf(dev, 547 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 548 stat1, err, lsb, msb); 549 if (stat1 == err && lsb == err && msb == err && 550 timeout > (stat1 & ATA_S_BUSY ? 100 : 10)) 551 mask &= ~0x02; 552 if (!(stat1 & ATA_S_BUSY)) { 553 if ((err & 0x7f) == ATA_E_ILI) { 554 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 555 ch->devices |= ATA_ATAPI_SLAVE; 556 } 557 else if (stat1 & ATA_S_READY) { 558 ch->devices |= ATA_ATA_SLAVE; 559 } 560 } 561 else if ((stat1 & 0x0f) && err == lsb && err == msb) { 562 stat1 |= ATA_S_BUSY; 563 } 564 } 565 } 566 567 if (mask == 0x00) /* nothing to wait for */ 568 break; 569 if (mask == 0x01) /* wait for master only */ 570 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10)) 571 break; 572 if (mask == 0x02) /* wait for slave only */ 573 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10)) 574 break; 575 if (mask == 0x03) { /* wait for both master & slave */ 576 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 577 break; 578 if ((stat0 == 0xff) && (timeout > 20)) 579 mask &= ~0x01; 580 if ((stat1 == 0xff) && (timeout > 20)) 581 mask &= ~0x02; 582 } 583 ata_udelay(100000); 584 } 585 586 if (bootverbose) 587 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%x\n", 588 stat0, stat1, ch->devices); 589 } 590 591 /* must be called with ATA channel locked and state_mtx held */ 592 int 593 ata_generic_status(device_t dev) 594 { 595 struct ata_channel *ch = device_get_softc(dev); 596 597 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 598 DELAY(100); 599 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 600 return 0; 601 } 602 return 1; 603 } 604 605 static int 606 ata_wait(struct ata_channel *ch, struct ata_device *atadev, u_int8_t mask) 607 { 608 u_int8_t status; 609 int timeout = 0; 610 611 DELAY(1); 612 613 /* wait at max 1 second for device to get !BUSY */ 614 while (timeout < 1000000) { 615 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 616 617 /* if drive fails status, reselect the drive and try again */ 618 if (status == 0xff) { 619 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit)); 620 timeout += 1000; 621 DELAY(1000); 622 continue; 623 } 624 625 /* are we done ? */ 626 if (!(status & ATA_S_BUSY)) 627 break; 628 629 if (timeout > 1000) { 630 timeout += 1000; 631 DELAY(1000); 632 } 633 else { 634 timeout += 10; 635 DELAY(10); 636 } 637 } 638 if (timeout >= 1000000) 639 return -2; 640 if (!mask) 641 return (status & ATA_S_ERROR); 642 643 DELAY(1); 644 645 /* wait 50 msec for bits wanted */ 646 timeout = 5000; 647 while (timeout--) { 648 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 649 if ((status & mask) == mask) 650 return (status & ATA_S_ERROR); 651 DELAY(10); 652 } 653 return -3; 654 } 655 656 int 657 ata_generic_command(struct ata_request *request) 658 { 659 struct ata_channel *ch = device_get_softc(request->parent); 660 struct ata_device *atadev = device_get_softc(request->dev); 661 662 /* select device */ 663 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(atadev->unit)); 664 665 /* ready to issue command ? */ 666 if (ata_wait(ch, atadev, 0) < 0) { 667 device_printf(request->dev, "timeout waiting to issue command\n"); 668 return -1; 669 } 670 671 /* enable interrupt */ 672 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 673 674 if (request->flags & ATA_R_ATAPI) { 675 int timeout = 5000; 676 677 /* issue packet command to controller */ 678 if (request->flags & ATA_R_DMA) { 679 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA); 680 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0); 681 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0); 682 } 683 else { 684 ATA_IDX_OUTB(ch, ATA_FEATURE, 0); 685 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize); 686 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8); 687 } 688 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD); 689 690 /* command interrupt device ? just return and wait for interrupt */ 691 if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR) 692 return 0; 693 694 /* wait for ready to write ATAPI command block */ 695 while (timeout--) { 696 int reason = ATA_IDX_INB(ch, ATA_IREASON); 697 int status = ATA_IDX_INB(ch, ATA_STATUS); 698 699 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 700 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 701 break; 702 DELAY(20); 703 } 704 if (timeout <= 0) { 705 device_printf(request->dev, "timeout waiting for ATAPI ready\n"); 706 request->result = EIO; 707 return -1; 708 } 709 710 /* this seems to be needed for some (slow) devices */ 711 DELAY(10); 712 713 /* output command block */ 714 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 715 (atadev->param.config & ATA_PROTO_MASK) == 716 ATA_PROTO_ATAPI_12 ? 6 : 8); 717 } 718 else { 719 ch->hw.tf_write(request); 720 721 /* issue command to controller */ 722 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 723 } 724 return 0; 725 } 726 727 static void 728 ata_tf_read(struct ata_request *request) 729 { 730 struct ata_channel *ch = device_get_softc(request->parent); 731 struct ata_device *atadev = device_get_softc(request->dev); 732 733 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 734 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB); 735 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8); 736 request->u.ata.lba = 737 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) | 738 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) | 739 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40); 740 741 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 742 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT); 743 request->u.ata.lba |= 744 (ATA_IDX_INB(ch, ATA_SECTOR) | 745 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 746 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16)); 747 } 748 else { 749 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 750 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 751 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 752 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 753 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24); 754 } 755 } 756 757 static void 758 ata_tf_write(struct ata_request *request) 759 { 760 struct ata_channel *ch = device_get_softc(request->parent); 761 struct ata_device *atadev = device_get_softc(request->dev); 762 763 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 764 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8); 765 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 766 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8); 767 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 768 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24); 769 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 770 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32); 771 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 772 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40); 773 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 774 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(atadev->unit)); 775 } 776 else { 777 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 778 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 779 if (atadev->flags & ATA_D_USE_CHS) { 780 int heads, sectors; 781 782 if (atadev->param.atavalid & ATA_FLAG_54_58) { 783 heads = atadev->param.current_heads; 784 sectors = atadev->param.current_sectors; 785 } 786 else { 787 heads = atadev->param.heads; 788 sectors = atadev->param.sectors; 789 } 790 791 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 792 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 793 (request->u.ata.lba / (sectors * heads))); 794 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 795 (request->u.ata.lba / (sectors * heads)) >> 8); 796 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit) | 797 (((request->u.ata.lba% (sectors * heads)) / 798 sectors) & 0xf)); 799 } 800 else { 801 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 802 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 803 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 804 ATA_IDX_OUTB(ch, ATA_DRIVE, 805 ATA_D_IBM | ATA_D_LBA | ATA_DEV(atadev->unit) | 806 ((request->u.ata.lba >> 24) & 0x0f)); 807 } 808 } 809 } 810 811 static void 812 ata_pio_read(struct ata_request *request, int length) 813 { 814 struct ata_channel *ch = device_get_softc(request->parent); 815 int size = min(request->transfersize, length); 816 int resid; 817 818 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 819 ATA_IDX_INSW_STRM(ch, ATA_DATA, 820 (void*)((uintptr_t)request->data+request->donecount), 821 size / sizeof(int16_t)); 822 else 823 ATA_IDX_INSL_STRM(ch, ATA_DATA, 824 (void*)((uintptr_t)request->data+request->donecount), 825 size / sizeof(int32_t)); 826 827 if (request->transfersize < length) { 828 device_printf(request->dev, "WARNING - %s read data overrun %d>%d\n", 829 ata_cmd2str(request), length, request->transfersize); 830 for (resid = request->transfersize; resid < length; 831 resid += sizeof(int16_t)) 832 ATA_IDX_INW(ch, ATA_DATA); 833 } 834 } 835 836 static void 837 ata_pio_write(struct ata_request *request, int length) 838 { 839 struct ata_channel *ch = device_get_softc(request->parent); 840 int size = min(request->transfersize, length); 841 int resid; 842 843 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 844 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 845 (void*)((uintptr_t)request->data+request->donecount), 846 size / sizeof(int16_t)); 847 else 848 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 849 (void*)((uintptr_t)request->data+request->donecount), 850 size / sizeof(int32_t)); 851 852 if (request->transfersize < length) { 853 device_printf(request->dev, "WARNING - %s write data underrun %d>%d\n", 854 ata_cmd2str(request), length, request->transfersize); 855 for (resid = request->transfersize; resid < length; 856 resid += sizeof(int16_t)) 857 ATA_IDX_OUTW(ch, ATA_DATA, 0); 858 } 859 } 860