1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/endian.h> 35 #include <sys/ata.h> 36 #include <sys/conf.h> 37 #include <sys/ctype.h> 38 #include <sys/bus.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/ata/ata-all.h> 45 #include <dev/ata/ata-pci.h> 46 #include <ata_if.h> 47 48 /* prototypes */ 49 static int ata_generic_status(device_t dev); 50 static int ata_wait(struct ata_channel *ch, int unit, u_int8_t); 51 static void ata_pio_read(struct ata_request *, int); 52 static void ata_pio_write(struct ata_request *, int); 53 static void ata_tf_read(struct ata_request *); 54 static void ata_tf_write(struct ata_request *); 55 56 /* 57 * low level ATA functions 58 */ 59 void 60 ata_generic_hw(device_t dev) 61 { 62 struct ata_channel *ch = device_get_softc(dev); 63 64 ch->hw.begin_transaction = ata_begin_transaction; 65 ch->hw.end_transaction = ata_end_transaction; 66 ch->hw.status = ata_generic_status; 67 ch->hw.softreset = NULL; 68 ch->hw.command = ata_generic_command; 69 ch->hw.tf_read = ata_tf_read; 70 ch->hw.tf_write = ata_tf_write; 71 ch->hw.pm_read = NULL; 72 ch->hw.pm_write = NULL; 73 } 74 75 /* must be called with ATA channel locked and state_mtx held */ 76 int 77 ata_begin_transaction(struct ata_request *request) 78 { 79 struct ata_channel *ch = device_get_softc(request->parent); 80 int dummy, error; 81 82 ATA_DEBUG_RQ(request, "begin transaction"); 83 84 /* disable ATAPI DMA writes if HW doesn't support it */ 85 if ((ch->flags & ATA_ATAPI_DMA_RO) && 86 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 87 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 88 request->flags &= ~ATA_R_DMA; 89 90 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 91 92 /* ATA PIO data transfer and control commands */ 93 default: 94 { 95 /* record command direction here as our request might be gone later */ 96 int write = (request->flags & ATA_R_WRITE); 97 98 /* issue command */ 99 if (ch->hw.command(request)) { 100 device_printf(request->parent, "error issuing %s command\n", 101 ata_cmd2str(request)); 102 request->result = EIO; 103 goto begin_finished; 104 } 105 106 /* device reset doesn't interrupt */ 107 if (request->u.ata.command == ATA_DEVICE_RESET) { 108 109 int timeout = 1000000; 110 do { 111 DELAY(10); 112 request->status = ATA_IDX_INB(ch, ATA_STATUS); 113 } while (request->status & ATA_S_BUSY && timeout--); 114 if (request->status & ATA_S_ERROR) 115 request->error = ATA_IDX_INB(ch, ATA_ERROR); 116 goto begin_finished; 117 } 118 119 /* if write command output the data */ 120 if (write) { 121 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) { 122 device_printf(request->parent, 123 "timeout waiting for write DRQ\n"); 124 request->result = EIO; 125 goto begin_finished; 126 } 127 ata_pio_write(request, request->transfersize); 128 } 129 } 130 goto begin_continue; 131 132 /* ATA DMA data transfer commands */ 133 case ATA_R_DMA: 134 /* check sanity, setup SG list and DMA engine */ 135 if ((error = ch->dma.load(request, NULL, &dummy))) { 136 device_printf(request->parent, "setting up DMA failed\n"); 137 request->result = error; 138 goto begin_finished; 139 } 140 141 /* issue command */ 142 if (ch->hw.command(request)) { 143 device_printf(request->parent, "error issuing %s command\n", 144 ata_cmd2str(request)); 145 request->result = EIO; 146 goto begin_finished; 147 } 148 149 /* start DMA engine */ 150 if (ch->dma.start && ch->dma.start(request)) { 151 device_printf(request->parent, "error starting DMA\n"); 152 request->result = EIO; 153 goto begin_finished; 154 } 155 goto begin_continue; 156 157 /* ATAPI PIO commands */ 158 case ATA_R_ATAPI: 159 /* is this just a POLL DSC command ? */ 160 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 161 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit)); 162 DELAY(10); 163 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 164 request->result = EBUSY; 165 goto begin_finished; 166 } 167 168 /* start ATAPI operation */ 169 if (ch->hw.command(request)) { 170 device_printf(request->parent, "error issuing ATA PACKET command\n"); 171 request->result = EIO; 172 goto begin_finished; 173 } 174 goto begin_continue; 175 176 /* ATAPI DMA commands */ 177 case ATA_R_ATAPI|ATA_R_DMA: 178 /* is this just a POLL DSC command ? */ 179 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 180 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit)); 181 DELAY(10); 182 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 183 request->result = EBUSY; 184 goto begin_finished; 185 } 186 187 /* check sanity, setup SG list and DMA engine */ 188 if ((error = ch->dma.load(request, NULL, &dummy))) { 189 device_printf(request->parent, "setting up DMA failed\n"); 190 request->result = error; 191 goto begin_finished; 192 } 193 194 /* start ATAPI operation */ 195 if (ch->hw.command(request)) { 196 device_printf(request->parent, "error issuing ATA PACKET command\n"); 197 request->result = EIO; 198 goto begin_finished; 199 } 200 201 /* start DMA engine */ 202 if (ch->dma.start && ch->dma.start(request)) { 203 request->result = EIO; 204 goto begin_finished; 205 } 206 goto begin_continue; 207 } 208 /* NOT REACHED */ 209 printf("ata_begin_transaction OOPS!!!\n"); 210 211 begin_finished: 212 if (ch->dma.unload) { 213 ch->dma.unload(request); 214 } 215 return ATA_OP_FINISHED; 216 217 begin_continue: 218 callout_reset(&request->callout, request->timeout * hz, 219 (timeout_t*)ata_timeout, request); 220 return ATA_OP_CONTINUES; 221 } 222 223 /* must be called with ATA channel locked and state_mtx held */ 224 int 225 ata_end_transaction(struct ata_request *request) 226 { 227 struct ata_channel *ch = device_get_softc(request->parent); 228 int length; 229 230 ATA_DEBUG_RQ(request, "end transaction"); 231 232 /* clear interrupt and get status */ 233 request->status = ATA_IDX_INB(ch, ATA_STATUS); 234 235 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 236 237 /* ATA PIO data transfer and control commands */ 238 default: 239 240 /* on timeouts we have no data or anything so just return */ 241 if (request->flags & ATA_R_TIMEOUT) 242 goto end_finished; 243 244 /* on control commands read back registers to the request struct */ 245 if (request->flags & ATA_R_CONTROL) { 246 ch->hw.tf_read(request); 247 } 248 249 /* if we got an error we are done with the HW */ 250 if (request->status & ATA_S_ERROR) { 251 request->error = ATA_IDX_INB(ch, ATA_ERROR); 252 goto end_finished; 253 } 254 255 /* are we moving data ? */ 256 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 257 258 /* if read data get it */ 259 if (request->flags & ATA_R_READ) { 260 int flags = ATA_S_DRQ; 261 262 if (request->u.ata.command != ATA_ATAPI_IDENTIFY) 263 flags |= ATA_S_READY; 264 if (ata_wait(ch, request->unit, flags) < 0) { 265 device_printf(request->parent, 266 "timeout waiting for read DRQ\n"); 267 request->result = EIO; 268 goto end_finished; 269 } 270 ata_pio_read(request, request->transfersize); 271 } 272 273 /* update how far we've gotten */ 274 request->donecount += request->transfersize; 275 276 /* do we need a scoop more ? */ 277 if (request->bytecount > request->donecount) { 278 279 /* set this transfer size according to HW capabilities */ 280 request->transfersize = 281 min((request->bytecount - request->donecount), 282 request->transfersize); 283 284 /* if data write command, output the data */ 285 if (request->flags & ATA_R_WRITE) { 286 287 /* if we get an error here we are done with the HW */ 288 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) { 289 device_printf(request->parent, 290 "timeout waiting for write DRQ\n"); 291 request->status = ATA_IDX_INB(ch, ATA_STATUS); 292 goto end_finished; 293 } 294 295 /* output data and return waiting for new interrupt */ 296 ata_pio_write(request, request->transfersize); 297 goto end_continue; 298 } 299 300 /* if data read command, return & wait for interrupt */ 301 if (request->flags & ATA_R_READ) 302 goto end_continue; 303 } 304 } 305 /* done with HW */ 306 goto end_finished; 307 308 /* ATA DMA data transfer commands */ 309 case ATA_R_DMA: 310 311 /* stop DMA engine and get status */ 312 if (ch->dma.stop) 313 request->dma->status = ch->dma.stop(request); 314 315 /* did we get error or data */ 316 if (request->status & ATA_S_ERROR) 317 request->error = ATA_IDX_INB(ch, ATA_ERROR); 318 else if (request->dma->status & ATA_BMSTAT_ERROR) 319 request->status |= ATA_S_ERROR; 320 else if (!(request->flags & ATA_R_TIMEOUT)) 321 request->donecount = request->bytecount; 322 323 /* release SG list etc */ 324 ch->dma.unload(request); 325 326 /* done with HW */ 327 goto end_finished; 328 329 /* ATAPI PIO commands */ 330 case ATA_R_ATAPI: 331 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 332 333 /* on timeouts we have no data or anything so just return */ 334 if (request->flags & ATA_R_TIMEOUT) 335 goto end_finished; 336 337 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 338 (request->status & ATA_S_DRQ)) { 339 340 case ATAPI_P_CMDOUT: 341 /* this seems to be needed for some (slow) devices */ 342 DELAY(10); 343 344 if (!(request->status & ATA_S_DRQ)) { 345 device_printf(request->parent, "command interrupt without DRQ\n"); 346 request->status = ATA_S_ERROR; 347 goto end_finished; 348 } 349 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 350 (request->flags & ATA_R_ATAPI16) ? 8 : 6); 351 /* return wait for interrupt */ 352 goto end_continue; 353 354 case ATAPI_P_WRITE: 355 if (request->flags & ATA_R_READ) { 356 request->status = ATA_S_ERROR; 357 device_printf(request->parent, 358 "%s trying to write on read buffer\n", 359 ata_cmd2str(request)); 360 goto end_finished; 361 break; 362 } 363 ata_pio_write(request, length); 364 request->donecount += length; 365 366 /* set next transfer size according to HW capabilities */ 367 request->transfersize = min((request->bytecount-request->donecount), 368 request->transfersize); 369 /* return wait for interrupt */ 370 goto end_continue; 371 372 case ATAPI_P_READ: 373 if (request->flags & ATA_R_WRITE) { 374 request->status = ATA_S_ERROR; 375 device_printf(request->parent, 376 "%s trying to read on write buffer\n", 377 ata_cmd2str(request)); 378 goto end_finished; 379 } 380 ata_pio_read(request, length); 381 request->donecount += length; 382 383 /* set next transfer size according to HW capabilities */ 384 request->transfersize = min((request->bytecount-request->donecount), 385 request->transfersize); 386 /* return wait for interrupt */ 387 goto end_continue; 388 389 case ATAPI_P_DONEDRQ: 390 device_printf(request->parent, 391 "WARNING - %s DONEDRQ non conformant device\n", 392 ata_cmd2str(request)); 393 if (request->flags & ATA_R_READ) { 394 ata_pio_read(request, length); 395 request->donecount += length; 396 } 397 else if (request->flags & ATA_R_WRITE) { 398 ata_pio_write(request, length); 399 request->donecount += length; 400 } 401 else 402 request->status = ATA_S_ERROR; 403 /* FALLTHROUGH */ 404 405 case ATAPI_P_ABORT: 406 case ATAPI_P_DONE: 407 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 408 request->error = ATA_IDX_INB(ch, ATA_ERROR); 409 goto end_finished; 410 411 default: 412 device_printf(request->parent, "unknown transfer phase\n"); 413 request->status = ATA_S_ERROR; 414 } 415 416 /* done with HW */ 417 goto end_finished; 418 419 /* ATAPI DMA commands */ 420 case ATA_R_ATAPI|ATA_R_DMA: 421 422 /* stop DMA engine and get status */ 423 if (ch->dma.stop) 424 request->dma->status = ch->dma.stop(request); 425 426 /* did we get error or data */ 427 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 428 request->error = ATA_IDX_INB(ch, ATA_ERROR); 429 else if (request->dma->status & ATA_BMSTAT_ERROR) 430 request->status |= ATA_S_ERROR; 431 else if (!(request->flags & ATA_R_TIMEOUT)) 432 request->donecount = request->bytecount; 433 434 /* release SG list etc */ 435 ch->dma.unload(request); 436 437 /* done with HW */ 438 goto end_finished; 439 } 440 /* NOT REACHED */ 441 printf("ata_end_transaction OOPS!!\n"); 442 443 end_finished: 444 callout_stop(&request->callout); 445 return ATA_OP_FINISHED; 446 447 end_continue: 448 return ATA_OP_CONTINUES; 449 } 450 451 /* must be called with ATA channel locked and state_mtx held */ 452 void 453 ata_generic_reset(device_t dev) 454 { 455 struct ata_channel *ch = device_get_softc(dev); 456 457 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0; 458 u_int8_t err = 0, lsb = 0, msb = 0; 459 int mask = 0, timeout; 460 461 /* do we have any signs of ATA/ATAPI HW being present ? */ 462 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 463 DELAY(10); 464 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 465 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 466 stat0 = ATA_S_BUSY; 467 mask |= 0x01; 468 } 469 470 /* in some setups we dont want to test for a slave */ 471 if (!(ch->flags & ATA_NO_SLAVE)) { 472 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_SLAVE)); 473 DELAY(10); 474 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 475 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 476 stat1 = ATA_S_BUSY; 477 mask |= 0x02; 478 } 479 } 480 481 if (bootverbose) 482 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 483 mask, ostat0, ostat1); 484 485 /* if nothing showed up there is no need to get any further */ 486 /* XXX SOS is that too strong?, we just might loose devices here */ 487 ch->devices = 0; 488 if (!mask) 489 return; 490 491 /* reset (both) devices on this channel */ 492 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 493 DELAY(10); 494 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 495 ata_udelay(10000); 496 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 497 ata_udelay(100000); 498 ATA_IDX_INB(ch, ATA_ERROR); 499 500 /* wait for BUSY to go inactive */ 501 for (timeout = 0; timeout < 310; timeout++) { 502 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) { 503 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_MASTER)); 504 DELAY(10); 505 err = ATA_IDX_INB(ch, ATA_ERROR); 506 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 507 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 508 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 509 if (bootverbose) 510 device_printf(dev, 511 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 512 stat0, err, lsb, msb); 513 if (stat0 == err && lsb == err && msb == err && 514 timeout > (stat0 & ATA_S_BUSY ? 100 : 10)) 515 mask &= ~0x01; 516 if (!(stat0 & ATA_S_BUSY)) { 517 if ((err & 0x7f) == ATA_E_ILI) { 518 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 519 ch->devices |= ATA_ATAPI_MASTER; 520 } 521 else if (stat0 & ATA_S_READY) { 522 ch->devices |= ATA_ATA_MASTER; 523 } 524 } 525 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 526 stat0 |= ATA_S_BUSY; 527 } 528 } 529 } 530 531 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) && 532 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) { 533 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_SLAVE)); 534 DELAY(10); 535 err = ATA_IDX_INB(ch, ATA_ERROR); 536 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 537 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 538 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 539 if (bootverbose) 540 device_printf(dev, 541 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 542 stat1, err, lsb, msb); 543 if (stat1 == err && lsb == err && msb == err && 544 timeout > (stat1 & ATA_S_BUSY ? 100 : 10)) 545 mask &= ~0x02; 546 if (!(stat1 & ATA_S_BUSY)) { 547 if ((err & 0x7f) == ATA_E_ILI) { 548 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 549 ch->devices |= ATA_ATAPI_SLAVE; 550 } 551 else if (stat1 & ATA_S_READY) { 552 ch->devices |= ATA_ATA_SLAVE; 553 } 554 } 555 else if ((stat1 & 0x0f) && err == lsb && err == msb) { 556 stat1 |= ATA_S_BUSY; 557 } 558 } 559 } 560 561 if (mask == 0x00) /* nothing to wait for */ 562 break; 563 if (mask == 0x01) /* wait for master only */ 564 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10)) 565 break; 566 if (mask == 0x02) /* wait for slave only */ 567 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10)) 568 break; 569 if (mask == 0x03) { /* wait for both master & slave */ 570 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 571 break; 572 if ((stat0 == 0xff) && (timeout > 20)) 573 mask &= ~0x01; 574 if ((stat1 == 0xff) && (timeout > 20)) 575 mask &= ~0x02; 576 } 577 ata_udelay(100000); 578 } 579 580 if (bootverbose) 581 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%x\n", 582 stat0, stat1, ch->devices); 583 } 584 585 /* must be called with ATA channel locked and state_mtx held */ 586 int 587 ata_generic_status(device_t dev) 588 { 589 struct ata_channel *ch = device_get_softc(dev); 590 591 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 592 DELAY(100); 593 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 594 return 0; 595 } 596 return 1; 597 } 598 599 static int 600 ata_wait(struct ata_channel *ch, int unit, u_int8_t mask) 601 { 602 u_int8_t status; 603 int timeout = 0; 604 605 DELAY(1); 606 607 /* wait at max 1 second for device to get !BUSY */ 608 while (timeout < 1000000) { 609 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 610 611 /* if drive fails status, reselect the drive and try again */ 612 if (status == 0xff) { 613 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(unit)); 614 timeout += 1000; 615 DELAY(1000); 616 continue; 617 } 618 619 /* are we done ? */ 620 if (!(status & ATA_S_BUSY)) 621 break; 622 623 if (timeout > 1000) { 624 timeout += 1000; 625 DELAY(1000); 626 } 627 else { 628 timeout += 10; 629 DELAY(10); 630 } 631 } 632 if (timeout >= 1000000) 633 return -2; 634 if (!mask) 635 return (status & ATA_S_ERROR); 636 637 DELAY(1); 638 639 /* wait 50 msec for bits wanted */ 640 timeout = 5000; 641 while (timeout--) { 642 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 643 if ((status & mask) == mask) 644 return (status & ATA_S_ERROR); 645 DELAY(10); 646 } 647 return -3; 648 } 649 650 int 651 ata_generic_command(struct ata_request *request) 652 { 653 struct ata_channel *ch = device_get_softc(request->parent); 654 655 /* select device */ 656 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit)); 657 658 /* ready to issue command ? */ 659 if (ata_wait(ch, request->unit, 0) < 0) { 660 device_printf(request->parent, "timeout waiting to issue command\n"); 661 return -1; 662 } 663 664 /* enable interrupt */ 665 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 666 667 if (request->flags & ATA_R_ATAPI) { 668 int timeout = 5000; 669 int res; 670 671 /* issue packet command to controller */ 672 if (request->flags & ATA_R_DMA) { 673 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA); 674 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0); 675 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0); 676 } 677 else { 678 ATA_IDX_OUTB(ch, ATA_FEATURE, 0); 679 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize); 680 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8); 681 } 682 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD); 683 684 /* command interrupt device ? just return and wait for interrupt */ 685 if (request->flags & ATA_R_ATAPI_INTR) 686 return 0; 687 688 /* command processed ? */ 689 res = ata_wait(ch, request->unit, 0); 690 if (res != 0) { 691 if (res < 0) 692 device_printf(request->parent, "timeout waiting for PACKET command\n"); 693 return (-1); 694 } 695 /* wait for ready to write ATAPI command block */ 696 while (timeout--) { 697 int reason = ATA_IDX_INB(ch, ATA_IREASON); 698 int status = ATA_IDX_INB(ch, ATA_STATUS); 699 700 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 701 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 702 break; 703 DELAY(20); 704 } 705 if (timeout <= 0) { 706 device_printf(request->parent, "timeout waiting for ATAPI ready\n"); 707 request->result = EIO; 708 return -1; 709 } 710 711 /* this seems to be needed for some (slow) devices */ 712 DELAY(10); 713 714 /* output command block */ 715 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 716 (request->flags & ATA_R_ATAPI16) ? 8 : 6); 717 } 718 else { 719 ch->hw.tf_write(request); 720 721 /* issue command to controller */ 722 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 723 } 724 return 0; 725 } 726 727 static void 728 ata_tf_read(struct ata_request *request) 729 { 730 struct ata_channel *ch = device_get_softc(request->parent); 731 732 if (request->flags & ATA_R_48BIT) { 733 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB); 734 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8); 735 request->u.ata.lba = 736 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) | 737 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) | 738 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40); 739 740 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 741 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT); 742 request->u.ata.lba |= 743 (ATA_IDX_INB(ch, ATA_SECTOR) | 744 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 745 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16)); 746 } 747 else { 748 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 749 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 750 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 751 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 752 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24); 753 } 754 } 755 756 static void 757 ata_tf_write(struct ata_request *request) 758 { 759 struct ata_channel *ch = device_get_softc(request->parent); 760 struct ata_device *atadev = device_get_softc(request->dev); 761 762 if (request->flags & ATA_R_48BIT) { 763 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8); 764 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 765 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8); 766 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 767 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24); 768 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 769 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32); 770 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 771 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40); 772 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 773 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 774 } 775 else { 776 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 777 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 778 if (atadev->flags & ATA_D_USE_CHS) { 779 int heads, sectors; 780 781 if (atadev->param.atavalid & ATA_FLAG_54_58) { 782 heads = atadev->param.current_heads; 783 sectors = atadev->param.current_sectors; 784 } 785 else { 786 heads = atadev->param.heads; 787 sectors = atadev->param.sectors; 788 } 789 790 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 791 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 792 (request->u.ata.lba / (sectors * heads))); 793 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 794 (request->u.ata.lba / (sectors * heads)) >> 8); 795 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 796 (((request->u.ata.lba% (sectors * heads)) / 797 sectors) & 0xf)); 798 } 799 else { 800 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 801 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 802 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 803 ATA_IDX_OUTB(ch, ATA_DRIVE, 804 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 805 ((request->u.ata.lba >> 24) & 0x0f)); 806 } 807 } 808 } 809 810 static void 811 ata_pio_read(struct ata_request *request, int length) 812 { 813 struct ata_channel *ch = device_get_softc(request->parent); 814 int size = min(request->transfersize, length); 815 int resid; 816 817 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 818 ATA_IDX_INSW_STRM(ch, ATA_DATA, 819 (void*)((uintptr_t)request->data+request->donecount), 820 size / sizeof(int16_t)); 821 else 822 ATA_IDX_INSL_STRM(ch, ATA_DATA, 823 (void*)((uintptr_t)request->data+request->donecount), 824 size / sizeof(int32_t)); 825 826 if (request->transfersize < length) { 827 device_printf(request->parent, "WARNING - %s read data overrun %d>%d\n", 828 ata_cmd2str(request), length, request->transfersize); 829 for (resid = request->transfersize; resid < length; 830 resid += sizeof(int16_t)) 831 ATA_IDX_INW(ch, ATA_DATA); 832 } 833 } 834 835 static void 836 ata_pio_write(struct ata_request *request, int length) 837 { 838 struct ata_channel *ch = device_get_softc(request->parent); 839 int size = min(request->transfersize, length); 840 int resid; 841 842 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 843 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 844 (void*)((uintptr_t)request->data+request->donecount), 845 size / sizeof(int16_t)); 846 else 847 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 848 (void*)((uintptr_t)request->data+request->donecount), 849 size / sizeof(int32_t)); 850 851 if (request->transfersize < length) { 852 device_printf(request->parent, "WARNING - %s write data underrun %d>%d\n", 853 ata_cmd2str(request), length, request->transfersize); 854 for (resid = request->transfersize; resid < length; 855 resid += sizeof(int16_t)) 856 ATA_IDX_OUTW(ch, ATA_DATA, 0); 857 } 858 } 859