1 /*- 2 * Copyright (c) 1998 - 2004 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_ata.h" 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/ata.h> 36 #include <sys/kernel.h> 37 #include <sys/conf.h> 38 #include <sys/bus.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/ata/ata-all.h> 45 46 /* prototypes */ 47 static int ata_generic_transaction(struct ata_request *); 48 static void ata_generic_interrupt(void *); 49 static void ata_generic_reset(struct ata_channel *); 50 static int ata_wait(struct ata_device *, u_int8_t); 51 /*static int ata_command(struct ata_device *, u_int8_t, u_int64_t, u_int16_t, u_int16_t);*/ 52 static void ata_pio_read(struct ata_request *, int); 53 static void ata_pio_write(struct ata_request *, int); 54 55 /* local vars */ 56 static int atadebug = 0; 57 58 /* 59 * low level ATA functions 60 */ 61 void 62 ata_generic_hw(struct ata_channel *ch) 63 { 64 ch->hw.reset = ata_generic_reset; 65 ch->hw.transaction = ata_generic_transaction; 66 ch->hw.interrupt = ata_generic_interrupt; 67 ch->hw.command = ata_generic_command; 68 } 69 70 /* must be called with ATA channel locked */ 71 static int 72 ata_generic_transaction(struct ata_request *request) 73 { 74 struct ata_channel *ch = request->device->channel; 75 76 /* safetybelt for HW that went away */ 77 if (!request->device->param || request->device->channel->flags&ATA_HWGONE) { 78 request->retries = 0; 79 request->result = ENXIO; 80 return ATA_OP_FINISHED; 81 } 82 83 /* record the request as running */ 84 ch->running = request; 85 86 ATA_DEBUG_RQ(request, "transaction"); 87 88 /* disable ATAPI DMA writes if HW doesn't support it */ 89 if ((ch->flags & ATA_ATAPI_DMA_RO) && 90 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 91 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 92 request->flags &= ~ATA_R_DMA; 93 94 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 95 96 /* ATA PIO data transfer and control commands */ 97 default: 98 { 99 /* record command direction here as our request might be gone later */ 100 int write = (request->flags & ATA_R_WRITE); 101 102 /* issue command */ 103 if (ch->hw.command(request->device, request->u.ata.command, 104 request->u.ata.lba, request->u.ata.count, 105 request->u.ata.feature)) { 106 ata_prtdev(request->device, "error issueing PIO command\n"); 107 request->result = EIO; 108 break; 109 } 110 111 /* device reset doesn't interrupt */ 112 if (request->u.ata.command == ATA_ATAPI_RESET) { 113 int timeout = 1000000; 114 do { 115 DELAY(10); 116 request->status = ATA_IDX_INB(ch, ATA_STATUS); 117 } while (request->status & ATA_S_BUSY && timeout--); 118 if (timeout) 119 printf("ATAPI_RESET time = %dus\n", (1000000-timeout)*10); 120 else 121 printf("ATAPI_RESET timeout\n"); 122 123 if (request->status & ATA_S_ERROR) { 124 request->error = ATA_IDX_INB(ch, ATA_ERROR); 125 //request->result = EIO; 126 } 127 break; 128 } 129 130 /* if write command output the data */ 131 if (write) { 132 if (ata_wait(request->device, 133 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 134 ata_prtdev(request->device,"timeout waiting for write DRQ"); 135 request->result = EIO; 136 break; 137 } 138 ata_pio_write(request, request->transfersize); 139 } 140 } 141 142 /* return and wait for interrupt */ 143 return ATA_OP_CONTINUES; 144 145 /* ATA DMA data transfer commands */ 146 case ATA_R_DMA: 147 /* check sanity, setup SG list and DMA engine */ 148 if (ch->dma->load(request->device, request->data, request->bytecount, 149 request->flags & ATA_R_READ)) { 150 ata_prtdev(request->device, "setting up DMA failed\n"); 151 request->result = EIO; 152 break; 153 } 154 155 /* issue command */ 156 if (ch->hw.command(request->device, request->u.ata.command, 157 request->u.ata.lba, request->u.ata.count, 158 request->u.ata.feature)) { 159 ata_prtdev(request->device, "error issuing DMA command\n"); 160 request->result = EIO; 161 break; 162 } 163 164 /* start DMA engine */ 165 if (ch->dma->start(ch)) { 166 ata_prtdev(request->device, "error starting DMA\n"); 167 request->result = EIO; 168 break; 169 } 170 171 /* return and wait for interrupt */ 172 return ATA_OP_CONTINUES; 173 174 /* ATAPI PIO commands */ 175 case ATA_R_ATAPI: 176 /* is this just a POLL DSC command ? */ 177 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 178 ATA_IDX_OUTB(ch, ATA_DRIVE, 179 ATA_D_IBM | request->device->unit); 180 DELAY(10); 181 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC)) 182 request->result = EBUSY; 183 break; 184 } 185 186 /* start ATAPI operation */ 187 if (ch->hw.command(request->device, ATA_PACKET_CMD, 188 request->transfersize << 8, 0, 0)) { 189 ata_prtdev(request->device, "error issuing ATA PACKET command\n"); 190 request->result = EIO; 191 break; 192 } 193 194 /* command interrupt device ? just return and wait for interrupt */ 195 if ((request->device->param->config & ATA_DRQ_MASK) == ATA_DRQ_INTR) 196 return ATA_OP_CONTINUES; 197 198 /* wait for ready to write ATAPI command block */ 199 { 200 int timeout = 5000; /* might be less for fast devices */ 201 while (timeout--) { 202 int reason = ATA_IDX_INB(ch, ATA_IREASON); 203 int status = ATA_IDX_INB(ch, ATA_STATUS); 204 205 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 206 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 207 break; 208 DELAY(20); 209 } 210 if (timeout <= 0) { 211 ata_prtdev(request->device, 212 "timeout waiting for ATAPI ready\n"); 213 request->result = EIO; 214 break; 215 } 216 } 217 218 /* this seems to be needed for some (slow) devices */ 219 DELAY(10); 220 221 /* output actual command block */ 222 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 223 (int16_t *)request->u.atapi.ccb, 224 (request->device->param->config & ATA_PROTO_MASK) == 225 ATA_PROTO_ATAPI_12 ? 6 : 8); 226 227 /* return and wait for interrupt */ 228 return ATA_OP_CONTINUES; 229 230 case ATA_R_ATAPI|ATA_R_DMA: 231 /* is this just a POLL DSC command ? */ 232 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 233 ATA_IDX_OUTB(ch, ATA_DRIVE, 234 ATA_D_IBM | request->device->unit); 235 DELAY(10); 236 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC)) 237 request->result = EBUSY; 238 break; 239 } 240 241 /* check sanity, setup SG list and DMA engine */ 242 if (ch->dma->load(request->device, 243 request->data, 244 request->bytecount, 245 request->flags & ATA_R_READ)) { 246 ata_prtdev(request->device, "setting up DMA failed\n"); 247 request->result = EIO; 248 break; 249 } 250 251 /* start ATAPI operation */ 252 if (ch->hw.command(request->device, ATA_PACKET_CMD, 0, 0, ATA_F_DMA)) { 253 ata_prtdev(request->device, "error issuing ATAPI packet command\n"); 254 request->result = EIO; 255 break; 256 } 257 258 /* wait for ready to write ATAPI command block */ 259 { 260 int timeout = 5000; /* might be less for fast devices */ 261 while (timeout--) { 262 int reason = ATA_IDX_INB(ch, ATA_IREASON); 263 int status = ATA_IDX_INB(ch, ATA_STATUS); 264 265 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 266 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 267 break; 268 DELAY(20); 269 } 270 if (timeout <= 0) { 271 ata_prtdev(request->device,"timeout waiting for ATAPI ready\n"); 272 request->result = EIO; 273 break; 274 } 275 } 276 277 /* this seems to be needed for some (slow) devices */ 278 DELAY(10); 279 280 /* output actual command block */ 281 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 282 (int16_t *)request->u.atapi.ccb, 283 (request->device->param->config & ATA_PROTO_MASK) == 284 ATA_PROTO_ATAPI_12 ? 6 : 8); 285 286 /* start DMA engine */ 287 if (ch->dma->start(ch)) { 288 request->result = EIO; 289 break; 290 } 291 292 /* return and wait for interrupt */ 293 return ATA_OP_CONTINUES; 294 } 295 296 /* request finish here */ 297 if (ch->dma->flags & ATA_DMA_ACTIVE) 298 ch->dma->unload(ch); 299 ch->running = NULL; 300 return ATA_OP_FINISHED; 301 } 302 303 static void 304 ata_generic_interrupt(void *data) 305 { 306 struct ata_channel *ch = (struct ata_channel *)data; 307 struct ata_request *request = ch->running; 308 int length; 309 310 /* ignore this interrupt if there is no running request */ 311 if (!request) 312 return; 313 314 ATA_DEBUG_RQ(request, "interrupt"); 315 316 /* ignore interrupt if device is busy */ 317 if (!(request->flags & ATA_R_TIMEOUT) && 318 ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 319 DELAY(100); 320 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DRQ)) 321 return; 322 } 323 324 ATA_DEBUG_RQ(request, "interrupt accepted"); 325 326 /* clear interrupt and get status */ 327 request->status = ATA_IDX_INB(ch, ATA_STATUS); 328 329 /* register interrupt */ 330 if (!(request->flags & ATA_R_TIMEOUT)) 331 request->flags |= ATA_R_INTR_SEEN; 332 333 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 334 335 /* ATA PIO data transfer and control commands */ 336 default: 337 338 /* on control commands read back registers to the request struct */ 339 if (request->flags & ATA_R_CONTROL) { 340 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 341 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 342 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 343 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16); 344 } 345 346 /* if we got an error we are done with the HW */ 347 if (request->status & ATA_S_ERROR) { 348 request->error = ATA_IDX_INB(ch, ATA_ERROR); 349 break; 350 } 351 352 /* are we moving data ? */ 353 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 354 355 /* if read data get it */ 356 if (request->flags & ATA_R_READ) 357 ata_pio_read(request, request->transfersize); 358 359 /* update how far we've gotten */ 360 request->donecount += request->transfersize; 361 362 /* do we need a scoop more ? */ 363 if (request->bytecount > request->donecount) { 364 365 /* set this transfer size according to HW capabilities */ 366 request->transfersize = 367 min((request->bytecount - request->donecount), 368 request->transfersize); 369 370 /* clear interrupt seen flag as we need to wait again */ 371 request->flags &= ~ATA_R_INTR_SEEN; 372 373 /* if data write command, output the data */ 374 if (request->flags & ATA_R_WRITE) { 375 376 /* if we get an error here we are done with the HW */ 377 if (ata_wait(request->device, 378 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 379 ata_prtdev(request->device, 380 "timeout waiting for write DRQ"); 381 request->status = ATA_IDX_INB(ch, ATA_STATUS); 382 break; 383 } 384 385 /* output data and return waiting for new interrupt */ 386 ata_pio_write(request, request->transfersize); 387 return; 388 } 389 390 /* if data read command, return & wait for interrupt */ 391 if (request->flags & ATA_R_READ) 392 return; 393 } 394 } 395 /* done with HW */ 396 break; 397 398 /* ATA DMA data transfer commands */ 399 case ATA_R_DMA: 400 401 /* stop DMA engine and get status */ 402 if (ch->dma->stop) 403 request->dmastat = ch->dma->stop(ch); 404 405 /* did we get error or data */ 406 if (request->status & ATA_S_ERROR) 407 request->error = ATA_IDX_INB(ch, ATA_ERROR); 408 else if (request->dmastat & ATA_BMSTAT_ERROR) 409 request->status |= ATA_S_ERROR; 410 else 411 request->donecount = request->bytecount; 412 413 /* release SG list etc */ 414 ch->dma->unload(ch); 415 416 /* done with HW */ 417 break; 418 419 /* ATAPI PIO commands */ 420 case ATA_R_ATAPI: 421 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 422 423 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 424 (request->status & ATA_S_DRQ)) { 425 426 case ATAPI_P_CMDOUT: 427 /* this seems to be needed for some (slow) devices */ 428 DELAY(10); 429 430 if (!(request->status & ATA_S_DRQ)) { 431 ata_prtdev(request->device, "command interrupt without DRQ\n"); 432 request->status = ATA_S_ERROR; 433 break; 434 } 435 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 436 (request->device->param->config & 437 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); 438 /* return wait for interrupt */ 439 return; 440 441 case ATAPI_P_WRITE: 442 if (request->flags & ATA_R_READ) { 443 request->status = ATA_S_ERROR; 444 ata_prtdev(request->device, 445 "%s trying to write on read buffer\n", 446 ata_cmd2str(request)); 447 break; 448 } 449 ata_pio_write(request, length); 450 request->donecount += length; 451 452 /* set next transfer size according to HW capabilities */ 453 request->transfersize = min((request->bytecount-request->donecount), 454 request->transfersize); 455 /* return wait for interrupt */ 456 return; 457 458 case ATAPI_P_READ: 459 if (request->flags & ATA_R_WRITE) { 460 request->status = ATA_S_ERROR; 461 ata_prtdev(request->device, 462 "%s trying to read on write buffer\n", 463 ata_cmd2str(request)); 464 break; 465 } 466 ata_pio_read(request, length); 467 request->donecount += length; 468 469 /* set next transfer size according to HW capabilities */ 470 request->transfersize = min((request->bytecount-request->donecount), 471 request->transfersize); 472 /* return wait for interrupt */ 473 return; 474 475 case ATAPI_P_DONEDRQ: 476 ata_prtdev(request->device, 477 "WARNING - %s DONEDRQ non conformant device\n", 478 ata_cmd2str(request)); 479 if (request->flags & ATA_R_READ) { 480 ata_pio_read(request, length); 481 request->donecount += length; 482 } 483 else if (request->flags & ATA_R_WRITE) { 484 ata_pio_write(request, length); 485 request->donecount += length; 486 } 487 else 488 request->status = ATA_S_ERROR; 489 /* FALLTHROUGH */ 490 491 case ATAPI_P_ABORT: 492 case ATAPI_P_DONE: 493 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 494 request->error = ATA_IDX_INB(ch, ATA_ERROR); 495 break; 496 497 default: 498 ata_prtdev(request->device, "unknown transfer phase\n"); 499 request->status = ATA_S_ERROR; 500 } 501 502 /* done with HW */ 503 break; 504 505 /* ATAPI DMA commands */ 506 case ATA_R_ATAPI|ATA_R_DMA: 507 508 /* stop the engine and get engine status */ 509 if (ch->dma->stop) 510 request->dmastat = ch->dma->stop(ch); 511 512 /* did we get error or data */ 513 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 514 request->error = ATA_IDX_INB(ch, ATA_ERROR); 515 else if (request->dmastat & ATA_BMSTAT_ERROR) 516 request->status |= ATA_S_ERROR; 517 else 518 request->donecount = request->bytecount; 519 520 /* release SG list etc */ 521 ch->dma->unload(ch); 522 523 /* done with HW */ 524 break; 525 } 526 527 /* if we timed out the unlocking of the ATA channel is done later */ 528 if (!(request->flags & ATA_R_TIMEOUT)) { 529 ch->running = NULL; 530 ATA_UNLOCK_CH(ch); 531 ch->locking(ch, ATA_LF_UNLOCK); 532 } 533 534 /* schedule completition for this request */ 535 ata_finish(request); 536 } 537 538 /* must be called with ATA channel locked */ 539 static void 540 ata_generic_reset(struct ata_channel *ch) 541 { 542 u_int8_t err, lsb, msb, ostat0, ostat1; 543 u_int8_t stat0 = 0, stat1 = 0; 544 int mask = 0, timeout; 545 546 /* reset host end of channel (if supported) */ 547 if (ch->reset) 548 ch->reset(ch); 549 550 /* do we have any signs of ATA/ATAPI HW being present ? */ 551 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 552 DELAY(10); 553 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 554 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 555 stat0 = ATA_S_BUSY; 556 mask |= 0x01; 557 } 558 559 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 560 DELAY(10); 561 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 562 563 /* in some setups we dont want to test for a slave */ 564 if (!(ch->flags & ATA_NO_SLAVE)) { 565 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 566 stat1 = ATA_S_BUSY; 567 mask |= 0x02; 568 } 569 } 570 571 if (bootverbose) 572 ata_printf(ch, -1, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 573 mask, ostat0, ostat1); 574 575 /* if nothing showed up there is no need to get any further */ 576 /* SOS is that too strong?, we just might loose devices here XXX */ 577 ch->devices = 0; 578 if (!mask) 579 return; 580 581 /* reset (both) devices on this channel */ 582 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 583 DELAY(10); 584 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS | ATA_A_RESET); 585 DELAY(10000); 586 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS); 587 DELAY(100000); 588 ATA_IDX_INB(ch, ATA_ERROR); 589 590 /* wait for BUSY to go inactive */ 591 for (timeout = 0; timeout < 310; timeout++) { 592 if (stat0 & ATA_S_BUSY) { 593 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 594 DELAY(10); 595 err = ATA_IDX_INB(ch, ATA_ERROR); 596 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 597 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 598 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 599 if (bootverbose) 600 ata_printf(ch, ATA_MASTER, 601 "stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 602 stat0, err, lsb, msb); 603 if (!(stat0 & ATA_S_BUSY)) { 604 if ((err & 0x7f) == ATA_E_ILI) { 605 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 606 ch->devices |= ATA_ATAPI_MASTER; 607 } 608 else if (stat0 & ATA_S_READY) { 609 ch->devices |= ATA_ATA_MASTER; 610 } 611 } 612 else if ((stat0 & 0x4f) && err == lsb && err == msb) { 613 stat0 |= ATA_S_BUSY; 614 } 615 } 616 } 617 if (!((mask == 0x03) && (stat0 & ATA_S_BUSY)) && (stat1 & ATA_S_BUSY)) { 618 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 619 DELAY(10); 620 err = ATA_IDX_INB(ch, ATA_ERROR); 621 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 622 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 623 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 624 if (bootverbose) 625 ata_printf(ch, ATA_SLAVE, 626 " stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 627 stat1, err, lsb, msb); 628 if (!(stat1 & ATA_S_BUSY)) { 629 if ((err & 0x7f) == ATA_E_ILI) { 630 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 631 ch->devices |= ATA_ATAPI_SLAVE; 632 } 633 else if (stat1 & ATA_S_READY) { 634 ch->devices |= ATA_ATA_SLAVE; 635 } 636 } 637 else if ((stat1 & 0x4f) && err == lsb && err == msb) { 638 stat1 |= ATA_S_BUSY; 639 } 640 } 641 } 642 if (mask == 0x01) /* wait for master only */ 643 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 5)) 644 break; 645 if (mask == 0x02) /* wait for slave only */ 646 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 5)) 647 break; 648 if (mask == 0x03) { /* wait for both master & slave */ 649 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 650 break; 651 if (stat0 == 0xff && timeout > 5) 652 mask &= ~0x01; 653 if (stat1 == 0xff && timeout > 5) 654 mask &= ~0x02; 655 } 656 DELAY(100000); 657 } 658 659 if (bootverbose) 660 ata_printf(ch, -1, 661 "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n", 662 stat0, stat1, ch->devices, 663 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 664 } 665 666 static int 667 ata_wait(struct ata_device *atadev, u_int8_t mask) 668 { 669 u_int8_t status; 670 int timeout = 0; 671 672 DELAY(1); 673 674 /* wait 5 seconds for device to get !BUSY */ 675 while (timeout < 5000000) { 676 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 677 678 /* if drive fails status, reselect the drive just to be sure */ 679 if (status == 0xff) { 680 ata_prtdev(atadev, "WARNING no status, reselecting device\n"); 681 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit); 682 DELAY(10); 683 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 684 if (status == 0xff) 685 return -1; 686 } 687 688 /* are we done ? */ 689 if (!(status & ATA_S_BUSY)) 690 break; 691 692 if (timeout > 1000) { 693 timeout += 1000; 694 DELAY(1000); 695 } 696 else { 697 timeout += 10; 698 DELAY(10); 699 } 700 } 701 if (timeout >= 5000000) 702 return -1; 703 if (!mask) 704 return (status & ATA_S_ERROR); 705 706 DELAY(1); 707 708 /* wait 50 msec for bits wanted */ 709 timeout = 5000; 710 while (timeout--) { 711 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 712 if ((status & mask) == mask) 713 return (status & ATA_S_ERROR); 714 DELAY (10); 715 } 716 return -1; 717 } 718 719 int 720 ata_generic_command(struct ata_device *atadev, u_int8_t command, 721 u_int64_t lba, u_int16_t count, u_int16_t feature) 722 { 723 if (atadebug) 724 ata_prtdev(atadev, "ata_command: addr=%04lx, command=%02x, " 725 "lba=%jd, count=%d, feature=%d\n", 726 rman_get_start(atadev->channel->r_io[ATA_DATA].res), 727 command, (intmax_t)lba, count, feature); 728 729 /* select device */ 730 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit); 731 732 /* ready to issue command ? */ 733 if (ata_wait(atadev, 0) < 0) { 734 ata_prtdev(atadev, "timeout sending command=%02x\n", command); 735 return -1; 736 } 737 738 /* enable interrupt */ 739 ATA_IDX_OUTB(atadev->channel, ATA_ALTSTAT, ATA_A_4BIT); 740 741 /* only use 48bit addressing if needed (avoid bugs and overhead) */ 742 if ((lba > 268435455 || count > 256) && atadev->param && 743 atadev->param->support.command2 & ATA_SUPPORT_ADDRESS48) { 744 745 /* translate command into 48bit version */ 746 switch (command) { 747 case ATA_READ: 748 command = ATA_READ48; break; 749 case ATA_READ_MUL: 750 command = ATA_READ_MUL48; break; 751 case ATA_READ_DMA: 752 command = ATA_READ_DMA48; break; 753 case ATA_READ_DMA_QUEUED: 754 command = ATA_READ_DMA_QUEUED48; break; 755 case ATA_WRITE: 756 command = ATA_WRITE48; break; 757 case ATA_WRITE_MUL: 758 command = ATA_WRITE_MUL48; break; 759 case ATA_WRITE_DMA: 760 command = ATA_WRITE_DMA48; break; 761 case ATA_WRITE_DMA_QUEUED: 762 command = ATA_WRITE_DMA_QUEUED48; break; 763 case ATA_FLUSHCACHE: 764 command = ATA_FLUSHCACHE48; break; 765 default: 766 ata_prtdev(atadev, "can't translate cmd to 48bit version\n"); 767 return -1; 768 } 769 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, (feature>>8) & 0xff); 770 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature & 0xff); 771 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, (count>>8) & 0xff); 772 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count & 0xff); 773 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, (lba>>24) & 0xff); 774 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff); 775 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>32) & 0xff); 776 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff); 777 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>40) & 0xff); 778 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff); 779 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_LBA | atadev->unit); 780 atadev->channel->flags |= ATA_48BIT_ACTIVE; 781 } 782 else { 783 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature); 784 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count); 785 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff); 786 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff); 787 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff); 788 if (atadev->flags & ATA_D_USE_CHS) 789 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, 790 ATA_D_IBM | atadev->unit | ((lba>>24) & 0xf)); 791 else 792 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, 793 ATA_D_IBM | ATA_D_LBA | atadev->unit|((lba>>24)&0xf)); 794 atadev->channel->flags &= ~ATA_48BIT_ACTIVE; 795 } 796 797 /* issue command to controller */ 798 ATA_IDX_OUTB(atadev->channel, ATA_CMD, command); 799 800 return 0; 801 } 802 803 static void 804 ata_pio_read(struct ata_request *request, int length) 805 { 806 int size = min(request->transfersize, length); 807 struct ata_channel *ch = request->device->channel; 808 int resid; 809 810 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 811 ATA_IDX_INSW_STRM(ch, ATA_DATA, 812 (void*)((uintptr_t)request->data+request->donecount), 813 size / sizeof(int16_t)); 814 else 815 ATA_IDX_INSL_STRM(ch, ATA_DATA, 816 (void*)((uintptr_t)request->data+request->donecount), 817 size / sizeof(int32_t)); 818 819 if (request->transfersize < length) { 820 ata_prtdev(request->device, "WARNING - %s read data overrun %d>%d\n", 821 ata_cmd2str(request), length, request->transfersize); 822 for (resid = request->transfersize; resid < length; 823 resid += sizeof(int16_t)) 824 ATA_IDX_INW(ch, ATA_DATA); 825 } 826 } 827 828 static void 829 ata_pio_write(struct ata_request *request, int length) 830 { 831 int size = min(request->transfersize, length); 832 struct ata_channel *ch = request->device->channel; 833 int resid; 834 835 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 836 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 837 (void*)((uintptr_t)request->data+request->donecount), 838 size / sizeof(int16_t)); 839 else 840 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 841 (void*)((uintptr_t)request->data+request->donecount), 842 size / sizeof(int32_t)); 843 844 if (request->transfersize < length) { 845 ata_prtdev(request->device, "WARNING - %s write data underrun %d>%d\n", 846 ata_cmd2str(request), length, request->transfersize); 847 for (resid = request->transfersize; resid < length; 848 resid += sizeof(int16_t)) 849 ATA_IDX_OUTW(ch, ATA_DATA, 0); 850 } 851 } 852