1 /*- 2 * Copyright (c) 1998 - 2004 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_ata.h" 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/ata.h> 36 #include <sys/kernel.h> 37 #include <sys/conf.h> 38 #include <sys/bus.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/ata/ata-all.h> 45 46 /* prototypes */ 47 static int ata_generic_transaction(struct ata_request *); 48 static void ata_generic_interrupt(void *); 49 static void ata_generic_reset(struct ata_channel *); 50 static int ata_wait(struct ata_device *, u_int8_t); 51 /*static int ata_command(struct ata_device *, u_int8_t, u_int64_t, u_int16_t, u_int16_t);*/ 52 static void ata_pio_read(struct ata_request *, int); 53 static void ata_pio_write(struct ata_request *, int); 54 55 /* local vars */ 56 static int atadebug = 0; 57 58 /* 59 * low level ATA functions 60 */ 61 void 62 ata_generic_hw(struct ata_channel *ch) 63 { 64 ch->hw.reset = ata_generic_reset; 65 ch->hw.transaction = ata_generic_transaction; 66 ch->hw.interrupt = ata_generic_interrupt; 67 ch->hw.command = ata_generic_command; 68 } 69 70 /* must be called with ATA channel locked */ 71 static int 72 ata_generic_transaction(struct ata_request *request) 73 { 74 struct ata_channel *ch = request->device->channel; 75 76 /* safetybelt for HW that went away */ 77 if (!request->device->param || request->device->channel->flags&ATA_HWGONE) { 78 request->result = ENXIO; 79 return ATA_OP_FINISHED; 80 } 81 82 /* record the request as running */ 83 ch->running = request; 84 85 ATA_DEBUG_RQ(request, "transaction"); 86 87 /* disable ATAPI DMA writes if HW doesn't support it */ 88 if ((ch->flags & ATA_ATAPI_DMA_RO) && 89 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 90 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 91 request->flags &= ~ATA_R_DMA; 92 93 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 94 95 /* ATA PIO data transfer and control commands */ 96 default: 97 { 98 /* record command direction here as our request might be gone later */ 99 int write = (request->flags & ATA_R_WRITE); 100 101 /* issue command */ 102 if (ch->hw.command(request->device, request->u.ata.command, 103 request->u.ata.lba, request->u.ata.count, 104 request->u.ata.feature)) { 105 ata_prtdev(request->device, "error issueing PIO command\n"); 106 request->result = EIO; 107 break; 108 } 109 110 /* if write command output the data */ 111 if (write) { 112 if (ata_wait(request->device, 113 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 114 ata_prtdev(request->device,"timeout waiting for write DRQ"); 115 request->result = EIO; 116 break; 117 } 118 ata_pio_write(request, request->transfersize); 119 } 120 } 121 122 /* return and wait for interrupt */ 123 return ATA_OP_CONTINUES; 124 125 /* ATA DMA data transfer commands */ 126 case ATA_R_DMA: 127 /* check sanity, setup SG list and DMA engine */ 128 if (ch->dma->load(request->device, request->data, request->bytecount, 129 request->flags & ATA_R_READ)) { 130 ata_prtdev(request->device, "setting up DMA failed\n"); 131 request->result = EIO; 132 break; 133 } 134 135 /* issue command */ 136 if (ch->hw.command(request->device, request->u.ata.command, 137 request->u.ata.lba, request->u.ata.count, 138 request->u.ata.feature)) { 139 ata_prtdev(request->device, "error issuing DMA command\n"); 140 request->result = EIO; 141 break; 142 } 143 144 /* start DMA engine */ 145 if (ch->dma->start(ch)) { 146 ata_prtdev(request->device, "error starting DMA\n"); 147 request->result = EIO; 148 break; 149 } 150 151 /* return and wait for interrupt */ 152 return ATA_OP_CONTINUES; 153 154 /* ATAPI PIO commands */ 155 case ATA_R_ATAPI: 156 /* is this just a POLL DSC command ? */ 157 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 158 ATA_IDX_OUTB(ch, ATA_DRIVE, 159 ATA_D_IBM | request->device->unit); 160 DELAY(10); 161 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC)) 162 request->result = EBUSY; 163 break; 164 } 165 166 /* start ATAPI operation */ 167 if (ch->hw.command(request->device, ATA_PACKET_CMD, 168 request->transfersize << 8, 0, 0)) { 169 ata_prtdev(request->device, "error issuing ATA PACKET command\n"); 170 request->result = EIO; 171 break; 172 } 173 174 /* command interrupt device ? just return and wait for interrupt */ 175 if ((request->device->param->config & ATA_DRQ_MASK) == ATA_DRQ_INTR) 176 return ATA_OP_CONTINUES; 177 178 /* wait for ready to write ATAPI command block */ 179 { 180 int timeout = 5000; /* might be less for fast devices */ 181 while (timeout--) { 182 int reason = ATA_IDX_INB(ch, ATA_IREASON); 183 int status = ATA_IDX_INB(ch, ATA_STATUS); 184 185 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 186 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 187 break; 188 DELAY(20); 189 } 190 if (timeout <= 0) { 191 ata_prtdev(request->device, 192 "timeout waiting for ATAPI ready\n"); 193 request->result = EIO; 194 break; 195 } 196 } 197 198 /* this seems to be needed for some (slow) devices */ 199 DELAY(10); 200 201 /* output actual command block */ 202 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 203 (int16_t *)request->u.atapi.ccb, 204 (request->device->param->config & ATA_PROTO_MASK) == 205 ATA_PROTO_ATAPI_12 ? 6 : 8); 206 207 /* return and wait for interrupt */ 208 return ATA_OP_CONTINUES; 209 210 case ATA_R_ATAPI|ATA_R_DMA: 211 /* is this just a POLL DSC command ? */ 212 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 213 ATA_IDX_OUTB(ch, ATA_DRIVE, 214 ATA_D_IBM | request->device->unit); 215 DELAY(10); 216 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC)) 217 request->result = EBUSY; 218 break; 219 } 220 221 /* check sanity, setup SG list and DMA engine */ 222 if (ch->dma->load(request->device, 223 request->data, 224 request->bytecount, 225 request->flags & ATA_R_READ)) { 226 ata_prtdev(request->device, "setting up DMA failed\n"); 227 request->result = EIO; 228 break; 229 } 230 231 /* start ATAPI operation */ 232 if (ch->hw.command(request->device, ATA_PACKET_CMD, 0, 0, ATA_F_DMA)) { 233 ata_prtdev(request->device, "error issuing ATAPI packet command\n"); 234 request->result = EIO; 235 break; 236 } 237 238 /* wait for ready to write ATAPI command block */ 239 { 240 int timeout = 5000; /* might be less for fast devices */ 241 while (timeout--) { 242 int reason = ATA_IDX_INB(ch, ATA_IREASON); 243 int status = ATA_IDX_INB(ch, ATA_STATUS); 244 245 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 246 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 247 break; 248 DELAY(20); 249 } 250 if (timeout <= 0) { 251 ata_prtdev(request->device,"timeout waiting for ATAPI ready\n"); 252 request->result = EIO; 253 break; 254 } 255 } 256 257 /* this seems to be needed for some (slow) devices */ 258 DELAY(10); 259 260 /* output actual command block */ 261 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 262 (int16_t *)request->u.atapi.ccb, 263 (request->device->param->config & ATA_PROTO_MASK) == 264 ATA_PROTO_ATAPI_12 ? 6 : 8); 265 266 /* start DMA engine */ 267 if (ch->dma->start(ch)) { 268 request->result = EIO; 269 break; 270 } 271 272 /* return and wait for interrupt */ 273 return ATA_OP_CONTINUES; 274 } 275 276 /* request finish here */ 277 if (ch->dma->flags & ATA_DMA_ACTIVE) 278 ch->dma->unload(ch); 279 ch->running = NULL; 280 return ATA_OP_FINISHED; 281 } 282 283 static void 284 ata_generic_interrupt(void *data) 285 { 286 struct ata_channel *ch = (struct ata_channel *)data; 287 struct ata_request *request = ch->running; 288 int length; 289 290 /* ignore this interrupt if there is no running request */ 291 if (!request) { 292 if (ATA_LOCK_CH(ch)) { 293 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 294 u_int8_t error = ATA_IDX_INB(ch, ATA_ERROR); 295 296 if (bootverbose) 297 ata_printf(ch, -1, 298 "spurious interrupt - status=0x%02x error=0x%02x\n", 299 status, error); 300 ATA_UNLOCK_CH(ch); 301 } 302 else { 303 if (bootverbose) 304 ata_printf(ch, -1, "spurious interrupt - channel busy\n"); 305 } 306 return; 307 } 308 309 ATA_DEBUG_RQ(request, "interrupt"); 310 311 /* ignore interrupt if device is busy */ 312 if (!(request->flags & ATA_R_TIMEOUT) && 313 ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 314 DELAY(100); 315 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DRQ)) 316 return; 317 } 318 319 ATA_DEBUG_RQ(request, "interrupt accepted"); 320 321 /* clear interrupt and get status */ 322 request->status = ATA_IDX_INB(ch, ATA_STATUS); 323 324 /* register interrupt */ 325 if (!(request->flags & ATA_R_TIMEOUT)) 326 request->flags |= ATA_R_INTR_SEEN; 327 328 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 329 330 /* ATA PIO data transfer and control commands */ 331 default: 332 333 /* on control commands read back registers to the request struct */ 334 if (request->flags & ATA_R_CONTROL) { 335 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 336 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 337 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 338 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16); 339 } 340 341 /* if we got an error we are done with the HW */ 342 if (request->status & ATA_S_ERROR) { 343 request->error = ATA_IDX_INB(ch, ATA_ERROR); 344 break; 345 } 346 347 /* are we moving data ? */ 348 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 349 350 /* if read data get it */ 351 if (request->flags & ATA_R_READ) 352 ata_pio_read(request, request->transfersize); 353 354 /* update how far we've gotten */ 355 request->donecount += request->transfersize; 356 357 /* do we need a scoop more ? */ 358 if (request->bytecount > request->donecount) { 359 360 /* set this transfer size according to HW capabilities */ 361 request->transfersize = 362 min((request->bytecount - request->donecount), 363 request->transfersize); 364 365 /* clear interrupt seen flag as we need to wait again */ 366 request->flags &= ~ATA_R_INTR_SEEN; 367 368 /* if data write command, output the data */ 369 if (request->flags & ATA_R_WRITE) { 370 371 /* if we get an error here we are done with the HW */ 372 if (ata_wait(request->device, 373 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 374 ata_prtdev(request->device, 375 "timeout waiting for write DRQ"); 376 request->status = ATA_IDX_INB(ch, ATA_STATUS); 377 break; 378 } 379 380 /* output data and return waiting for new interrupt */ 381 ata_pio_write(request, request->transfersize); 382 return; 383 } 384 385 /* if data read command, return & wait for interrupt */ 386 if (request->flags & ATA_R_READ) 387 return; 388 } 389 } 390 /* done with HW */ 391 break; 392 393 /* ATA DMA data transfer commands */ 394 case ATA_R_DMA: 395 396 /* stop DMA engine and get status */ 397 if (ch->dma->stop) 398 request->dmastat = ch->dma->stop(ch); 399 400 /* did we get error or data */ 401 if (request->status & ATA_S_ERROR) 402 request->error = ATA_IDX_INB(ch, ATA_ERROR); 403 else if (request->dmastat & ATA_BMSTAT_ERROR) 404 request->status |= ATA_S_ERROR; 405 else 406 request->donecount = request->bytecount; 407 408 /* release SG list etc */ 409 ch->dma->unload(ch); 410 411 /* done with HW */ 412 break; 413 414 /* ATAPI PIO commands */ 415 case ATA_R_ATAPI: 416 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 417 418 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 419 (request->status & ATA_S_DRQ)) { 420 421 case ATAPI_P_CMDOUT: 422 /* this seems to be needed for some (slow) devices */ 423 DELAY(10); 424 425 if (!(request->status & ATA_S_DRQ)) { 426 ata_prtdev(request->device, "command interrupt without DRQ\n"); 427 request->status = ATA_S_ERROR; 428 break; 429 } 430 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 431 (request->device->param->config & 432 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); 433 /* return wait for interrupt */ 434 return; 435 436 case ATAPI_P_WRITE: 437 if (request->flags & ATA_R_READ) { 438 request->status = ATA_S_ERROR; 439 ata_prtdev(request->device, 440 "%s trying to write on read buffer\n", 441 ata_cmd2str(request)); 442 break; 443 } 444 ata_pio_write(request, length); 445 request->donecount += length; 446 447 /* set next transfer size according to HW capabilities */ 448 request->transfersize = min((request->bytecount-request->donecount), 449 request->transfersize); 450 /* return wait for interrupt */ 451 return; 452 453 case ATAPI_P_READ: 454 if (request->flags & ATA_R_WRITE) { 455 request->status = ATA_S_ERROR; 456 ata_prtdev(request->device, 457 "%s trying to read on write buffer\n", 458 ata_cmd2str(request)); 459 break; 460 } 461 ata_pio_read(request, length); 462 request->donecount += length; 463 464 /* set next transfer size according to HW capabilities */ 465 request->transfersize = min((request->bytecount-request->donecount), 466 request->transfersize); 467 /* return wait for interrupt */ 468 return; 469 470 case ATAPI_P_DONEDRQ: 471 ata_prtdev(request->device, 472 "WARNING - %s DONEDRQ non conformant device\n", 473 ata_cmd2str(request)); 474 if (request->flags & ATA_R_READ) { 475 ata_pio_read(request, length); 476 request->donecount += length; 477 } 478 else if (request->flags & ATA_R_WRITE) { 479 ata_pio_write(request, length); 480 request->donecount += length; 481 } 482 else 483 request->status = ATA_S_ERROR; 484 /* FALLTHROUGH */ 485 486 case ATAPI_P_ABORT: 487 case ATAPI_P_DONE: 488 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 489 request->error = ATA_IDX_INB(ch, ATA_ERROR); 490 break; 491 492 default: 493 ata_prtdev(request->device, "unknown transfer phase\n"); 494 request->status = ATA_S_ERROR; 495 } 496 497 /* done with HW */ 498 break; 499 500 /* ATAPI DMA commands */ 501 case ATA_R_ATAPI|ATA_R_DMA: 502 503 /* stop the engine and get engine status */ 504 if (ch->dma->stop) 505 request->dmastat = ch->dma->stop(ch); 506 507 /* did we get error or data */ 508 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 509 request->error = ATA_IDX_INB(ch, ATA_ERROR); 510 else if (request->dmastat & ATA_BMSTAT_ERROR) 511 request->status |= ATA_S_ERROR; 512 else 513 request->donecount = request->bytecount; 514 515 /* release SG list etc */ 516 ch->dma->unload(ch); 517 518 /* done with HW */ 519 break; 520 } 521 522 /* if we timed out the unlocking of the ATA channel is done later */ 523 if (!(request->flags & ATA_R_TIMEOUT)) { 524 ch->running = NULL; 525 ATA_UNLOCK_CH(ch); 526 ch->locking(ch, ATA_LF_UNLOCK); 527 } 528 529 /* schedule completition for this request */ 530 ata_finish(request); 531 } 532 533 /* must be called with ATA channel locked */ 534 static void 535 ata_generic_reset(struct ata_channel *ch) 536 { 537 u_int8_t err, lsb, msb, ostat0, ostat1; 538 u_int8_t stat0 = 0, stat1 = 0; 539 int mask = 0, timeout; 540 541 /* reset host end of channel (if supported) */ 542 if (ch->reset) 543 ch->reset(ch); 544 545 /* do we have any signs of ATA/ATAPI HW being present ? */ 546 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 547 DELAY(10); 548 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 549 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 550 stat0 = ATA_S_BUSY; 551 mask |= 0x01; 552 } 553 554 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 555 DELAY(10); 556 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 557 558 /* in some setups we dont want to test for a slave */ 559 if (!(ch->flags & ATA_NO_SLAVE)) { 560 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 561 stat1 = ATA_S_BUSY; 562 mask |= 0x02; 563 } 564 } 565 566 if (bootverbose) 567 ata_printf(ch, -1, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 568 mask, ostat0, ostat1); 569 570 /* if nothing showed up there is no need to get any further */ 571 /* SOS is that too strong?, we just might loose devices here XXX */ 572 ch->devices = 0; 573 if (!mask) 574 return; 575 576 /* reset (both) devices on this channel */ 577 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 578 DELAY(10); 579 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS | ATA_A_RESET); 580 DELAY(10000); 581 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS); 582 DELAY(100000); 583 ATA_IDX_INB(ch, ATA_ERROR); 584 585 /* wait for BUSY to go inactive */ 586 for (timeout = 0; timeout < 310; timeout++) { 587 if (stat0 & ATA_S_BUSY) { 588 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 589 DELAY(10); 590 err = ATA_IDX_INB(ch, ATA_ERROR); 591 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 592 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 593 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 594 if (bootverbose) 595 ata_printf(ch, ATA_MASTER, 596 "stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 597 stat0, err, lsb, msb); 598 if (!(stat0 & ATA_S_BUSY)) { 599 if ((err & 0x7f) == ATA_E_ILI) { 600 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 601 ch->devices |= ATA_ATAPI_MASTER; 602 } 603 else if (stat0 & ATA_S_READY) { 604 ch->devices |= ATA_ATA_MASTER; 605 } 606 } 607 else if ((stat0 & 0x4f) && err == lsb && err == msb) { 608 stat0 |= ATA_S_BUSY; 609 } 610 } 611 } 612 if (!((mask == 0x03) && (stat0 & ATA_S_BUSY)) && (stat1 & ATA_S_BUSY)) { 613 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 614 DELAY(10); 615 err = ATA_IDX_INB(ch, ATA_ERROR); 616 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 617 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 618 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 619 if (bootverbose) 620 ata_printf(ch, ATA_SLAVE, 621 " stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 622 stat1, err, lsb, msb); 623 if (!(stat1 & ATA_S_BUSY)) { 624 if ((err & 0x7f) == ATA_E_ILI) { 625 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 626 ch->devices |= ATA_ATAPI_SLAVE; 627 } 628 else if (stat1 & ATA_S_READY) { 629 ch->devices |= ATA_ATA_SLAVE; 630 } 631 } 632 else if ((stat1 & 0x4f) && err == lsb && err == msb) { 633 stat1 |= ATA_S_BUSY; 634 } 635 } 636 } 637 if (mask == 0x01) /* wait for master only */ 638 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 5)) 639 break; 640 if (mask == 0x02) /* wait for slave only */ 641 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 5)) 642 break; 643 if (mask == 0x03) { /* wait for both master & slave */ 644 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 645 break; 646 if (stat0 == 0xff && timeout > 5) 647 mask &= ~0x01; 648 if (stat1 == 0xff && timeout > 5) 649 mask &= ~0x02; 650 } 651 DELAY(100000); 652 } 653 654 if (stat0 & ATA_S_BUSY) 655 mask &= ~0x01; 656 if (stat1 & ATA_S_BUSY) 657 mask &= ~0x02; 658 659 if (bootverbose) 660 ata_printf(ch, -1, 661 "reset tp2 mask=%02x stat0=%02x stat1=%02x devices=0x%b\n", 662 mask, stat0, stat1, ch->devices, 663 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 664 } 665 666 static int 667 ata_wait(struct ata_device *atadev, u_int8_t mask) 668 { 669 u_int8_t status; 670 int timeout = 0; 671 672 DELAY(1); 673 674 /* wait 5 seconds for device to get !BUSY */ 675 while (timeout < 5000000) { 676 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 677 678 /* if drive fails status, reselect the drive just to be sure */ 679 if (status == 0xff) { 680 ata_prtdev(atadev, "WARNING no status, reselecting device\n"); 681 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit); 682 DELAY(10); 683 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 684 if (status == 0xff) 685 return -1; 686 } 687 688 /* are we done ? */ 689 if (!(status & ATA_S_BUSY)) 690 break; 691 692 if (timeout > 1000) { 693 timeout += 1000; 694 DELAY(1000); 695 } 696 else { 697 timeout += 10; 698 DELAY(10); 699 } 700 } 701 if (timeout >= 5000000) 702 return -1; 703 if (!mask) 704 return (status & ATA_S_ERROR); 705 706 DELAY(1); 707 708 /* wait 50 msec for bits wanted */ 709 timeout = 5000; 710 while (timeout--) { 711 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 712 if ((status & mask) == mask) 713 return (status & ATA_S_ERROR); 714 DELAY (10); 715 } 716 return -1; 717 } 718 719 int 720 ata_generic_command(struct ata_device *atadev, u_int8_t command, 721 u_int64_t lba, u_int16_t count, u_int16_t feature) 722 { 723 if (atadebug) 724 ata_prtdev(atadev, "ata_command: addr=%04lx, command=%02x, " 725 "lba=%jd, count=%d, feature=%d\n", 726 rman_get_start(atadev->channel->r_io[ATA_DATA].res), 727 command, (intmax_t)lba, count, feature); 728 729 /* select device */ 730 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit); 731 732 /* ready to issue command ? */ 733 if (ata_wait(atadev, 0) < 0) { 734 ata_prtdev(atadev, "timeout sending command=%02x\n", command); 735 return -1; 736 } 737 738 /* enable interrupt */ 739 ATA_IDX_OUTB(atadev->channel, ATA_ALTSTAT, ATA_A_4BIT); 740 741 /* only use 48bit addressing if needed (avoid bugs and overhead) */ 742 if ((lba > 268435455 || count > 256) && atadev->param && 743 atadev->param->support.command2 & ATA_SUPPORT_ADDRESS48) { 744 745 /* translate command into 48bit version */ 746 switch (command) { 747 case ATA_READ: 748 command = ATA_READ48; break; 749 case ATA_READ_MUL: 750 command = ATA_READ_MUL48; break; 751 case ATA_READ_DMA: 752 command = ATA_READ_DMA48; break; 753 case ATA_READ_DMA_QUEUED: 754 command = ATA_READ_DMA_QUEUED48; break; 755 case ATA_WRITE: 756 command = ATA_WRITE48; break; 757 case ATA_WRITE_MUL: 758 command = ATA_WRITE_MUL48; break; 759 case ATA_WRITE_DMA: 760 command = ATA_WRITE_DMA48; break; 761 case ATA_WRITE_DMA_QUEUED: 762 command = ATA_WRITE_DMA_QUEUED48; break; 763 case ATA_FLUSHCACHE: 764 command = ATA_FLUSHCACHE48; break; 765 default: 766 ata_prtdev(atadev, "can't translate cmd to 48bit version\n"); 767 return -1; 768 } 769 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, (feature>>8) & 0xff); 770 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature & 0xff); 771 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, (count>>8) & 0xff); 772 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count & 0xff); 773 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, (lba>>24) & 0xff); 774 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff); 775 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>32) & 0xff); 776 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff); 777 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>40) & 0xff); 778 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff); 779 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_LBA | atadev->unit); 780 atadev->channel->flags |= ATA_48BIT_ACTIVE; 781 } 782 else { 783 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature); 784 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count); 785 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff); 786 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff); 787 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff); 788 if (atadev->flags & ATA_D_USE_CHS) 789 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, 790 ATA_D_IBM | atadev->unit | ((lba>>24) & 0xf)); 791 else 792 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, 793 ATA_D_IBM | ATA_D_LBA | atadev->unit|((lba>>24)&0xf)); 794 atadev->channel->flags &= ~ATA_48BIT_ACTIVE; 795 } 796 797 /* issue command to controller */ 798 ATA_IDX_OUTB(atadev->channel, ATA_CMD, command); 799 800 return 0; 801 } 802 803 static void 804 ata_pio_read(struct ata_request *request, int length) 805 { 806 int size = min(request->transfersize, length); 807 struct ata_channel *ch = request->device->channel; 808 int resid; 809 810 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 811 ATA_IDX_INSW_STRM(ch, ATA_DATA, 812 (void*)((uintptr_t)request->data+request->donecount), 813 size / sizeof(int16_t)); 814 else 815 ATA_IDX_INSL_STRM(ch, ATA_DATA, 816 (void*)((uintptr_t)request->data+request->donecount), 817 size / sizeof(int32_t)); 818 819 if (request->transfersize < length) { 820 ata_prtdev(request->device, "WARNING - %s read data overrun %d>%d\n", 821 ata_cmd2str(request), length, request->transfersize); 822 for (resid = request->transfersize; resid < length; 823 resid += sizeof(int16_t)) 824 ATA_IDX_INW(ch, ATA_DATA); 825 } 826 } 827 828 static void 829 ata_pio_write(struct ata_request *request, int length) 830 { 831 int size = min(request->transfersize, length); 832 struct ata_channel *ch = request->device->channel; 833 int resid; 834 835 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 836 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 837 (void*)((uintptr_t)request->data+request->donecount), 838 size / sizeof(int16_t)); 839 else 840 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 841 (void*)((uintptr_t)request->data+request->donecount), 842 size / sizeof(int32_t)); 843 844 if (request->transfersize < length) { 845 ata_prtdev(request->device, "WARNING - %s write data underrun %d>%d\n", 846 ata_cmd2str(request), length, request->transfersize); 847 for (resid = request->transfersize; resid < length; 848 resid += sizeof(int16_t)) 849 ATA_IDX_OUTW(ch, ATA_DATA, 0); 850 } 851 } 852