1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/endian.h> 35 #include <sys/ata.h> 36 #include <sys/conf.h> 37 #include <sys/ctype.h> 38 #include <sys/bus.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/ata/ata-all.h> 45 #include <dev/ata/ata-pci.h> 46 #include <ata_if.h> 47 48 /* prototypes */ 49 static int ata_generic_status(device_t dev); 50 static int ata_wait(struct ata_channel *ch, int unit, u_int8_t); 51 static void ata_pio_read(struct ata_request *, int); 52 static void ata_pio_write(struct ata_request *, int); 53 static void ata_tf_read(struct ata_request *); 54 static void ata_tf_write(struct ata_request *); 55 56 /* 57 * low level ATA functions 58 */ 59 void 60 ata_generic_hw(device_t dev) 61 { 62 struct ata_channel *ch = device_get_softc(dev); 63 64 ch->hw.begin_transaction = ata_begin_transaction; 65 ch->hw.end_transaction = ata_end_transaction; 66 ch->hw.status = ata_generic_status; 67 ch->hw.softreset = NULL; 68 ch->hw.command = ata_generic_command; 69 ch->hw.tf_read = ata_tf_read; 70 ch->hw.tf_write = ata_tf_write; 71 ch->hw.pm_read = NULL; 72 ch->hw.pm_write = NULL; 73 } 74 75 /* must be called with ATA channel locked and state_mtx held */ 76 int 77 ata_begin_transaction(struct ata_request *request) 78 { 79 struct ata_channel *ch = device_get_softc(request->parent); 80 int dummy, error; 81 82 ATA_DEBUG_RQ(request, "begin transaction"); 83 84 /* disable ATAPI DMA writes if HW doesn't support it */ 85 if ((ch->flags & ATA_NO_ATAPI_DMA) && 86 (request->flags & ATA_R_ATAPI) == ATA_R_ATAPI) 87 request->flags &= ~ATA_R_DMA; 88 if ((ch->flags & ATA_ATAPI_DMA_RO) && 89 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 90 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 91 request->flags &= ~ATA_R_DMA; 92 93 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 94 95 /* ATA PIO data transfer and control commands */ 96 default: 97 { 98 /* record command direction here as our request might be gone later */ 99 int write = (request->flags & ATA_R_WRITE); 100 101 /* issue command */ 102 if (ch->hw.command(request)) { 103 device_printf(request->parent, "error issuing %s command\n", 104 ata_cmd2str(request)); 105 request->result = EIO; 106 goto begin_finished; 107 } 108 109 /* device reset doesn't interrupt */ 110 if (request->u.ata.command == ATA_DEVICE_RESET) { 111 112 int timeout = 1000000; 113 do { 114 DELAY(10); 115 request->status = ATA_IDX_INB(ch, ATA_STATUS); 116 } while (request->status & ATA_S_BUSY && timeout--); 117 if (request->status & ATA_S_ERROR) 118 request->error = ATA_IDX_INB(ch, ATA_ERROR); 119 ch->hw.tf_read(request); 120 goto begin_finished; 121 } 122 123 /* if write command output the data */ 124 if (write) { 125 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) { 126 device_printf(request->parent, 127 "timeout waiting for write DRQ\n"); 128 request->result = EIO; 129 goto begin_finished; 130 } 131 ata_pio_write(request, request->transfersize); 132 } 133 } 134 goto begin_continue; 135 136 /* ATA DMA data transfer commands */ 137 case ATA_R_DMA: 138 /* check sanity, setup SG list and DMA engine */ 139 if ((error = ch->dma.load(request, NULL, &dummy))) { 140 device_printf(request->parent, "setting up DMA failed\n"); 141 request->result = error; 142 goto begin_finished; 143 } 144 145 /* start DMA engine if necessary */ 146 if ((ch->flags & ATA_DMA_BEFORE_CMD) && 147 ch->dma.start && ch->dma.start(request)) { 148 device_printf(request->parent, "error starting DMA\n"); 149 request->result = EIO; 150 goto begin_finished; 151 } 152 153 /* issue command */ 154 if (ch->hw.command(request)) { 155 device_printf(request->parent, "error issuing %s command\n", 156 ata_cmd2str(request)); 157 request->result = EIO; 158 goto begin_finished; 159 } 160 161 /* start DMA engine */ 162 if (!(ch->flags & ATA_DMA_BEFORE_CMD) && 163 ch->dma.start && ch->dma.start(request)) { 164 device_printf(request->parent, "error starting DMA\n"); 165 request->result = EIO; 166 goto begin_finished; 167 } 168 goto begin_continue; 169 170 /* ATAPI PIO commands */ 171 case ATA_R_ATAPI: 172 /* is this just a POLL DSC command ? */ 173 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 174 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit)); 175 DELAY(10); 176 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 177 request->result = EBUSY; 178 goto begin_finished; 179 } 180 181 /* start ATAPI operation */ 182 if (ch->hw.command(request)) { 183 device_printf(request->parent, "error issuing ATA PACKET command\n"); 184 request->result = EIO; 185 goto begin_finished; 186 } 187 goto begin_continue; 188 189 /* ATAPI DMA commands */ 190 case ATA_R_ATAPI|ATA_R_DMA: 191 /* is this just a POLL DSC command ? */ 192 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 193 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit)); 194 DELAY(10); 195 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 196 request->result = EBUSY; 197 goto begin_finished; 198 } 199 200 /* check sanity, setup SG list and DMA engine */ 201 if ((error = ch->dma.load(request, NULL, &dummy))) { 202 device_printf(request->parent, "setting up DMA failed\n"); 203 request->result = error; 204 goto begin_finished; 205 } 206 207 /* start ATAPI operation */ 208 if (ch->hw.command(request)) { 209 device_printf(request->parent, "error issuing ATA PACKET command\n"); 210 request->result = EIO; 211 goto begin_finished; 212 } 213 214 /* start DMA engine */ 215 if (ch->dma.start && ch->dma.start(request)) { 216 request->result = EIO; 217 goto begin_finished; 218 } 219 goto begin_continue; 220 } 221 /* NOT REACHED */ 222 printf("ata_begin_transaction OOPS!!!\n"); 223 224 begin_finished: 225 if (ch->dma.unload) { 226 ch->dma.unload(request); 227 } 228 return ATA_OP_FINISHED; 229 230 begin_continue: 231 callout_reset(&request->callout, request->timeout * hz, 232 (timeout_t*)ata_timeout, request); 233 return ATA_OP_CONTINUES; 234 } 235 236 /* must be called with ATA channel locked and state_mtx held */ 237 int 238 ata_end_transaction(struct ata_request *request) 239 { 240 struct ata_channel *ch = device_get_softc(request->parent); 241 int length; 242 243 ATA_DEBUG_RQ(request, "end transaction"); 244 245 /* clear interrupt and get status */ 246 request->status = ATA_IDX_INB(ch, ATA_STATUS); 247 248 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 249 250 /* ATA PIO data transfer and control commands */ 251 default: 252 253 /* on timeouts we have no data or anything so just return */ 254 if (request->flags & ATA_R_TIMEOUT) 255 goto end_finished; 256 257 /* Read back registers to the request struct. */ 258 if ((request->status & ATA_S_ERROR) || 259 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT))) { 260 ch->hw.tf_read(request); 261 } 262 263 /* if we got an error we are done with the HW */ 264 if (request->status & ATA_S_ERROR) { 265 request->error = ATA_IDX_INB(ch, ATA_ERROR); 266 goto end_finished; 267 } 268 269 /* are we moving data ? */ 270 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 271 272 /* if read data get it */ 273 if (request->flags & ATA_R_READ) { 274 int flags = ATA_S_DRQ; 275 276 if (request->u.ata.command != ATA_ATAPI_IDENTIFY) 277 flags |= ATA_S_READY; 278 if (ata_wait(ch, request->unit, flags) < 0) { 279 device_printf(request->parent, 280 "timeout waiting for read DRQ\n"); 281 request->result = EIO; 282 goto end_finished; 283 } 284 ata_pio_read(request, request->transfersize); 285 } 286 287 /* update how far we've gotten */ 288 request->donecount += request->transfersize; 289 290 /* do we need a scoop more ? */ 291 if (request->bytecount > request->donecount) { 292 293 /* set this transfer size according to HW capabilities */ 294 request->transfersize = 295 min((request->bytecount - request->donecount), 296 request->transfersize); 297 298 /* if data write command, output the data */ 299 if (request->flags & ATA_R_WRITE) { 300 301 /* if we get an error here we are done with the HW */ 302 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) { 303 device_printf(request->parent, 304 "timeout waiting for write DRQ\n"); 305 request->status = ATA_IDX_INB(ch, ATA_STATUS); 306 goto end_finished; 307 } 308 309 /* output data and return waiting for new interrupt */ 310 ata_pio_write(request, request->transfersize); 311 goto end_continue; 312 } 313 314 /* if data read command, return & wait for interrupt */ 315 if (request->flags & ATA_R_READ) 316 goto end_continue; 317 } 318 } 319 /* done with HW */ 320 goto end_finished; 321 322 /* ATA DMA data transfer commands */ 323 case ATA_R_DMA: 324 325 /* stop DMA engine and get status */ 326 if (ch->dma.stop) 327 request->dma->status = ch->dma.stop(request); 328 329 /* did we get error or data */ 330 if (request->status & ATA_S_ERROR) 331 request->error = ATA_IDX_INB(ch, ATA_ERROR); 332 else if (request->dma->status & ATA_BMSTAT_ERROR) 333 request->status |= ATA_S_ERROR; 334 else if (!(request->flags & ATA_R_TIMEOUT)) 335 request->donecount = request->bytecount; 336 337 /* Read back registers to the request struct. */ 338 if ((request->status & ATA_S_ERROR) || 339 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT))) { 340 ch->hw.tf_read(request); 341 } 342 343 /* release SG list etc */ 344 ch->dma.unload(request); 345 346 /* done with HW */ 347 goto end_finished; 348 349 /* ATAPI PIO commands */ 350 case ATA_R_ATAPI: 351 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 352 353 /* on timeouts we have no data or anything so just return */ 354 if (request->flags & ATA_R_TIMEOUT) 355 goto end_finished; 356 357 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 358 (request->status & ATA_S_DRQ)) { 359 360 case ATAPI_P_CMDOUT: 361 /* this seems to be needed for some (slow) devices */ 362 DELAY(10); 363 364 if (!(request->status & ATA_S_DRQ)) { 365 device_printf(request->parent, "command interrupt without DRQ\n"); 366 request->status = ATA_S_ERROR; 367 goto end_finished; 368 } 369 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 370 (request->flags & ATA_R_ATAPI16) ? 8 : 6); 371 /* return wait for interrupt */ 372 goto end_continue; 373 374 case ATAPI_P_WRITE: 375 if (request->flags & ATA_R_READ) { 376 request->status = ATA_S_ERROR; 377 device_printf(request->parent, 378 "%s trying to write on read buffer\n", 379 ata_cmd2str(request)); 380 goto end_finished; 381 } 382 ata_pio_write(request, length); 383 request->donecount += length; 384 385 /* set next transfer size according to HW capabilities */ 386 request->transfersize = min((request->bytecount-request->donecount), 387 request->transfersize); 388 /* return wait for interrupt */ 389 goto end_continue; 390 391 case ATAPI_P_READ: 392 if (request->flags & ATA_R_WRITE) { 393 request->status = ATA_S_ERROR; 394 device_printf(request->parent, 395 "%s trying to read on write buffer\n", 396 ata_cmd2str(request)); 397 goto end_finished; 398 } 399 ata_pio_read(request, length); 400 request->donecount += length; 401 402 /* set next transfer size according to HW capabilities */ 403 request->transfersize = min((request->bytecount-request->donecount), 404 request->transfersize); 405 /* return wait for interrupt */ 406 goto end_continue; 407 408 case ATAPI_P_DONEDRQ: 409 device_printf(request->parent, 410 "WARNING - %s DONEDRQ non conformant device\n", 411 ata_cmd2str(request)); 412 if (request->flags & ATA_R_READ) { 413 ata_pio_read(request, length); 414 request->donecount += length; 415 } 416 else if (request->flags & ATA_R_WRITE) { 417 ata_pio_write(request, length); 418 request->donecount += length; 419 } 420 else 421 request->status = ATA_S_ERROR; 422 /* FALLTHROUGH */ 423 424 case ATAPI_P_ABORT: 425 case ATAPI_P_DONE: 426 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 427 request->error = ATA_IDX_INB(ch, ATA_ERROR); 428 goto end_finished; 429 430 default: 431 device_printf(request->parent, "unknown transfer phase\n"); 432 request->status = ATA_S_ERROR; 433 } 434 435 /* done with HW */ 436 goto end_finished; 437 438 /* ATAPI DMA commands */ 439 case ATA_R_ATAPI|ATA_R_DMA: 440 441 /* stop DMA engine and get status */ 442 if (ch->dma.stop) 443 request->dma->status = ch->dma.stop(request); 444 445 /* did we get error or data */ 446 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 447 request->error = ATA_IDX_INB(ch, ATA_ERROR); 448 else if (request->dma->status & ATA_BMSTAT_ERROR) 449 request->status |= ATA_S_ERROR; 450 else if (!(request->flags & ATA_R_TIMEOUT)) 451 request->donecount = request->bytecount; 452 453 /* release SG list etc */ 454 ch->dma.unload(request); 455 456 /* done with HW */ 457 goto end_finished; 458 } 459 /* NOT REACHED */ 460 printf("ata_end_transaction OOPS!!\n"); 461 462 end_finished: 463 callout_stop(&request->callout); 464 return ATA_OP_FINISHED; 465 466 end_continue: 467 return ATA_OP_CONTINUES; 468 } 469 470 /* must be called with ATA channel locked and state_mtx held */ 471 void 472 ata_generic_reset(device_t dev) 473 { 474 struct ata_channel *ch = device_get_softc(dev); 475 476 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0; 477 u_int8_t err = 0, lsb = 0, msb = 0; 478 int mask = 0, timeout; 479 480 /* do we have any signs of ATA/ATAPI HW being present ? */ 481 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 482 DELAY(10); 483 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 484 if (((ostat0 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) && 485 ostat0 != 0xa5) { 486 stat0 = ATA_S_BUSY; 487 mask |= 0x01; 488 } 489 490 /* in some setups we dont want to test for a slave */ 491 if (!(ch->flags & ATA_NO_SLAVE)) { 492 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_SLAVE)); 493 DELAY(10); 494 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 495 if (((ostat1 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) && 496 ostat1 != 0xa5) { 497 stat1 = ATA_S_BUSY; 498 mask |= 0x02; 499 } 500 } 501 502 if (bootverbose) 503 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 504 mask, ostat0, ostat1); 505 506 /* if nothing showed up there is no need to get any further */ 507 /* XXX SOS is that too strong?, we just might loose devices here */ 508 ch->devices = 0; 509 if (!mask) 510 return; 511 512 /* reset (both) devices on this channel */ 513 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 514 DELAY(10); 515 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 516 ata_udelay(10000); 517 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 518 ata_udelay(100000); 519 ATA_IDX_INB(ch, ATA_ERROR); 520 521 /* wait for BUSY to go inactive */ 522 for (timeout = 0; timeout < 310; timeout++) { 523 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) { 524 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_MASTER)); 525 DELAY(10); 526 if (ch->flags & ATA_STATUS_IS_LONG) 527 stat0 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff; 528 else 529 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 530 err = ATA_IDX_INB(ch, ATA_ERROR); 531 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 532 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 533 if (bootverbose) 534 device_printf(dev, 535 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 536 stat0, err, lsb, msb); 537 if (stat0 == err && lsb == err && msb == err && 538 timeout > (stat0 & ATA_S_BUSY ? 100 : 10)) 539 mask &= ~0x01; 540 if (!(stat0 & ATA_S_BUSY)) { 541 if ((err & 0x7f) == ATA_E_ILI) { 542 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 543 ch->devices |= ATA_ATAPI_MASTER; 544 } 545 else if (lsb == 0 && msb == 0 && (stat0 & ATA_S_READY)) { 546 ch->devices |= ATA_ATA_MASTER; 547 } 548 } 549 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 550 stat0 |= ATA_S_BUSY; 551 } 552 } 553 } 554 555 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) && 556 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) { 557 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_SLAVE)); 558 DELAY(10); 559 if (ch->flags & ATA_STATUS_IS_LONG) 560 stat1 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff; 561 else 562 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 563 err = ATA_IDX_INB(ch, ATA_ERROR); 564 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 565 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 566 if (bootverbose) 567 device_printf(dev, 568 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 569 stat1, err, lsb, msb); 570 if (stat1 == err && lsb == err && msb == err && 571 timeout > (stat1 & ATA_S_BUSY ? 100 : 10)) 572 mask &= ~0x02; 573 if (!(stat1 & ATA_S_BUSY)) { 574 if ((err & 0x7f) == ATA_E_ILI) { 575 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 576 ch->devices |= ATA_ATAPI_SLAVE; 577 } 578 else if (lsb == 0 && msb == 0 && (stat1 & ATA_S_READY)) { 579 ch->devices |= ATA_ATA_SLAVE; 580 } 581 } 582 else if ((stat1 & 0x0f) && err == lsb && err == msb) { 583 stat1 |= ATA_S_BUSY; 584 } 585 } 586 } 587 588 if ((ch->flags & ATA_KNOWN_PRESENCE) == 0 && 589 timeout > ((mask == 0x03) ? 20 : 10)) { 590 if ((mask & 0x01) && stat0 == 0xff) 591 mask &= ~0x01; 592 if ((mask & 0x02) && stat1 == 0xff) 593 mask &= ~0x02; 594 } 595 if (((mask & 0x01) == 0 || !(stat0 & ATA_S_BUSY)) && 596 ((mask & 0x02) == 0 || !(stat1 & ATA_S_BUSY))) 597 break; 598 ata_udelay(100000); 599 } 600 601 if (bootverbose) 602 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%x\n", 603 stat0, stat1, ch->devices); 604 } 605 606 /* must be called with ATA channel locked and state_mtx held */ 607 int 608 ata_generic_status(device_t dev) 609 { 610 struct ata_channel *ch = device_get_softc(dev); 611 612 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 613 DELAY(100); 614 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 615 return 0; 616 } 617 return 1; 618 } 619 620 static int 621 ata_wait(struct ata_channel *ch, int unit, u_int8_t mask) 622 { 623 u_int8_t status; 624 int timeout = 0; 625 626 DELAY(1); 627 628 /* wait at max 1 second for device to get !BUSY */ 629 while (timeout < 1000000) { 630 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 631 632 /* if drive fails status, reselect the drive and try again */ 633 if (status == 0xff) { 634 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(unit)); 635 timeout += 1000; 636 DELAY(1000); 637 continue; 638 } 639 640 /* are we done ? */ 641 if (!(status & ATA_S_BUSY)) 642 break; 643 644 if (timeout > 1000) { 645 timeout += 1000; 646 DELAY(1000); 647 } 648 else { 649 timeout += 10; 650 DELAY(10); 651 } 652 } 653 if (timeout >= 1000000) 654 return -2; 655 if (!mask) 656 return (status & ATA_S_ERROR); 657 658 DELAY(1); 659 660 /* wait 50 msec for bits wanted */ 661 timeout = 5000; 662 while (timeout--) { 663 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 664 if ((status & mask) == mask) 665 return (status & ATA_S_ERROR); 666 DELAY(10); 667 } 668 return -3; 669 } 670 671 int 672 ata_generic_command(struct ata_request *request) 673 { 674 struct ata_channel *ch = device_get_softc(request->parent); 675 676 /* select device */ 677 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit)); 678 679 /* ready to issue command ? */ 680 if (ata_wait(ch, request->unit, 0) < 0) { 681 device_printf(request->parent, "timeout waiting to issue command\n"); 682 request->flags |= ATA_R_TIMEOUT; 683 return (-1); 684 } 685 686 /* enable interrupt */ 687 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 688 689 if (request->flags & ATA_R_ATAPI) { 690 int timeout = 5000; 691 int res; 692 693 /* issue packet command to controller */ 694 if (request->flags & ATA_R_DMA) { 695 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA); 696 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0); 697 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0); 698 } 699 else { 700 ATA_IDX_OUTB(ch, ATA_FEATURE, 0); 701 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize); 702 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8); 703 } 704 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD); 705 706 /* command interrupt device ? just return and wait for interrupt */ 707 if (request->flags & ATA_R_ATAPI_INTR) 708 return (0); 709 710 /* command processed ? */ 711 res = ata_wait(ch, request->unit, 0); 712 if (res != 0) { 713 if (res < 0) { 714 device_printf(request->parent, 715 "timeout waiting for PACKET command\n"); 716 request->flags |= ATA_R_TIMEOUT; 717 } 718 return (-1); 719 } 720 /* wait for ready to write ATAPI command block */ 721 while (timeout--) { 722 int reason = ATA_IDX_INB(ch, ATA_IREASON); 723 int status = ATA_IDX_INB(ch, ATA_STATUS); 724 725 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 726 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 727 break; 728 DELAY(20); 729 } 730 if (timeout <= 0) { 731 device_printf(request->parent, 732 "timeout waiting for ATAPI ready\n"); 733 request->flags |= ATA_R_TIMEOUT; 734 return (-1); 735 } 736 737 /* this seems to be needed for some (slow) devices */ 738 DELAY(10); 739 740 /* output command block */ 741 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 742 (request->flags & ATA_R_ATAPI16) ? 8 : 6); 743 } 744 else { 745 ch->hw.tf_write(request); 746 747 /* issue command to controller */ 748 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 749 } 750 return (0); 751 } 752 753 static void 754 ata_tf_read(struct ata_request *request) 755 { 756 struct ata_channel *ch = device_get_softc(request->parent); 757 758 if (request->flags & ATA_R_48BIT) { 759 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB); 760 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8); 761 request->u.ata.lba = 762 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) | 763 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) | 764 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40); 765 766 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 767 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT); 768 request->u.ata.lba |= 769 (ATA_IDX_INB(ch, ATA_SECTOR) | 770 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 771 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16)); 772 } 773 else { 774 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 775 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 776 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 777 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 778 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24); 779 } 780 } 781 782 static void 783 ata_tf_write(struct ata_request *request) 784 { 785 struct ata_channel *ch = device_get_softc(request->parent); 786 #ifndef ATA_CAM 787 struct ata_device *atadev = device_get_softc(request->dev); 788 #endif 789 790 if (request->flags & ATA_R_48BIT) { 791 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8); 792 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 793 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8); 794 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 795 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24); 796 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 797 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32); 798 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 799 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40); 800 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 801 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 802 } 803 else { 804 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 805 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 806 #ifndef ATA_CAM 807 if (atadev->flags & ATA_D_USE_CHS) { 808 int heads, sectors; 809 810 if (atadev->param.atavalid & ATA_FLAG_54_58) { 811 heads = atadev->param.current_heads; 812 sectors = atadev->param.current_sectors; 813 } 814 else { 815 heads = atadev->param.heads; 816 sectors = atadev->param.sectors; 817 } 818 819 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 820 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 821 (request->u.ata.lba / (sectors * heads))); 822 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 823 (request->u.ata.lba / (sectors * heads)) >> 8); 824 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 825 (((request->u.ata.lba% (sectors * heads)) / 826 sectors) & 0xf)); 827 } 828 else { 829 #endif 830 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 831 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 832 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 833 ATA_IDX_OUTB(ch, ATA_DRIVE, 834 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 835 ((request->u.ata.lba >> 24) & 0x0f)); 836 #ifndef ATA_CAM 837 } 838 #endif 839 } 840 } 841 842 static void 843 ata_pio_read(struct ata_request *request, int length) 844 { 845 struct ata_channel *ch = device_get_softc(request->parent); 846 uint8_t *addr; 847 int size = min(request->transfersize, length); 848 int resid; 849 uint8_t buf[2]; 850 851 addr = (uint8_t *)request->data + request->donecount; 852 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)) || 853 ((uintptr_t)addr % sizeof(int32_t))) { 854 ATA_IDX_INSW_STRM(ch, ATA_DATA, (void*)addr, size / sizeof(int16_t)); 855 if (size & 1) { 856 ATA_IDX_INSW_STRM(ch, ATA_DATA, (void*)buf, 1); 857 (addr + (size & ~1))[0] = buf[0]; 858 } 859 } else 860 ATA_IDX_INSL_STRM(ch, ATA_DATA, (void*)addr, size / sizeof(int32_t)); 861 862 if (request->transfersize < length) { 863 device_printf(request->parent, "WARNING - %s read data overrun %d>%d\n", 864 ata_cmd2str(request), length, request->transfersize); 865 for (resid = request->transfersize + (size & 1); resid < length; 866 resid += sizeof(int16_t)) 867 ATA_IDX_INW(ch, ATA_DATA); 868 } 869 } 870 871 static void 872 ata_pio_write(struct ata_request *request, int length) 873 { 874 struct ata_channel *ch = device_get_softc(request->parent); 875 uint8_t *addr; 876 int size = min(request->transfersize, length); 877 int resid; 878 uint8_t buf[2]; 879 880 addr = (uint8_t *)request->data + request->donecount; 881 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)) || 882 ((uintptr_t)addr % sizeof(int32_t))) { 883 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (void*)addr, size / sizeof(int16_t)); 884 if (size & 1) { 885 buf[0] = (addr + (size & ~1))[0]; 886 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (void*)buf, 1); 887 } 888 } else 889 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, (void*)addr, size / sizeof(int32_t)); 890 891 if (request->transfersize < length) { 892 device_printf(request->parent, "WARNING - %s write data underrun %d>%d\n", 893 ata_cmd2str(request), length, request->transfersize); 894 for (resid = request->transfersize + (size & 1); resid < length; 895 resid += sizeof(int16_t)) 896 ATA_IDX_OUTW(ch, ATA_DATA, 0); 897 } 898 } 899