1 /*- 2 * Copyright (c) 1998 - 2004 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_ata.h" 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/ata.h> 36 #include <sys/kernel.h> 37 #include <sys/conf.h> 38 #include <sys/bus.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/ata/ata-all.h> 45 46 /* prototypes */ 47 static int ata_transaction(struct ata_request *); 48 static void ata_interrupt(void *); 49 static void ata_reset(struct ata_channel *); 50 static int ata_wait(struct ata_device *, u_int8_t); 51 static int ata_command(struct ata_device *, u_int8_t, u_int64_t, u_int16_t, u_int16_t); 52 static void ata_pio_read(struct ata_request *, int); 53 static void ata_pio_write(struct ata_request *, int); 54 55 /* local vars */ 56 static int atadebug = 0; 57 58 /* 59 * low level ATA functions 60 */ 61 void 62 ata_generic_hw(struct ata_channel *ch) 63 { 64 ch->hw.reset = ata_reset; 65 ch->hw.transaction = ata_transaction; 66 ch->hw.interrupt = ata_interrupt; 67 } 68 69 /* must be called with ATA channel locked */ 70 static int 71 ata_transaction(struct ata_request *request) 72 { 73 /* safetybelt for HW that went away */ 74 if (!request->device->param || request->device->channel->flags&ATA_HWGONE) { 75 request->result = ENXIO; 76 return ATA_OP_FINISHED; 77 } 78 79 /* record the request as running */ 80 request->device->channel->running = request; 81 82 ATA_DEBUG_RQ(request, "transaction"); 83 84 /* disable ATAPI DMA writes if HW doesn't support it */ 85 if ((request->device->channel->flags & ATA_ATAPI_DMA_RO) && 86 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 87 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 88 request->flags &= ~ATA_R_DMA; 89 90 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 91 92 /* ATA PIO data transfer and control commands */ 93 default: 94 { 95 /* record command direction here as our request might be gone later */ 96 int write = (request->flags & ATA_R_WRITE); 97 98 /* issue command */ 99 if (ata_command(request->device, request->u.ata.command, 100 request->u.ata.lba, request->u.ata.count, 101 request->u.ata.feature)) { 102 ata_prtdev(request->device, "error issueing PIO command\n"); 103 request->result = EIO; 104 break; 105 } 106 107 /* if write command output the data */ 108 if (write) { 109 if (ata_wait(request->device, 110 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 111 ata_prtdev(request->device,"timeout waiting for write DRQ"); 112 request->result = EIO; 113 break; 114 } 115 ata_pio_write(request, request->transfersize); 116 } 117 } 118 119 /* return and wait for interrupt */ 120 return ATA_OP_CONTINUES; 121 122 /* ATA DMA data transfer commands */ 123 case ATA_R_DMA: 124 /* check sanity, setup SG list and DMA engine */ 125 if (request->device->channel->dma->load(request->device, 126 request->data, 127 request->bytecount, 128 request->flags & ATA_R_READ)) { 129 ata_prtdev(request->device, "setting up DMA failed\n"); 130 request->result = EIO; 131 break; 132 } 133 134 /* issue command */ 135 if (ata_command(request->device, request->u.ata.command, 136 request->u.ata.lba, request->u.ata.count, 137 request->u.ata.feature)) { 138 ata_prtdev(request->device, "error issuing DMA command\n"); 139 request->result = EIO; 140 break; 141 } 142 143 /* start DMA engine */ 144 if (request->device->channel->dma->start(request->device->channel)) { 145 ata_prtdev(request->device, "error starting DMA\n"); 146 request->result = EIO; 147 break; 148 } 149 150 /* return and wait for interrupt */ 151 return ATA_OP_CONTINUES; 152 153 /* ATAPI PIO commands */ 154 case ATA_R_ATAPI: 155 /* is this just a POLL DSC command ? */ 156 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 157 ATA_IDX_OUTB(request->device->channel, ATA_DRIVE, 158 ATA_D_IBM | request->device->unit); 159 DELAY(10); 160 if (!(ATA_IDX_INB(request->device->channel, ATA_ALTSTAT)&ATA_S_DSC)) 161 request->result = EBUSY; 162 break; 163 } 164 165 /* start ATAPI operation */ 166 if (ata_command(request->device, ATA_PACKET_CMD, 167 request->transfersize << 8, 0, 0)) { 168 ata_prtdev(request->device, "error issuing ATA PACKET command\n"); 169 request->result = EIO; 170 break; 171 } 172 173 /* command interrupt device ? just return and wait for interrupt */ 174 if ((request->device->param->config & ATA_DRQ_MASK) == ATA_DRQ_INTR) 175 return ATA_OP_CONTINUES; 176 177 /* wait for ready to write ATAPI command block */ 178 { 179 int timeout = 5000; /* might be less for fast devices */ 180 while (timeout--) { 181 int reason = ATA_IDX_INB(request->device->channel, ATA_IREASON); 182 int status = ATA_IDX_INB(request->device->channel, ATA_STATUS); 183 184 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 185 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 186 break; 187 DELAY(20); 188 } 189 if (timeout <= 0) { 190 ata_prtdev(request->device, 191 "timeout waiting for ATAPI ready\n"); 192 request->result = EIO; 193 break; 194 } 195 } 196 197 /* this seems to be needed for some (slow) devices */ 198 DELAY(10); 199 200 /* output actual command block */ 201 ATA_IDX_OUTSW_STRM(request->device->channel, ATA_DATA, 202 (int16_t *)request->u.atapi.ccb, 203 (request->device->param->config & ATA_PROTO_MASK) == 204 ATA_PROTO_ATAPI_12 ? 6 : 8); 205 206 /* return and wait for interrupt */ 207 return ATA_OP_CONTINUES; 208 209 case ATA_R_ATAPI|ATA_R_DMA: 210 /* is this just a POLL DSC command ? */ 211 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 212 ATA_IDX_OUTB(request->device->channel, ATA_DRIVE, 213 ATA_D_IBM | request->device->unit); 214 DELAY(10); 215 if (!(ATA_IDX_INB(request->device->channel, ATA_ALTSTAT)&ATA_S_DSC)) 216 request->result = EBUSY; 217 break; 218 } 219 220 /* check sanity, setup SG list and DMA engine */ 221 if (request->device->channel->dma->load(request->device, 222 request->data, 223 request->bytecount, 224 request->flags & ATA_R_READ)) { 225 ata_prtdev(request->device, "setting up DMA failed\n"); 226 request->result = EIO; 227 break; 228 } 229 230 /* start ATAPI operation */ 231 if (ata_command(request->device, ATA_PACKET_CMD, 0, 0, ATA_F_DMA)) { 232 ata_prtdev(request->device, "error issuing ATAPI packet command\n"); 233 request->result = EIO; 234 break; 235 } 236 237 /* wait for ready to write ATAPI command block */ 238 { 239 int timeout = 5000; /* might be less for fast devices */ 240 while (timeout--) { 241 int reason = ATA_IDX_INB(request->device->channel, ATA_IREASON); 242 int status = ATA_IDX_INB(request->device->channel, ATA_STATUS); 243 244 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 245 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 246 break; 247 DELAY(20); 248 } 249 if (timeout <= 0) { 250 ata_prtdev(request->device,"timeout waiting for ATAPI ready\n"); 251 request->result = EIO; 252 break; 253 } 254 } 255 256 /* this seems to be needed for some (slow) devices */ 257 DELAY(10); 258 259 /* output actual command block */ 260 ATA_IDX_OUTSW_STRM(request->device->channel, ATA_DATA, 261 (int16_t *)request->u.atapi.ccb, 262 (request->device->param->config & ATA_PROTO_MASK) == 263 ATA_PROTO_ATAPI_12 ? 6 : 8); 264 265 /* start DMA engine */ 266 if (request->device->channel->dma->start(request->device->channel)) { 267 request->result = EIO; 268 break; 269 } 270 271 /* return and wait for interrupt */ 272 return ATA_OP_CONTINUES; 273 } 274 275 /* request finish here */ 276 if (request->device->channel->dma->flags & ATA_DMA_ACTIVE) 277 request->device->channel->dma->unload(request->device->channel); 278 request->device->channel->running = NULL; 279 return ATA_OP_FINISHED; 280 } 281 282 static void 283 ata_interrupt(void *data) 284 { 285 struct ata_channel *ch = (struct ata_channel *)data; 286 struct ata_request *request = ch->running; 287 int length; 288 289 /* ignore this interrupt if there is no running request */ 290 if (!request) { 291 if (ATA_LOCK_CH(ch, ATA_CONTROL)) { 292 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 293 u_int8_t error = ATA_IDX_INB(ch, ATA_ERROR); 294 295 if (bootverbose) 296 ata_printf(ch, -1, 297 "spurious interrupt - status=0x%02x error=0x%02x\n", 298 status, error); 299 ATA_UNLOCK_CH(ch); 300 } 301 else { 302 if (bootverbose) 303 ata_printf(ch, -1, "spurious interrupt - channel busy\n"); 304 } 305 return; 306 } 307 308 ATA_DEBUG_RQ(request, "interrupt"); 309 310 /* ignore interrupt if device is busy */ 311 if (!(request->flags & ATA_R_TIMEOUT) && 312 ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 313 DELAY(100); 314 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DRQ)) 315 return; 316 } 317 318 ATA_DEBUG_RQ(request, "interrupt accepted"); 319 320 /* clear interrupt and get status */ 321 request->status = ATA_IDX_INB(ch, ATA_STATUS); 322 323 324 if (!(request->flags & ATA_R_TIMEOUT)) 325 request->flags |= ATA_R_INTR_SEEN; 326 327 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 328 329 /* ATA PIO data transfer and control commands */ 330 default: 331 332 /* on control commands read back registers to the request struct */ 333 if (request->flags & ATA_R_CONTROL) { 334 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 335 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 336 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 337 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16); 338 } 339 340 /* if we got an error we are done with the HW */ 341 if (request->status & ATA_S_ERROR) { 342 request->error = ATA_IDX_INB(ch, ATA_ERROR); 343 break; 344 } 345 346 /* are we moving data ? */ 347 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 348 349 /* if read data get it */ 350 if (request->flags & ATA_R_READ) 351 ata_pio_read(request, request->transfersize); 352 353 /* update how far we've gotten */ 354 request->donecount += request->transfersize; 355 356 /* do we need a scoop more ? */ 357 if (request->bytecount > request->donecount) { 358 359 /* set this transfer size according to HW capabilities */ 360 request->transfersize = 361 min((request->bytecount - request->donecount), 362 request->transfersize); 363 364 /* clear interrupt seen flag as we need to wait again */ 365 request->flags &= ~ATA_R_INTR_SEEN; 366 367 /* if data write command, output the data */ 368 if (request->flags & ATA_R_WRITE) { 369 370 /* if we get an error here we are done with the HW */ 371 if (ata_wait(request->device, 372 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { 373 ata_prtdev(request->device, 374 "timeout waiting for write DRQ"); 375 request->status = ATA_IDX_INB(ch, ATA_STATUS); 376 break; 377 } 378 379 /* output data and return waiting for new interrupt */ 380 ata_pio_write(request, request->transfersize); 381 return; 382 } 383 384 /* if data read command, return & wait for interrupt */ 385 if (request->flags & ATA_R_READ) 386 return; 387 } 388 } 389 /* done with HW */ 390 break; 391 392 /* ATA DMA data transfer commands */ 393 case ATA_R_DMA: 394 /* stop DMA engine and get status */ 395 request->dmastat = ch->dma->stop(ch); 396 397 /* did we get error or data */ 398 if (request->status & ATA_S_ERROR) 399 request->error = ATA_IDX_INB(ch, ATA_ERROR); 400 else if (request->dmastat & ATA_BMSTAT_ERROR) 401 request->status |= ATA_S_ERROR; 402 else 403 request->donecount = request->bytecount; 404 405 /* release SG list etc */ 406 ch->dma->unload(ch); 407 408 /* done with HW */ 409 break; 410 411 /* ATAPI PIO commands */ 412 case ATA_R_ATAPI: 413 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 414 415 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 416 (request->status & ATA_S_DRQ)) { 417 418 case ATAPI_P_CMDOUT: 419 /* this seems to be needed for some (slow) devices */ 420 DELAY(10); 421 422 if (!(request->status & ATA_S_DRQ)) { 423 ata_prtdev(request->device, "command interrupt without DRQ\n"); 424 request->status = ATA_S_ERROR; 425 break; 426 } 427 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 428 (request->device->param->config & 429 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); 430 /* return wait for interrupt */ 431 return; 432 433 case ATAPI_P_WRITE: 434 if (request->flags & ATA_R_READ) { 435 request->status = ATA_S_ERROR; 436 ata_prtdev(request->device, 437 "%s trying to write on read buffer\n", 438 ata_cmd2str(request)); 439 break; 440 } 441 ata_pio_write(request, length); 442 request->donecount += length; 443 444 /* set next transfer size according to HW capabilities */ 445 request->transfersize = min((request->bytecount-request->donecount), 446 request->transfersize); 447 /* return wait for interrupt */ 448 return; 449 450 case ATAPI_P_READ: 451 if (request->flags & ATA_R_WRITE) { 452 request->status = ATA_S_ERROR; 453 ata_prtdev(request->device, 454 "%s trying to read on write buffer\n", 455 ata_cmd2str(request)); 456 break; 457 } 458 ata_pio_read(request, length); 459 request->donecount += length; 460 461 /* set next transfer size according to HW capabilities */ 462 request->transfersize = min((request->bytecount-request->donecount), 463 request->transfersize); 464 /* return wait for interrupt */ 465 return; 466 467 case ATAPI_P_DONEDRQ: 468 ata_prtdev(request->device, 469 "WARNING - %s DONEDRQ non conformant device\n", 470 ata_cmd2str(request)); 471 if (request->flags & ATA_R_READ) { 472 ata_pio_read(request, length); 473 request->donecount += length; 474 } 475 else if (request->flags & ATA_R_WRITE) { 476 ata_pio_write(request, length); 477 request->donecount += length; 478 } 479 else 480 request->status = ATA_S_ERROR; 481 /* FALLTHROUGH */ 482 483 case ATAPI_P_ABORT: 484 case ATAPI_P_DONE: 485 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 486 request->error = ATA_IDX_INB(ch, ATA_ERROR); 487 break; 488 489 default: 490 ata_prtdev(request->device, "unknown transfer phase\n"); 491 request->status = ATA_S_ERROR; 492 } 493 494 /* done with HW */ 495 break; 496 497 /* ATAPI DMA commands */ 498 case ATA_R_ATAPI|ATA_R_DMA: 499 500 /* stop the engine and get engine status */ 501 request->dmastat = ch->dma->stop(ch); 502 503 /* did we get error or data */ 504 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 505 request->error = ATA_IDX_INB(ch, ATA_ERROR); 506 else if (request->dmastat & ATA_BMSTAT_ERROR) 507 request->status |= ATA_S_ERROR; 508 else 509 request->donecount = request->bytecount; 510 511 /* release SG list etc */ 512 ch->dma->unload(ch); 513 514 /* done with HW */ 515 break; 516 } 517 518 /* if we timed out the unlocking of the ATA channel is done later */ 519 if (!(request->flags & ATA_R_TIMEOUT)) { 520 ch->running = NULL; 521 ATA_UNLOCK_CH(ch); 522 ch->locking(ch, ATA_LF_UNLOCK); 523 } 524 525 /* schedule completition for this request */ 526 ata_finish(request); 527 } 528 529 /* must be called with ATA channel locked */ 530 static void 531 ata_reset(struct ata_channel *ch) 532 { 533 u_int8_t err, lsb, msb, ostat0, ostat1; 534 u_int8_t stat0 = 0, stat1 = 0; 535 int mask = 0, timeout; 536 537 /* do we have any signs of ATA/ATAPI HW being present ? */ 538 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 539 DELAY(10); 540 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 541 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 542 stat0 = ATA_S_BUSY; 543 mask |= 0x01; 544 } 545 546 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 547 DELAY(10); 548 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 549 550 /* in some setups we dont want to test for a slave */ 551 if (!(ch->flags & ATA_NO_SLAVE)) { 552 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 553 stat1 = ATA_S_BUSY; 554 mask |= 0x02; 555 } 556 } 557 558 /* if nothing showed up there is no need to get any further */ 559 /* SOS is that too strong?, we just might loose devices here XXX */ 560 ch->devices = 0; 561 if (!mask) 562 return; 563 564 if (bootverbose) 565 ata_printf(ch, -1, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 566 mask, ostat0, ostat1); 567 568 /* reset host end of channel (if supported) */ 569 if (ch->reset) 570 ch->reset(ch); 571 572 /* reset (both) devices on this channel */ 573 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 574 DELAY(10); 575 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS | ATA_A_RESET); 576 DELAY(10000); 577 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS); 578 DELAY(100000); 579 ATA_IDX_INB(ch, ATA_ERROR); 580 581 /* wait for BUSY to go inactive */ 582 for (timeout = 0; timeout < 310; timeout++) { 583 if (stat0 & ATA_S_BUSY) { 584 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 585 DELAY(10); 586 err = ATA_IDX_INB(ch, ATA_ERROR); 587 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 588 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 589 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 590 if (bootverbose) 591 ata_printf(ch, ATA_MASTER, 592 "stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 593 stat0, err, lsb, msb); 594 if (!(stat0 & ATA_S_BUSY)) { 595 if ((err & 0x7f) == ATA_E_ILI) { 596 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 597 ch->devices |= ATA_ATAPI_MASTER; 598 } 599 else if (stat0 & ATA_S_READY) { 600 ch->devices |= ATA_ATA_MASTER; 601 } 602 } 603 else if ((stat0 & 0x4f) && err == lsb && err == msb) { 604 stat0 |= ATA_S_BUSY; 605 } 606 } 607 } 608 if (!((mask == 0x03) && (stat0 & ATA_S_BUSY)) && (stat1 & ATA_S_BUSY)) { 609 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 610 DELAY(10); 611 err = ATA_IDX_INB(ch, ATA_ERROR); 612 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 613 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 614 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 615 if (bootverbose) 616 ata_printf(ch, ATA_SLAVE, 617 " stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 618 stat1, err, lsb, msb); 619 if (!(stat1 & ATA_S_BUSY)) { 620 if ((err & 0x7f) == ATA_E_ILI) { 621 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 622 ch->devices |= ATA_ATAPI_SLAVE; 623 } 624 else if (stat1 & ATA_S_READY) { 625 ch->devices |= ATA_ATA_SLAVE; 626 } 627 } 628 else if ((stat1 & 0x4f) && err == lsb && err == msb) { 629 stat1 |= ATA_S_BUSY; 630 } 631 } 632 } 633 if (mask == 0x01) /* wait for master only */ 634 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 20)) 635 break; 636 if (mask == 0x02) /* wait for slave only */ 637 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 20)) 638 break; 639 if (mask == 0x03) { /* wait for both master & slave */ 640 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 641 break; 642 if (stat0 == 0xff && timeout > 20) 643 mask &= ~0x01; 644 if (stat1 == 0xff && timeout > 20) 645 mask &= ~0x02; 646 } 647 DELAY(100000); 648 } 649 650 if (stat0 & ATA_S_BUSY) 651 mask &= ~0x01; 652 if (stat1 & ATA_S_BUSY) 653 mask &= ~0x02; 654 655 if (bootverbose) 656 ata_printf(ch, -1, 657 "reset tp2 mask=%02x stat0=%02x stat1=%02x devices=0x%b\n", 658 mask, stat0, stat1, ch->devices, 659 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 660 } 661 662 static int 663 ata_wait(struct ata_device *atadev, u_int8_t mask) 664 { 665 u_int8_t status; 666 int timeout = 0; 667 668 DELAY(1); 669 670 /* wait 5 seconds for device to get !BUSY */ 671 while (timeout < 5000000) { 672 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 673 674 /* if drive fails status, reselect the drive just to be sure */ 675 if (status == 0xff) { 676 ata_prtdev(atadev, "WARNING no status, reselecting device\n"); 677 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit); 678 DELAY(10); 679 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 680 if (status == 0xff) 681 return -1; 682 } 683 684 /* are we done ? */ 685 if (!(status & ATA_S_BUSY)) 686 break; 687 688 if (timeout > 1000) { 689 timeout += 1000; 690 DELAY(1000); 691 } 692 else { 693 timeout += 10; 694 DELAY(10); 695 } 696 } 697 if (timeout >= 5000000) 698 return -1; 699 if (!mask) 700 return (status & ATA_S_ERROR); 701 702 DELAY(1); 703 704 /* wait 50 msec for bits wanted */ 705 timeout = 5000; 706 while (timeout--) { 707 status = ATA_IDX_INB(atadev->channel, ATA_STATUS); 708 if ((status & mask) == mask) 709 return (status & ATA_S_ERROR); 710 DELAY (10); 711 } 712 return -1; 713 } 714 715 static int 716 ata_command(struct ata_device *atadev, u_int8_t command, 717 u_int64_t lba, u_int16_t count, u_int16_t feature) 718 { 719 if (atadebug) 720 ata_prtdev(atadev, "ata_command: addr=%04lx, command=%02x, " 721 "lba=%jd, count=%d, feature=%d\n", 722 rman_get_start(atadev->channel->r_io[ATA_DATA].res), 723 command, (intmax_t)lba, count, feature); 724 725 /* select device */ 726 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit); 727 728 /* ready to issue command ? */ 729 if (ata_wait(atadev, 0) < 0) { 730 ata_prtdev(atadev, "timeout sending command=%02x\n", command); 731 return -1; 732 } 733 734 /* enable interrupt */ 735 ATA_IDX_OUTB(atadev->channel, ATA_ALTSTAT, ATA_A_4BIT); 736 737 /* only use 48bit addressing if needed (avoid bugs and overhead) */ 738 if ((lba > 268435455 || count > 256) && atadev->param && 739 atadev->param->support.command2 & ATA_SUPPORT_ADDRESS48) { 740 741 /* translate command into 48bit version */ 742 switch (command) { 743 case ATA_READ: 744 command = ATA_READ48; break; 745 case ATA_READ_MUL: 746 command = ATA_READ_MUL48; break; 747 case ATA_READ_DMA: 748 command = ATA_READ_DMA48; break; 749 case ATA_READ_DMA_QUEUED: 750 command = ATA_READ_DMA_QUEUED48; break; 751 case ATA_WRITE: 752 command = ATA_WRITE48; break; 753 case ATA_WRITE_MUL: 754 command = ATA_WRITE_MUL48; break; 755 case ATA_WRITE_DMA: 756 command = ATA_WRITE_DMA48; break; 757 case ATA_WRITE_DMA_QUEUED: 758 command = ATA_WRITE_DMA_QUEUED48; break; 759 case ATA_FLUSHCACHE: 760 command = ATA_FLUSHCACHE48; break; 761 default: 762 ata_prtdev(atadev, "can't translate cmd to 48bit version\n"); 763 return -1; 764 } 765 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, (feature>>8) & 0xff); 766 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature & 0xff); 767 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, (count>>8) & 0xff); 768 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count & 0xff); 769 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, (lba>>24) & 0xff); 770 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff); 771 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>32) & 0xff); 772 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff); 773 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>40) & 0xff); 774 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff); 775 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_LBA | atadev->unit); 776 atadev->channel->flags |= ATA_48BIT_ACTIVE; 777 } 778 else { 779 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature); 780 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count); 781 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff); 782 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff); 783 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff); 784 if (atadev->flags & ATA_D_USE_CHS) 785 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, 786 ATA_D_IBM | atadev->unit | ((lba>>24) & 0xf)); 787 else 788 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, 789 ATA_D_IBM | ATA_D_LBA | atadev->unit|((lba>>24)&0xf)); 790 atadev->channel->flags &= ~ATA_48BIT_ACTIVE; 791 } 792 793 /* issue command to controller */ 794 ATA_IDX_OUTB(atadev->channel, ATA_CMD, command); 795 796 return 0; 797 } 798 799 static void 800 ata_pio_read(struct ata_request *request, int length) 801 { 802 int size = min(request->transfersize, length); 803 struct ata_channel *ch = request->device->channel; 804 int resid; 805 806 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 807 ATA_IDX_INSW_STRM(ch, ATA_DATA, 808 (void*)((uintptr_t)request->data+request->donecount), 809 size / sizeof(int16_t)); 810 else 811 ATA_IDX_INSL_STRM(ch, ATA_DATA, 812 (void*)((uintptr_t)request->data+request->donecount), 813 size / sizeof(int32_t)); 814 815 if (request->transfersize < length) { 816 ata_prtdev(request->device, "WARNING - %s read data overrun %d>%d\n", 817 ata_cmd2str(request), length, request->transfersize); 818 for (resid = request->transfersize; resid < length; 819 resid += sizeof(int16_t)) 820 ATA_IDX_INW(ch, ATA_DATA); 821 } 822 } 823 824 static void 825 ata_pio_write(struct ata_request *request, int length) 826 { 827 int size = min(request->transfersize, length); 828 struct ata_channel *ch = request->device->channel; 829 int resid; 830 831 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 832 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 833 (void*)((uintptr_t)request->data+request->donecount), 834 size / sizeof(int16_t)); 835 else 836 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 837 (void*)((uintptr_t)request->data+request->donecount), 838 size / sizeof(int32_t)); 839 840 if (request->transfersize < length) { 841 ata_prtdev(request->device, "WARNING - %s write data underrun %d>%d\n", 842 ata_cmd2str(request), length, request->transfersize); 843 for (resid = request->transfersize; resid < length; 844 resid += sizeof(int16_t)) 845 ATA_IDX_OUTW(ch, ATA_DATA, 0); 846 } 847 } 848