1 /*- 2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include "pci.h" 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bio.h> 35 #include <sys/malloc.h> 36 #include <sys/bus.h> 37 #include <sys/disk.h> 38 #include <sys/devicestat.h> 39 #include <vm/vm.h> 40 #include <vm/pmap.h> 41 #if NPCI > 0 42 #include <pci/pcivar.h> 43 #endif 44 #include <machine/bus.h> 45 #include <sys/rman.h> 46 #include <dev/ata/ata-all.h> 47 48 #if NPCI > 0 49 50 /* prototypes */ 51 static void cyrix_timing(struct ata_softc *, int, int); 52 static void promise_timing(struct ata_softc *, int, int); 53 static void hpt_timing(struct ata_softc *, int, int); 54 55 /* misc defines */ 56 #ifdef __alpha__ 57 #undef vtophys 58 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 59 #endif 60 61 void * 62 ata_dmaalloc(struct ata_softc *scp, int device) 63 { 64 void *dmatab; 65 66 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) { 67 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 68 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 69 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 70 free(dmatab, M_DEVBUF); 71 dmatab = NULL; 72 } 73 } 74 return dmatab; 75 } 76 77 void 78 ata_dmainit(struct ata_softc *scp, int device, 79 int apiomode, int wdmamode, int udmamode) 80 { 81 device_t parent = device_get_parent(scp->dev); 82 int devno = (scp->channel << 1) + ATA_DEV(device); 83 int error; 84 85 /* set our most pessimistic default mode */ 86 scp->mode[ATA_DEV(device)] = ATA_PIO; 87 88 if (!scp->r_bmio) 89 return; 90 91 /* if simplex controller, only allow DMA on primary channel */ 92 if (scp->channel == 1) { 93 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 94 ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 95 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 96 if (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 97 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 98 return; 99 } 100 } 101 102 /* DMA engine address alignment is usually 1 word (2 bytes) */ 103 scp->alignment = 0x1; 104 105 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) { 106 ata_printf(scp, device, 107 "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 108 udmamode = 2; 109 } 110 111 switch (scp->chiptype) { 112 113 case 0x244b8086: /* Intel ICH2 */ 114 if (udmamode >= 5) { 115 int32_t mask48, new48; 116 int16_t word54; 117 118 word54 = pci_read_config(parent, 0x54, 2); 119 if (word54 & (0x10 << devno)) { 120 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 121 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 122 if (bootverbose) 123 ata_printf(scp, device, 124 "%s setting UDMA5 on ICH2 chip\n", 125 (error) ? "failed" : "success"); 126 if (!error) { 127 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 128 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 129 pci_write_config(parent, 0x48, 130 (pci_read_config(parent, 0x48, 4) & 131 ~mask48) | new48, 4); 132 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 133 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 134 return; 135 } 136 } 137 } 138 /* make sure eventual ATA100 mode from the BIOS is disabled */ 139 pci_write_config(parent, 0x54, 140 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 141 /* FALLTHROUGH */ 142 143 case 0x24118086: /* Intel ICH */ 144 if (udmamode >= 4) { 145 int32_t mask48, new48; 146 int16_t word54; 147 148 word54 = pci_read_config(parent, 0x54, 2); 149 if (word54 & (0x10 << devno)) { 150 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 151 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 152 if (bootverbose) 153 ata_printf(scp, device, 154 "%s setting UDMA4 on ICH%s chip\n", 155 (error) ? "failed" : "success", 156 (scp->chiptype == 0x244b8086) ? "2" : ""); 157 if (!error) { 158 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 159 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 160 pci_write_config(parent, 0x48, 161 (pci_read_config(parent, 0x48, 4) & 162 ~mask48) | new48, 4); 163 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 164 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 165 return; 166 } 167 } 168 } 169 /* make sure eventual ATA66 mode from the BIOS is disabled */ 170 pci_write_config(parent, 0x54, 171 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 172 /* FALLTHROUGH */ 173 174 case 0x71118086: /* Intel PIIX4 */ 175 case 0x71998086: /* Intel PIIX4e */ 176 case 0x24218086: /* Intel ICH0 */ 177 if (udmamode >= 2) { 178 int32_t mask48, new48; 179 180 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 181 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 182 if (bootverbose) 183 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 184 (error) ? "failed" : "success", 185 (scp->chiptype == 0x244b8086) ? "ICH2" : 186 (scp->chiptype == 0x24118086) ? "ICH" : 187 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 188 if (!error) { 189 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 190 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 191 pci_write_config(parent, 0x48, 192 (pci_read_config(parent, 0x48, 4) & 193 ~mask48) | new48, 4); 194 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 195 return; 196 } 197 } 198 /* make sure eventual ATA33 mode from the BIOS is disabled */ 199 pci_write_config(parent, 0x48, 200 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 201 /* FALLTHROUGH */ 202 203 case 0x70108086: /* Intel PIIX3 */ 204 if (wdmamode >= 2 && apiomode >= 4) { 205 int32_t mask40, new40, mask44, new44; 206 207 /* if SITRE not set doit for both channels */ 208 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 209 new40 = pci_read_config(parent, 0x40, 4); 210 new44 = pci_read_config(parent, 0x44, 4); 211 if (!(new40 & 0x00004000)) { 212 new44 &= ~0x0000000f; 213 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 214 } 215 if (!(new40 & 0x40000000)) { 216 new44 &= ~0x000000f0; 217 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 218 } 219 new40 |= 0x40004000; 220 pci_write_config(parent, 0x40, new40, 4); 221 pci_write_config(parent, 0x44, new44, 4); 222 } 223 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 224 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 225 if (bootverbose) 226 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 227 (error) ? "failed" : "success", 228 (scp->chiptype == 0x244b8086) ? "ICH2" : 229 (scp->chiptype == 0x24118086) ? "ICH" : 230 (scp->chiptype == 0x24218086) ? "ICH0" : 231 (scp->chiptype == 0x70108086) ? "PIIX3":"PIIX4"); 232 if (!error) { 233 if (device == ATA_MASTER) { 234 mask40 = 0x0000330f; 235 new40 = 0x00002307; 236 mask44 = 0; 237 new44 = 0; 238 } 239 else { 240 mask40 = 0x000000f0; 241 new40 = 0x00000070; 242 mask44 = 0x0000000f; 243 new44 = 0x0000000b; 244 } 245 if (scp->channel) { 246 mask40 <<= 16; 247 new40 <<= 16; 248 mask44 <<= 4; 249 new44 <<= 4; 250 } 251 pci_write_config(parent, 0x40, 252 (pci_read_config(parent, 0x40, 4) & ~mask40)| 253 new40, 4); 254 pci_write_config(parent, 0x44, 255 (pci_read_config(parent, 0x44, 4) & ~mask44)| 256 new44, 4); 257 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 258 return; 259 } 260 } 261 /* we could set PIO mode timings, but we assume the BIOS did that */ 262 break; 263 264 case 0x12308086: /* Intel PIIX */ 265 if (wdmamode >= 2 && apiomode >= 4) { 266 int32_t word40; 267 268 word40 = pci_read_config(parent, 0x40, 4); 269 word40 >>= scp->channel * 16; 270 271 /* Check for timing config usable for DMA on controller */ 272 if (!((word40 & 0x3300) == 0x2300 && 273 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 274 break; 275 276 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 277 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 278 if (bootverbose) 279 ata_printf(scp, device, 280 "%s setting WDMA2 on PIIX chip\n", 281 (error) ? "failed" : "success"); 282 if (!error) { 283 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 284 return; 285 } 286 } 287 break; 288 289 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 290 /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 291 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 292 ata_printf(scp, device, 293 "Aladdin: two atapi devices on this channel, no DMA\n"); 294 break; 295 } 296 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 297 int32_t word54 = pci_read_config(parent, 0x54, 4); 298 299 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 300 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 301 if (bootverbose) 302 ata_printf(scp, device, 303 "%s setting UDMA2 on Aladdin chip\n", 304 (error) ? "failed" : "success"); 305 if (!error) { 306 word54 &= ~(0x000f000f << (devno << 2)); 307 word54 |= (0x000a0005 << (devno << 2)); 308 pci_write_config(parent, 0x54, word54, 4); 309 pci_write_config(parent, 0x53, 310 pci_read_config(parent, 0x53, 1) | 0x03, 1); 311 scp->flags |= ATA_ATAPI_DMA_RO; 312 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 313 return; 314 } 315 } 316 317 /* make sure eventual UDMA mode from the BIOS is disabled */ 318 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 319 ~(0x0008 << (devno << 2)), 2); 320 321 if (wdmamode >= 2 && apiomode >= 4) { 322 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 323 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 324 if (bootverbose) 325 ata_printf(scp, device, 326 "%s setting WDMA2 on Aladdin chip\n", 327 (error) ? "failed" : "success"); 328 if (!error) { 329 pci_write_config(parent, 0x53, 330 pci_read_config(parent, 0x53, 1) | 0x03, 1); 331 scp->flags |= ATA_ATAPI_DMA_RO; 332 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 333 return; 334 } 335 } 336 pci_write_config(parent, 0x53, 337 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 338 /* we could set PIO mode timings, but we assume the BIOS did that */ 339 break; 340 341 case 0x74091022: /* AMD 756 */ 342 if (udmamode >= 4) { 343 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 344 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 345 if (bootverbose) 346 ata_printf(scp, device, 347 "%s setting UDMA4 on AMD chip\n", 348 (error) ? "failed" : "success"); 349 if (!error) { 350 pci_write_config(parent, 0x53 - devno, 0xc3, 1); 351 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 352 return; 353 } 354 } 355 goto via_82c586; 356 357 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 358 if (ata_find_dev(parent, 0x06861106, 0x40)) { /* 82C686b */ 359 if (udmamode >= 5) { 360 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 361 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 362 if (bootverbose) 363 ata_printf(scp, device, 364 "%s setting UDMA5 on VIA chip\n", 365 (error) ? "failed" : "success"); 366 if (!error) { 367 pci_write_config(parent, 0x53 - devno, 0xf0, 1); 368 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 369 return; 370 } 371 } 372 if (udmamode >= 4) { 373 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 374 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 375 if (bootverbose) 376 ata_printf(scp, device, 377 "%s setting UDMA4 on VIA chip\n", 378 (error) ? "failed" : "success"); 379 if (!error) { 380 pci_write_config(parent, 0x53 - devno, 0xf1, 1); 381 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 382 return; 383 } 384 } 385 if (udmamode >= 2) { 386 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 387 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 388 if (bootverbose) 389 ata_printf(scp, device, 390 "%s setting UDMA2 on VIA chip\n", 391 (error) ? "failed" : "success"); 392 if (!error) { 393 pci_write_config(parent, 0x53 - devno, 0xf4, 1); 394 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 395 return; 396 } 397 } 398 } 399 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 400 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 401 if (udmamode >= 4) { 402 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 403 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 404 if (bootverbose) 405 ata_printf(scp, device, 406 "%s setting UDMA4 on VIA chip\n", 407 (error) ? "failed" : "success"); 408 if (!error) { 409 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 410 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 411 return; 412 } 413 } 414 if (udmamode >= 2) { 415 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 416 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 417 if (bootverbose) 418 ata_printf(scp, device, 419 "%s setting UDMA2 on VIA chip\n", 420 (error) ? "failed" : "success"); 421 if (!error) { 422 pci_write_config(parent, 0x53 - devno, 0xea, 1); 423 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 424 return; 425 } 426 } 427 } 428 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 429 ata_find_dev(parent, 0x05861106, 0x02)) { /* 82C586b */ 430 via_82c586: 431 if (udmamode >= 2) { 432 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 433 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 434 if (bootverbose) 435 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 436 (error) ? "failed" : "success", 437 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 438 if (!error) { 439 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 440 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 441 return; 442 } 443 } 444 } 445 if (wdmamode >= 2 && apiomode >= 4) { 446 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 447 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 448 if (bootverbose) 449 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 450 (error) ? "failed" : "success", 451 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 452 if (!error) { 453 pci_write_config(parent, 0x53 - devno, 0x82, 1); 454 pci_write_config(parent, 0x4b - devno, 0x31, 1); 455 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 456 return; 457 } 458 } 459 /* we could set PIO mode timings, but we assume the BIOS did that */ 460 break; 461 462 case 0x55131039: /* SiS 5591 */ 463 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 464 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 465 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 466 if (bootverbose) 467 ata_printf(scp, device, 468 "%s setting UDMA2 on SiS chip\n", 469 (error) ? "failed" : "success"); 470 if (!error) { 471 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 472 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 473 return; 474 } 475 } 476 if (wdmamode >=2 && apiomode >= 4) { 477 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 478 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 479 if (bootverbose) 480 ata_printf(scp, device, 481 "%s setting WDMA2 on SiS chip\n", 482 (error) ? "failed" : "success"); 483 if (!error) { 484 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 485 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 486 return; 487 } 488 } 489 /* we could set PIO mode timings, but we assume the BIOS did that */ 490 break; 491 492 case 0x06491095: /* CMD 649 ATA100 controller */ 493 if (udmamode >= 5) { 494 u_int8_t umode; 495 496 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 497 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 498 if (bootverbose) 499 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 500 (error) ? "failed" : "success"); 501 if (!error) { 502 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 503 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 504 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 505 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 506 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 507 return; 508 } 509 } 510 /* FALLTHROUGH */ 511 512 case 0x06481095: /* CMD 648 ATA66 controller */ 513 if (udmamode >= 4) { 514 u_int8_t umode; 515 516 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 517 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 518 if (bootverbose) 519 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 520 (error) ? "failed" : "success"); 521 if (!error) { 522 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 523 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 524 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 525 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 526 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 527 return; 528 } 529 } 530 if (udmamode >= 2) { 531 u_int8_t umode; 532 533 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 534 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 535 if (bootverbose) 536 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 537 (error) ? "failed" : "success"); 538 if (!error) { 539 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 540 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 541 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 542 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 543 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 544 return; 545 } 546 } 547 /* make sure eventual UDMA mode from the BIOS is disabled */ 548 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 549 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 550 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 551 /* FALLTHROUGH */ 552 553 case 0x06461095: /* CMD 646 ATA controller */ 554 if (wdmamode >= 2 && apiomode >= 4) { 555 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 556 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 557 if (bootverbose) 558 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 559 error ? "failed" : "success"); 560 if (!error) { 561 int32_t offset = (devno < 3) ? (devno << 1) : 7; 562 563 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 564 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 565 return; 566 } 567 } 568 /* we could set PIO mode timings, but we assume the BIOS did that */ 569 break; 570 571 case 0xc6931080: /* Cypress 82c693 ATA controller */ 572 if (wdmamode >= 2 && apiomode >= 4) { 573 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 574 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 575 if (bootverbose) 576 ata_printf(scp, device, 577 "%s setting WDMA2 on Cypress chip\n", 578 error ? "failed" : "success"); 579 if (!error) { 580 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 581 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 582 return; 583 } 584 } 585 /* we could set PIO mode timings, but we assume the BIOS did that */ 586 break; 587 588 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 589 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 590 if (udmamode >= 2) { 591 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 592 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 593 if (bootverbose) 594 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 595 (error) ? "failed" : "success"); 596 if (!error) { 597 cyrix_timing(scp, devno, ATA_UDMA2); 598 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 599 return; 600 } 601 } 602 if (wdmamode >= 2 && apiomode >= 4) { 603 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 604 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 605 if (bootverbose) 606 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 607 (error) ? "failed" : "success"); 608 if (!error) { 609 cyrix_timing(scp, devno, ATA_WDMA2); 610 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 611 return; 612 } 613 } 614 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 615 ata_pio2mode(apiomode), ATA_C_F_SETXFER, 616 ATA_WAIT_READY); 617 if (bootverbose) 618 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 619 (error) ? "failed" : "success", 620 ata_mode2str(ata_pio2mode(apiomode))); 621 cyrix_timing(scp, devno, ata_pio2mode(apiomode)); 622 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 623 return; 624 625 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 626 if (udmamode >= 2) { 627 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 628 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 629 if (bootverbose) 630 ata_printf(scp, device, 631 "%s setting UDMA2 on ServerWorks chip\n", 632 (error) ? "failed" : "success"); 633 if (!error) { 634 u_int16_t reg56; 635 636 pci_write_config(parent, 0x54, 637 pci_read_config(parent, 0x54, 1) | 638 (0x01 << devno), 1); 639 reg56 = pci_read_config(parent, 0x56, 2); 640 reg56 &= ~(0xf << (devno * 4)); 641 reg56 |= (0x2 << (devno * 4)); 642 pci_write_config(parent, 0x56, reg56, 2); 643 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 644 return; 645 } 646 } 647 if (wdmamode >= 2 && apiomode >= 4) { 648 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 649 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 650 if (bootverbose) 651 ata_printf(scp, device, 652 "%s setting WDMA2 on ServerWorks chip\n", 653 (error) ? "failed" : "success"); 654 if (!error) { 655 int offset = (scp->channel * 2) + (device == ATA_MASTER); 656 int word44 = pci_read_config(parent, 0x44, 4); 657 658 pci_write_config(parent, 0x54, 659 pci_read_config(parent, 0x54, 1) & 660 ~(0x01 << devno), 1); 661 word44 &= ~(0xff << (offset << 8)); 662 word44 |= (0x20 << (offset << 8)); 663 pci_write_config(parent, 0x44, 0x20, 4); 664 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 665 return; 666 } 667 } 668 /* we could set PIO mode timings, but we assume the BIOS did that */ 669 break; 670 671 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 672 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 673 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 674 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 675 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 676 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 677 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 678 break; 679 680 if (udmamode >= 5 && 681 (scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 682 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 683 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 684 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 685 if (bootverbose) 686 ata_printf(scp, device, 687 "%s setting UDMA5 on Promise chip\n", 688 (error) ? "failed" : "success"); 689 if (!error) { 690 promise_timing(scp, devno, ATA_UDMA5); 691 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 692 return; 693 } 694 } 695 if (udmamode >= 4 && (scp->chiptype == 0x4d38105a || 696 scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 697 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 698 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 699 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 700 if (bootverbose) 701 ata_printf(scp, device, 702 "%s setting UDMA4 on Promise chip\n", 703 (error) ? "failed" : "success"); 704 if (!error) { 705 promise_timing(scp, devno, ATA_UDMA4); 706 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 707 return; 708 } 709 } 710 if (udmamode >= 2) { 711 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 712 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 713 if (bootverbose) 714 ata_printf(scp, device, 715 "%s setting UDMA2 on Promise chip\n", 716 (error) ? "failed" : "success"); 717 if (!error) { 718 promise_timing(scp, devno, ATA_UDMA2); 719 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 720 return; 721 } 722 } 723 if (wdmamode >= 2 && apiomode >= 4) { 724 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 725 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 726 if (bootverbose) 727 ata_printf(scp, device, 728 "%s setting WDMA2 on Promise chip\n", 729 (error) ? "failed" : "success"); 730 if (!error) { 731 promise_timing(scp, devno, ATA_WDMA2); 732 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 733 return; 734 } 735 } 736 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 737 ata_pio2mode(apiomode), 738 ATA_C_F_SETXFER, ATA_WAIT_READY); 739 if (bootverbose) 740 ata_printf(scp, device, 741 "%s setting PIO%d on Promise chip\n", 742 (error) ? "failed" : "success", 743 (apiomode >= 0) ? apiomode : 0); 744 promise_timing(scp, devno, ata_pio2mode(apiomode)); 745 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 746 return; 747 748 case 0x00041103: /* HighPoint HPT366/368/370 controllers */ 749 /* no ATAPI devices for now */ 750 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 751 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 752 break; 753 754 if (udmamode >=5 && pci_get_revid(parent) >= 0x03 && 755 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 756 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 757 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 758 if (bootverbose) 759 ata_printf(scp, device, 760 "%s setting UDMA5 on HighPoint chip\n", 761 (error) ? "failed" : "success"); 762 if (!error) { 763 hpt_timing(scp, devno, ATA_UDMA5); 764 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 765 return; 766 } 767 } 768 if (udmamode >=4 && 769 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 770 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 771 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 772 if (bootverbose) 773 ata_printf(scp, device, 774 "%s setting UDMA4 on HighPoint chip\n", 775 (error) ? "failed" : "success"); 776 if (!error) { 777 hpt_timing(scp, devno, ATA_UDMA4); 778 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 779 return; 780 } 781 } 782 if (udmamode >= 2) { 783 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 784 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 785 if (bootverbose) 786 ata_printf(scp, device, 787 "%s setting UDMA2 on HighPoint chip\n", 788 (error) ? "failed" : "success"); 789 if (!error) { 790 hpt_timing(scp, devno, ATA_UDMA2); 791 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 792 return; 793 } 794 } 795 if (wdmamode >= 2 && apiomode >= 4) { 796 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 797 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 798 if (bootverbose) 799 ata_printf(scp, device, 800 "%s setting WDMA2 on HighPoint chip\n", 801 (error) ? "failed" : "success"); 802 if (!error) { 803 hpt_timing(scp, devno, ATA_WDMA2); 804 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 805 return; 806 } 807 } 808 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 809 ata_pio2mode(apiomode), 810 ATA_C_F_SETXFER, ATA_WAIT_READY); 811 if (bootverbose) 812 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 813 (error) ? "failed" : "success", 814 (apiomode >= 0) ? apiomode : 0); 815 hpt_timing(scp, devno, ata_pio2mode(apiomode)); 816 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 817 return; 818 819 default: /* unknown controller chip */ 820 /* better not try generic DMA on ATAPI devices it almost never works */ 821 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 822 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 823 break; 824 825 /* if controller says its setup for DMA take the easy way out */ 826 /* the downside is we dont know what DMA mode we are in */ 827 if ((udmamode >= 0 || wdmamode > 1) && 828 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 829 ((device==ATA_MASTER) ? 830 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 831 scp->mode[ATA_DEV(device)] = ATA_DMA; 832 return; 833 } 834 835 /* well, we have no support for this, but try anyways */ 836 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) { 837 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 838 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 839 if (bootverbose) 840 ata_printf(scp, device, 841 "%s setting WDMA2 on generic chip\n", 842 (error) ? "failed" : "success"); 843 if (!error) { 844 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 845 return; 846 } 847 } 848 } 849 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 850 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 851 if (bootverbose) 852 ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 853 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 854 if (!error) 855 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 856 else { 857 if (bootverbose) 858 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 859 scp->mode[ATA_DEV(device)] = ATA_PIO; 860 } 861 } 862 863 int 864 ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 865 caddr_t data, int32_t count) 866 { 867 u_int32_t dma_count, dma_base; 868 int i = 0; 869 870 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 871 ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 872 return -1; 873 } 874 875 if (!count) { 876 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 877 return -1; 878 } 879 880 dma_base = vtophys(data); 881 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 882 data += dma_count; 883 count -= dma_count; 884 885 while (count) { 886 dmatab[i].base = dma_base; 887 dmatab[i].count = (dma_count & 0xffff); 888 i++; 889 if (i >= ATA_DMA_ENTRIES) { 890 ata_printf(scp, device, "too many segments in DMA table\n"); 891 return -1; 892 } 893 dma_base = vtophys(data); 894 dma_count = min(count, PAGE_SIZE); 895 data += min(count, PAGE_SIZE); 896 count -= min(count, PAGE_SIZE); 897 } 898 dmatab[i].base = dma_base; 899 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 900 return 0; 901 } 902 903 void 904 ata_dmastart(struct ata_softc *scp, int device, 905 struct ata_dmaentry *dmatab, int dir) 906 { 907 scp->flags |= ATA_DMA_ACTIVE; 908 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab)); 909 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 910 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 911 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) | 912 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 913 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 914 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 915 } 916 917 int 918 ata_dmadone(struct ata_softc *scp) 919 { 920 int error; 921 922 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 923 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 924 scp->flags &= ~ATA_DMA_ACTIVE; 925 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT); 926 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 927 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 928 return error & ATA_BMSTAT_MASK; 929 } 930 931 int 932 ata_dmastatus(struct ata_softc *scp) 933 { 934 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 935 } 936 937 static void 938 cyrix_timing(struct ata_softc *scp, int devno, int mode) 939 { 940 u_int32_t reg20 = 0x0000e132; 941 u_int32_t reg24 = 0x00017771; 942 943 switch (mode) { 944 case ATA_PIO0: reg20 = 0x0000e132; break; 945 case ATA_PIO1: reg20 = 0x00018121; break; 946 case ATA_PIO2: reg20 = 0x00024020; break; 947 case ATA_PIO3: reg20 = 0x00032010; break; 948 case ATA_PIO4: reg20 = 0x00040010; break; 949 case ATA_WDMA2: reg24 = 0x00002020; break; 950 case ATA_UDMA2: reg24 = 0x00911030; break; 951 } 952 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20); 953 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24); 954 } 955 956 static void 957 promise_timing(struct ata_softc *scp, int devno, int mode) 958 { 959 u_int32_t timing = 0; 960 struct promise_timing { 961 u_int8_t pa:4; 962 u_int8_t prefetch:1; 963 u_int8_t iordy:1; 964 u_int8_t errdy:1; 965 u_int8_t syncin:1; 966 u_int8_t pb:5; 967 u_int8_t mb:3; 968 u_int8_t mc:4; 969 u_int8_t dmaw:1; 970 u_int8_t dmar:1; 971 u_int8_t iordyp:1; 972 u_int8_t dmarqp:1; 973 u_int8_t reserved:8; 974 } *t = (struct promise_timing*)&timing; 975 976 t->iordy = 1; t->iordyp = 1; 977 if (mode >= ATA_DMA) { 978 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 979 } 980 981 switch (scp->chiptype) { 982 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 983 switch (mode) { 984 default: 985 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 986 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 987 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 988 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 989 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 990 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 991 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 992 } 993 break; 994 995 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 996 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 997 case 0x0d30105a: /* Promise OEM ATA 100 */ 998 switch (mode) { 999 default: 1000 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1001 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1002 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1003 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1004 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1005 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1006 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1007 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1008 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1009 } 1010 break; 1011 } 1012 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 1013 } 1014 1015 static void 1016 hpt_timing(struct ata_softc *scp, int devno, int mode) 1017 { 1018 device_t parent = device_get_parent(scp->dev); 1019 u_int32_t timing; 1020 1021 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 1022 switch (mode) { 1023 case ATA_PIO0: timing = 0x06914e57; break; 1024 case ATA_PIO1: timing = 0x06914e43; break; 1025 case ATA_PIO2: timing = 0x06514e33; break; 1026 case ATA_PIO3: timing = 0x06514e22; break; 1027 case ATA_PIO4: timing = 0x06514e21; break; 1028 case ATA_WDMA2: timing = 0x26514e21; break; 1029 case ATA_UDMA2: timing = 0x16494e31; break; 1030 case ATA_UDMA4: timing = 0x16454e31; break; 1031 case ATA_UDMA5: timing = 0x16454e31; break; 1032 default: timing = 0x06514e57; 1033 } 1034 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1035 pci_write_config(parent, 0x5b, 0x22, 1); 1036 } 1037 else { /* HPT36[68] */ 1038 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1039 case 0x85: /* 25Mhz */ 1040 switch (mode) { 1041 case ATA_PIO0: timing = 0xc0d08585; break; 1042 case ATA_PIO1: timing = 0xc0d08572; break; 1043 case ATA_PIO2: timing = 0xc0ca8542; break; 1044 case ATA_PIO3: timing = 0xc0ca8532; break; 1045 case ATA_PIO4: timing = 0xc0ca8521; break; 1046 case ATA_WDMA2: timing = 0xa0ca8521; break; 1047 case ATA_UDMA2: timing = 0x90cf8521; break; 1048 case ATA_UDMA4: timing = 0x90c98521; break; 1049 default: timing = 0x01208585; 1050 } 1051 break; 1052 default: 1053 case 0xa7: /* 33MHz */ 1054 switch (mode) { 1055 case ATA_PIO0: timing = 0xc0d0a7aa; break; 1056 case ATA_PIO1: timing = 0xc0d0a7a3; break; 1057 case ATA_PIO2: timing = 0xc0d0a753; break; 1058 case ATA_PIO3: timing = 0xc0c8a742; break; 1059 case ATA_PIO4: timing = 0xc0c8a731; break; 1060 case ATA_WDMA2: timing = 0xa0c8a731; break; 1061 case ATA_UDMA2: timing = 0x90caa731; break; 1062 case ATA_UDMA4: timing = 0x90c9a731; break; 1063 default: timing = 0x0120a7a7; 1064 } 1065 break; 1066 case 0xd9: /* 40Mhz */ 1067 switch (mode) { 1068 case ATA_PIO0: timing = 0xc018d9d9; break; 1069 case ATA_PIO1: timing = 0xc010d9c7; break; 1070 case ATA_PIO2: timing = 0xc010d997; break; 1071 case ATA_PIO3: timing = 0xc010d974; break; 1072 case ATA_PIO4: timing = 0xc008d963; break; 1073 case ATA_WDMA2: timing = 0xa008d943; break; 1074 case ATA_UDMA2: timing = 0x900bd943; break; 1075 case ATA_UDMA4: timing = 0x900fd943; break; 1076 default: timing = 0x0120d9d9; 1077 } 1078 } 1079 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 1080 } 1081 } 1082 1083 #else /* NPCI > 0 */ 1084 1085 void * 1086 ata_dmaalloc(struct ata_softc *scp, int device) 1087 { 1088 return 0; 1089 } 1090 1091 void 1092 ata_dmainit(struct ata_softc *scp, int device, 1093 int piomode, int wdmamode, int udmamode) 1094 { 1095 } 1096 1097 int 1098 ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 1099 caddr_t data, int32_t count) 1100 { 1101 return -1; 1102 } 1103 1104 void 1105 ata_dmastart(struct ata_softc *scp, int device, 1106 struct ata_dmaentry *dmatab, int dir) 1107 { 1108 } 1109 1110 int 1111 ata_dmadone(struct ata_softc *scp) 1112 { 1113 return -1; 1114 } 1115 1116 int 1117 ata_dmastatus(struct ata_softc *scp) 1118 { 1119 return -1; 1120 } 1121 1122 #endif /* NPCI > 0 */ 1123