xref: /freebsd/sys/dev/ata/ata-dma.c (revision eacee0ff7ec955b32e09515246bd97b6edcd2b0f)
1 /*-
2  * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer,
10  *    without modification, immediately at the beginning of the file.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. The name of the author may not be used to endorse or promote products
15  *    derived from this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  *
28  * $FreeBSD$
29  */
30 
31 #include "pci.h"
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/ata.h>
35 #include <sys/bio.h>
36 #include <sys/malloc.h>
37 #include <sys/bus.h>
38 #include <sys/disk.h>
39 #include <sys/devicestat.h>
40 #include <vm/vm.h>
41 #include <vm/pmap.h>
42 #include <pci/pcivar.h>
43 #include <machine/bus.h>
44 #include <sys/rman.h>
45 #include <dev/ata/ata-all.h>
46 
47 /* prototypes */
48 static void cyrix_timing(struct ata_channel *, int, int);
49 static void promise_timing(struct ata_channel *, int, int);
50 static void hpt_timing(struct ata_channel *, int, int);
51 
52 /* misc defines */
53 #ifdef __alpha__
54 #undef vtophys
55 #define vtophys(va)	alpha_XXX_dmamap((vm_offset_t)va)
56 #endif
57 #define ATAPI_DEVICE(ch, device) \
58 	((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || \
59 	 (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE))
60 
61 void *
62 ata_dmaalloc(struct ata_channel *ch, int device)
63 {
64     void *dmatab;
65 
66     if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) {
67 	if (((uintptr_t)dmatab >> PAGE_SHIFT) ^
68 	    (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) {
69 	    ata_printf(ch, device, "dmatab crosses page boundary, no DMA\n");
70 	    free(dmatab, M_DEVBUF);
71 	    dmatab = NULL;
72 	}
73     }
74     return dmatab;
75 }
76 
77 void
78 ata_dmainit(struct ata_channel *ch, int device,
79 	    int apiomode, int wdmamode, int udmamode)
80 {
81     struct ata_device *atadev = &ch->device[ATA_DEV(device)];
82     device_t parent = device_get_parent(ch->dev);
83     int devno = (ch->unit << 1) + ATA_DEV(device);
84     int error;
85 
86     /* set our most pessimistic default mode */
87     atadev->mode = ATA_PIO;
88 
89     if (!ch->r_bmio)
90 	return;
91 
92     /* if simplex controller, only allow DMA on primary channel */
93     if (ch->unit == 1) {
94 	ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
95 		 ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) &
96 		 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
97 	if (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
98 	    ata_prtdev(atadev, "simplex device, DMA on primary only\n");
99 	    return;
100 	}
101     }
102 
103     /* DMA engine address alignment is usually 1 word (2 bytes) */
104     ch->alignment = 0x1;
105 
106 #if 1
107     if (udmamode > 2 && !ch->device[ATA_DEV(device)].param->hwres_cblid) {
108 	ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
109 	udmamode = 2;
110     }
111 #endif
112     switch (ch->chiptype) {
113 
114     case 0x248a8086:	/* Intel ICH3 mobile */
115     case 0x248b8086:	/* Intel ICH3 */
116     case 0x244a8086:	/* Intel ICH2 mobile */
117     case 0x244b8086:	/* Intel ICH2 */
118 	if (udmamode >= 5) {
119 	    int32_t mask48, new48;
120 	    int16_t word54;
121 
122 	    word54 = pci_read_config(parent, 0x54, 2);
123 	    if (word54 & (0x10 << devno)) {
124 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
125 				    ATA_UDMA5,	ATA_C_F_SETXFER,ATA_WAIT_READY);
126 		if (bootverbose)
127 		    ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n",
128 			       (error) ? "failed" : "success");
129 		if (!error) {
130 		    mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
131 		    new48 = (1 << devno) + (1 << (16 + (devno << 2)));
132 		    pci_write_config(parent, 0x48,
133 				     (pci_read_config(parent, 0x48, 4) &
134 				     ~mask48) | new48, 4);
135 		    pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
136 		    atadev->mode = ATA_UDMA5;
137 		    return;
138 		}
139 	    }
140 	}
141 	/* make sure eventual ATA100 mode from the BIOS is disabled */
142 	pci_write_config(parent, 0x54,
143 			 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
144 	/* FALLTHROUGH */
145 
146     case 0x24118086:	/* Intel ICH */
147     case 0x76018086:	/* Intel ICH */
148 	if (udmamode >= 4) {
149 	    int32_t mask48, new48;
150 	    int16_t word54;
151 
152 	    word54 = pci_read_config(parent, 0x54, 2);
153 	    if (word54 & (0x10 << devno)) {
154 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
155 				    ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
156 		if (bootverbose)
157 		    ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n",
158 			       (error) ? "failed" : "success");
159 		if (!error) {
160 		    mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
161 		    new48 = (1 << devno) + (2 << (16 + (devno << 2)));
162 		    pci_write_config(parent, 0x48,
163 				     (pci_read_config(parent, 0x48, 4) &
164 				     ~mask48) | new48, 4);
165 		    pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
166 		    atadev->mode = ATA_UDMA4;
167 		    return;
168 		}
169 	    }
170 	}
171 	/* make sure eventual ATA66 mode from the BIOS is disabled */
172 	pci_write_config(parent, 0x54,
173 			 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
174 	/* FALLTHROUGH */
175 
176     case 0x71118086:	/* Intel PIIX4 */
177     case 0x84CA8086:	/* Intel PIIX4 */
178     case 0x71998086:	/* Intel PIIX4e */
179     case 0x24218086:	/* Intel ICH0 */
180 	if (udmamode >= 2) {
181 	    int32_t mask48, new48;
182 
183 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
184 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
185 	    if (bootverbose)
186 		ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n",
187 			   (error) ? "failed" : "success");
188 	    if (!error) {
189 		mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
190 		new48 = (1 << devno) + (2 << (16 + (devno << 2)));
191 		pci_write_config(parent, 0x48,
192 				 (pci_read_config(parent, 0x48, 4) &
193 				 ~mask48) | new48, 4);
194 		atadev->mode = ATA_UDMA2;
195 		return;
196 	    }
197 	}
198 	/* make sure eventual ATA33 mode from the BIOS is disabled */
199 	pci_write_config(parent, 0x48,
200 			 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
201 	/* FALLTHROUGH */
202 
203     case 0x70108086:	/* Intel PIIX3 */
204 	if (wdmamode >= 2 && apiomode >= 4) {
205 	    int32_t mask40, new40, mask44, new44;
206 
207 	    /* if SITRE not set doit for both channels */
208 	    if (!((pci_read_config(parent,0x40,4)>>(ch->unit<<8))&0x4000)) {
209 		new40 = pci_read_config(parent, 0x40, 4);
210 		new44 = pci_read_config(parent, 0x44, 4);
211 		if (!(new40 & 0x00004000)) {
212 		    new44 &= ~0x0000000f;
213 		    new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
214 		}
215 		if (!(new40 & 0x40000000)) {
216 		    new44 &= ~0x000000f0;
217 		    new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
218 		}
219 		new40 |= 0x40004000;
220 		pci_write_config(parent, 0x40, new40, 4);
221 		pci_write_config(parent, 0x44, new44, 4);
222 	    }
223 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
224 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
225 	    if (bootverbose)
226 		ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
227 			   (error) ? "failed" : "success");
228 	    if (!error) {
229 		if (device == ATA_MASTER) {
230 		    mask40 = 0x0000330f;
231 		    new40 = 0x00002307;
232 		    mask44 = 0;
233 		    new44 = 0;
234 		}
235 		else {
236 		    mask40 = 0x000000f0;
237 		    new40 = 0x00000070;
238 		    mask44 = 0x0000000f;
239 		    new44 = 0x0000000b;
240 		}
241 		if (ch->unit) {
242 		    mask40 <<= 16;
243 		    new40 <<= 16;
244 		    mask44 <<= 4;
245 		    new44 <<= 4;
246 		}
247 		pci_write_config(parent, 0x40,
248 				 (pci_read_config(parent, 0x40, 4) & ~mask40)|
249 				 new40, 4);
250 		pci_write_config(parent, 0x44,
251 				 (pci_read_config(parent, 0x44, 4) & ~mask44)|
252 				 new44, 4);
253 		atadev->mode = ATA_WDMA2;
254 		return;
255 	    }
256 	}
257 	/* we could set PIO mode timings, but we assume the BIOS did that */
258 	break;
259 
260     case 0x12308086:	/* Intel PIIX */
261 	if (wdmamode >= 2 && apiomode >= 4) {
262 	    int32_t word40;
263 
264 	    word40 = pci_read_config(parent, 0x40, 4);
265 	    word40 >>= ch->unit * 16;
266 
267 	    /* Check for timing config usable for DMA on controller */
268 	    if (!((word40 & 0x3300) == 0x2300 &&
269 		  ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
270 		break;
271 
272 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
273 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
274 	    if (bootverbose)
275 		ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
276 			   (error) ? "failed" : "success");
277 	    if (!error) {
278 		atadev->mode = ATA_WDMA2;
279 		return;
280 	    }
281 	}
282 	break;
283 
284     case 0x522910b9:	/* AcerLabs Aladdin IV/V */
285 	/* the older Aladdin doesn't support ATAPI DMA on both master & slave */
286 	if (pci_get_revid(parent) < 0xc2 &&
287 	    ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
288 	    ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
289 	    break;
290 	}
291 	if (udmamode >= 5 && pci_get_revid(parent) >= 0xc4) {
292 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
293 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
294 	    if (bootverbose)
295 		ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n",
296 			   (error) ? "failed" : "success");
297 	    if (!error) {
298 		int32_t word54 = pci_read_config(parent, 0x54, 4);
299 
300 		pci_write_config(parent, 0x4b,
301 				 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
302 		word54 &= ~(0x000f000f << (devno << 2));
303 		word54 |= (0x000f0005 << (devno << 2));
304 		pci_write_config(parent, 0x54, word54, 4);
305 		pci_write_config(parent, 0x53,
306 				 pci_read_config(parent, 0x53, 1) | 0x03, 1);
307 		atadev->mode = ATA_UDMA5;
308 		return;
309 	    }
310 	}
311 	if (udmamode >= 4 && pci_get_revid(parent) >= 0xc2) {
312 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
313 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
314 	    if (bootverbose)
315 		ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n",
316 			   (error) ? "failed" : "success");
317 	    if (!error) {
318 		int32_t word54 = pci_read_config(parent, 0x54, 4);
319 
320 		pci_write_config(parent, 0x4b,
321 				 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
322 		word54 &= ~(0x000f000f << (devno << 2));
323 		word54 |= (0x00080005 << (devno << 2));
324 		pci_write_config(parent, 0x54, word54, 4);
325 		pci_write_config(parent, 0x53,
326 				 pci_read_config(parent, 0x53, 1) | 0x03, 1);
327 		atadev->mode = ATA_UDMA4;
328 		return;
329 	    }
330 	}
331 	if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) {
332 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
333 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
334 	    if (bootverbose)
335 		ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n",
336 			   (error) ? "failed" : "success");
337 	    if (!error) {
338 		int32_t word54 = pci_read_config(parent, 0x54, 4);
339 
340 		word54 &= ~(0x000f000f << (devno << 2));
341 		word54 |= (0x000a0005 << (devno << 2));
342 		pci_write_config(parent, 0x54, word54, 4);
343 		pci_write_config(parent, 0x53,
344 				 pci_read_config(parent, 0x53, 1) | 0x03, 1);
345 		ch->flags |= ATA_ATAPI_DMA_RO;
346 		atadev->mode = ATA_UDMA2;
347 		return;
348 	    }
349 	}
350 
351 	/* make sure eventual UDMA mode from the BIOS is disabled */
352 	pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
353 				       ~(0x0008 << (devno << 2)), 2);
354 
355 	if (wdmamode >= 2 && apiomode >= 4) {
356 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
357 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
358 	    if (bootverbose)
359 		ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n",
360 			   (error) ? "failed" : "success");
361 	    if (!error) {
362 		pci_write_config(parent, 0x53,
363 				 pci_read_config(parent, 0x53, 1) | 0x03, 1);
364 		ch->flags |= ATA_ATAPI_DMA_RO;
365 		atadev->mode = ATA_WDMA2;
366 		return;
367 	    }
368 	}
369 	pci_write_config(parent, 0x53,
370 			 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
371 	/* we could set PIO mode timings, but we assume the BIOS did that */
372 	break;
373 
374     case 0x74111022:	/* AMD 766 */
375 	if (udmamode >= 5) {
376 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
377 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
378 	    if (bootverbose)
379 		ata_prtdev(atadev, "%s setting UDMA5 on AMD chip\n",
380 			   (error) ? "failed" : "success");
381 	    if (!error) {
382 		pci_write_config(parent, 0x53 - devno, 0xc6, 1);
383 		atadev->mode = ATA_UDMA5;
384 		return;
385 	    }
386 	}
387 	/* FALLTHROUGH */
388 
389     case 0x74091022:	/* AMD 756 */
390 	if (udmamode >= 4) {
391 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
392 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
393 	    if (bootverbose)
394 		ata_prtdev(atadev, "%s setting UDMA4 on AMD chip\n",
395 			   (error) ? "failed" : "success");
396 	    if (!error) {
397 		pci_write_config(parent, 0x53 - devno, 0xc5, 1);
398 		atadev->mode = ATA_UDMA4;
399 		return;
400 	    }
401 	}
402 	goto via_82c586;
403 
404     case 0x05711106:	/* VIA 82C571, 82C586, 82C596, 82C686 , 8231, 8233 */
405 	{
406 	    int via_modes[4][7] = {
407 		{ 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 },	/* ATA33 */
408 		{ 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 },	/* ATA66 */
409 		{ 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 },	/* ATA100 */
410 		{ 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 }};	/* ATA133 */
411 	    int *reg_val = NULL;
412 
413 	    if (ata_find_dev(parent, 0x31471106, 0x40)) {	/* 8233a */
414 		udmamode = imin(udmamode, 6);
415 		reg_val = via_modes[3];
416 	    }
417 	    else if (ata_find_dev(parent, 0x06861106, 0x40) ||	/* 82C686b */
418 		ata_find_dev(parent, 0x82311106, 0) ||		/* 8231 */
419 		ata_find_dev(parent, 0x30741106, 0) ||		/* 8233 */
420 		ata_find_dev(parent, 0x31091106, 0)) {		/* 8233c */
421 		udmamode = imin(udmamode, 5);
422 		reg_val = via_modes[2];
423 	    }
424 	    else if (ata_find_dev(parent, 0x06861106, 0x10) ||	/* 82C686a */
425 		     ata_find_dev(parent, 0x05961106, 0x12)) {	/* 82C596b */
426 		udmamode = imin(udmamode, 4);
427 		reg_val = via_modes[1];
428 	    }
429 	    else if (ata_find_dev(parent, 0x06861106, 0x0)) {	/* 82C686 */
430 		udmamode = imin(udmamode, 2);
431 		reg_val = via_modes[1];
432 	    }
433 	    else if (ata_find_dev(parent, 0x05961106, 0) ||	/* 82C596a */
434 		     ata_find_dev(parent, 0x05861106, 0x03)) {	/* 82C586b */
435 via_82c586:
436 		udmamode = imin(udmamode, 2);
437 		reg_val = via_modes[0];
438 	    }
439 	    else
440 		udmamode = 0;
441 
442 	    if (udmamode >= 6) {
443 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
444 				    ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
445 		if (bootverbose)
446 		    ata_prtdev(atadev, "%s setting UDMA6 on VIA chip\n",
447 			       (error) ? "failed" : "success");
448 		if (!error) {
449 		    pci_write_config(parent, 0x53 - devno, reg_val[6], 1);
450 		    atadev->mode = ATA_UDMA6;
451 		    return;
452 		}
453 	    }
454 	    if (udmamode >= 5) {
455 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
456 				    ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
457 		if (bootverbose)
458 		    ata_prtdev(atadev, "%s setting UDMA5 on VIA chip\n",
459 			       (error) ? "failed" : "success");
460 		if (!error) {
461 		    pci_write_config(parent, 0x53 - devno, reg_val[5], 1);
462 		    atadev->mode = ATA_UDMA5;
463 		    return;
464 		}
465 	    }
466 	    if (udmamode >= 4) {
467 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
468 				    ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
469 		if (bootverbose)
470 		    ata_prtdev(atadev, "%s setting UDMA4 on VIA chip\n",
471 			       (error) ? "failed" : "success");
472 		if (!error) {
473 		    pci_write_config(parent, 0x53 - devno, reg_val[4], 1);
474 		    atadev->mode = ATA_UDMA4;
475 		    return;
476 		}
477 	    }
478 	    if (udmamode >= 2) {
479 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
480 				    ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
481 		if (bootverbose)
482 		    ata_prtdev(atadev, "%s setting UDMA2 on VIA chip\n",
483 			       (error) ? "failed" : "success");
484 		if (!error) {
485 		    pci_write_config(parent, 0x53 - devno, reg_val[2], 1);
486 		    atadev->mode = ATA_UDMA2;
487 		    return;
488 		}
489 	    }
490 
491 	}
492 	if (wdmamode >= 2 && apiomode >= 4) {
493 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
494 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
495 	    if (bootverbose)
496 		ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n",
497 			   (error) ? "failed" : "success",
498 			   (ch->chiptype == 0x74091022) ? "AMD" : "VIA");
499 	    if (!error) {
500 		pci_write_config(parent, 0x53 - devno, 0x0b, 1);
501 		pci_write_config(parent, 0x4b - devno, 0x31, 1);
502 		atadev->mode = ATA_WDMA2;
503 		return;
504 	    }
505 	}
506 	/* we could set PIO mode timings, but we assume the BIOS did that */
507 	break;
508 
509     case 0x55131039:	/* SiS 5591 */
510 	if (ata_find_dev(parent, 0x06301039, 0x30) ||	/* SiS 630 */
511 	    ata_find_dev(parent, 0x06331039, 0x00) ||	/* SiS 633 */
512 	    ata_find_dev(parent, 0x06351039, 0x00) ||	/* SiS 635 */
513 	    ata_find_dev(parent, 0x06401039, 0x00) ||	/* SiS 640 */
514 	    ata_find_dev(parent, 0x06451039, 0x00) ||	/* SiS 645 */
515 	    ata_find_dev(parent, 0x06501039, 0x00) ||	/* SiS 650 */
516 	    ata_find_dev(parent, 0x07301039, 0x00) ||	/* SiS 730 */
517 	    ata_find_dev(parent, 0x07331039, 0x00) ||	/* SiS 733 */
518 	    ata_find_dev(parent, 0x07351039, 0x00) ||	/* SiS 735 */
519 	    ata_find_dev(parent, 0x07401039, 0x00) ||	/* SiS 740 */
520 	    ata_find_dev(parent, 0x07451039, 0x00) ||	/* SiS 745 */
521 	    ata_find_dev(parent, 0x07501039, 0x00)) {	/* SiS 750 */
522 	    int8_t reg = 0x40 + (devno << 1);
523 	    int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
524 
525 	    if (udmamode >= 5) {
526 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
527 				    ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
528 		if (bootverbose)
529 		    ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n",
530 			       (error) ? "failed" : "success");
531 		if (!error) {
532 		    pci_write_config(parent, reg, val | 0x8000, 2);
533 		    atadev->mode = ATA_UDMA5;
534 		    return;
535 		}
536 	    }
537 	    if (udmamode >= 4) {
538 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
539 				    ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
540 		if (bootverbose)
541 		    ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
542 			       (error) ? "failed" : "success");
543 		if (!error) {
544 		    pci_write_config(parent, reg, val | 0x9000, 2);
545 		    atadev->mode = ATA_UDMA4;
546 		    return;
547 		}
548 	    }
549 	    if (udmamode >= 2) {
550 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
551 				    ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
552 		if (bootverbose)
553 		    ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
554 			       (error) ? "failed" : "success");
555 		if (!error) {
556 		    pci_write_config(parent, reg, val | 0xb000, 2);
557 		    atadev->mode = ATA_UDMA2;
558 		    return;
559 		}
560 	    }
561 	} else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
562 		   ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
563 		   ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
564 		   ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
565 	    int8_t reg = 0x40 + (devno << 1);
566 	    int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
567 
568 	    if (udmamode >= 4) {
569 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
570 				    ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
571 		if (bootverbose)
572 		    ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
573 			       (error) ? "failed" : "success");
574 		if (!error) {
575 		    pci_write_config(parent, reg, val | 0x9000, 2);
576 		    atadev->mode = ATA_UDMA4;
577 		    return;
578 		}
579 	    }
580 	    if (udmamode >= 2) {
581 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
582 				    ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
583 		if (bootverbose)
584 		    ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
585 			       (error) ? "failed" : "success");
586 		if (!error) {
587 		    pci_write_config(parent, reg, val | 0xa000, 2);
588 		    atadev->mode = ATA_UDMA2;
589 		    return;
590 		}
591 	    }
592 	} else if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) {
593 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
594 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
595 	    if (bootverbose)
596 		ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
597 			   (error) ? "failed" : "success");
598 	    if (!error) {
599 		pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
600 		atadev->mode = ATA_UDMA2;
601 		return;
602 	    }
603 	}
604 	if (wdmamode >=2 && apiomode >= 4) {
605 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
606 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
607 	    if (bootverbose)
608 		ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n",
609 			   (error) ? "failed" : "success");
610 	    if (!error) {
611 		pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
612 		atadev->mode = ATA_WDMA2;
613 		return;
614 	    }
615 	}
616 	/* we could set PIO mode timings, but we assume the BIOS did that */
617 	break;
618 
619     case 0x06491095:	/* CMD 649 ATA100 controller */
620 	if (udmamode >= 5) {
621 	    u_int8_t umode;
622 
623 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
624 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
625 	    if (bootverbose)
626 		ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n",
627 			   (error) ? "failed" : "success");
628 	    if (!error) {
629 		umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
630 		umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
631 		umode |= (device == ATA_MASTER ? 0x05 : 0x0a);
632 		pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
633 		atadev->mode = ATA_UDMA5;
634 		return;
635 	    }
636 	}
637 	/* FALLTHROUGH */
638 
639     case 0x06481095:	/* CMD 648 ATA66 controller */
640 	if (udmamode >= 4) {
641 	    u_int8_t umode;
642 
643 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
644 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
645 	    if (bootverbose)
646 		ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n",
647 			   (error) ? "failed" : "success");
648 	    if (!error) {
649 		umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
650 		umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
651 		umode |= (device == ATA_MASTER ? 0x15 : 0x4a);
652 		pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
653 		atadev->mode = ATA_UDMA4;
654 		return;
655 	    }
656 	}
657 	if (udmamode >= 2) {
658 	    u_int8_t umode;
659 
660 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
661 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
662 	    if (bootverbose)
663 		ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n",
664 			   (error) ? "failed" : "success");
665 	    if (!error) {
666 		umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
667 		umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
668 		umode |= (device == ATA_MASTER ? 0x11 : 0x42);
669 		pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
670 		atadev->mode = ATA_UDMA2;
671 		return;
672 	    }
673 	}
674 	/* make sure eventual UDMA mode from the BIOS is disabled */
675 	pci_write_config(parent, ch->unit ? 0x7b : 0x73,
676 			 pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1)&
677 			 ~(device == ATA_MASTER ? 0x35 : 0xca), 1);
678 	/* FALLTHROUGH */
679 
680     case 0x06461095:	/* CMD 646 ATA controller */
681 	if (wdmamode >= 2 && apiomode >= 4) {
682 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
683 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
684 	    if (bootverbose)
685 		ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n",
686 			   error ? "failed" : "success");
687 	    if (!error) {
688 		int32_t offset = (devno < 3) ? (devno << 1) : 7;
689 
690 		pci_write_config(parent, 0x54 + offset, 0x3f, 1);
691 		atadev->mode = ATA_WDMA2;
692 		return;
693 	    }
694 	}
695 	/* we could set PIO mode timings, but we assume the BIOS did that */
696 	break;
697 
698     case 0xc6931080:	/* Cypress 82c693 ATA controller */
699 	if (wdmamode >= 2 && apiomode >= 4) {
700 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
701 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
702 	    if (bootverbose)
703 		ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n",
704 			   error ? "failed" : "success");
705 	    if (!error) {
706 		pci_write_config(ch->dev, ch->unit ? 0x4e:0x4c, 0x2020, 2);
707 		atadev->mode = ATA_WDMA2;
708 		return;
709 	    }
710 	}
711 	/* we could set PIO mode timings, but we assume the BIOS did that */
712 	break;
713 
714     case 0x01021078:	/* Cyrix 5530 ATA33 controller */
715 	ch->alignment = 0xf;	/* DMA engine requires 16 byte alignment */
716 	if (udmamode >= 2) {
717 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
718 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
719 	    if (bootverbose)
720 		ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n",
721 			   (error) ? "failed" : "success");
722 	    if (!error) {
723 		cyrix_timing(ch, devno, ATA_UDMA2);
724 		atadev->mode = ATA_UDMA2;
725 		return;
726 	    }
727 	}
728 	if (wdmamode >= 2 && apiomode >= 4) {
729 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
730 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
731 	    if (bootverbose)
732 		ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n",
733 			   (error) ? "failed" : "success");
734 	    if (!error) {
735 		cyrix_timing(ch, devno, ATA_WDMA2);
736 		atadev->mode = ATA_WDMA2;
737 		return;
738 	    }
739 	}
740 	error = ata_command(atadev, ATA_C_SETFEATURES, 0,
741 			    ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
742 			    ATA_WAIT_READY);
743 	if (bootverbose)
744 	    ata_prtdev(atadev, "%s setting %s on Cyrix chip\n",
745 		       (error) ? "failed" : "success",
746 		       ata_mode2str(ATA_PIO0 + apiomode));
747 	cyrix_timing(ch, devno, ATA_PIO0 + apiomode);
748 	atadev->mode = ATA_PIO0 + apiomode;
749 	return;
750 
751     case 0x02111166:	/* ServerWorks ROSB4 ATA33 controller */
752 	if (udmamode >= 2) {
753 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
754 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
755 	    if (bootverbose)
756 		ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n",
757 			   (error) ? "failed" : "success");
758 	    if (!error) {
759 		u_int16_t reg56;
760 
761 		pci_write_config(parent, 0x54,
762 				 pci_read_config(parent, 0x54, 1) |
763 				 (0x01 << devno), 1);
764 		reg56 = pci_read_config(parent, 0x56, 2);
765 		reg56 &= ~(0xf << (devno * 4));
766 		reg56 |= (0x2 << (devno * 4));
767 		pci_write_config(parent, 0x56, reg56, 2);
768 		atadev->mode = ATA_UDMA2;
769 		return;
770 	    }
771 	}
772 	if (wdmamode >= 2 && apiomode >= 4) {
773 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
774 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
775 	    if (bootverbose)
776 		ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n",
777 			   (error) ? "failed" : "success");
778 	    if (!error) {
779 		int offset = (ch->unit * 2) + (device == ATA_MASTER);
780 		int word44 = pci_read_config(parent, 0x44, 4);
781 
782 		pci_write_config(parent, 0x54,
783 				 pci_read_config(parent, 0x54, 1) &
784 				 ~(0x01 << devno), 1);
785 		word44 &= ~(0xff << (offset << 8));
786 		word44 |= (0x20 << (offset << 8));
787 		pci_write_config(parent, 0x44, 0x20, 4);
788 		atadev->mode = ATA_WDMA2;
789 		return;
790 	    }
791 	}
792 	/* we could set PIO mode timings, but we assume the BIOS did that */
793 	break;
794 
795     case 0x4d69105a:	/* Promise TX2 ATA133 controllers */
796 	ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
797 	if (udmamode >= 6 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
798 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
799 				ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
800 	    if (bootverbose)
801 		ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n",
802 			   (error) ? "failed" : "success");
803 	    if (!error) {
804 		atadev->mode = ATA_UDMA6;
805 		return;
806 	    }
807 	}
808 	/* FALLTHROUGH */
809 
810     case 0x4d68105a:	/* Promise TX2 ATA100 controllers */
811     case 0x6268105a:	/* Promise TX2 ATA100 controllers */
812 	ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
813 	if (udmamode >= 5 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
814 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
815 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
816 	    if (bootverbose)
817 		ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
818 			   (error) ? "failed" : "success");
819 	    if (!error) {
820 		atadev->mode = ATA_UDMA5;
821 		return;
822 	    }
823 	}
824 	ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
825 	if (udmamode >= 4 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
826 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
827 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
828 	    if (bootverbose)
829 		ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
830 			   (error) ? "failed" : "success");
831 	    if (!error) {
832 		atadev->mode = ATA_UDMA4;
833 		return;
834 	    }
835 	}
836 	if (udmamode >= 2) {
837 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
838 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
839 	    if (bootverbose)
840 		ata_prtdev(atadev, "%s setting UDMA on Promise chip\n",
841 			   (error) ? "failed" : "success");
842 	    if (!error) {
843 		atadev->mode = ATA_UDMA2;
844 		return;
845 	    }
846 	}
847 	if (wdmamode >= 2 && apiomode >= 4) {
848 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
849 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
850 	    if (bootverbose)
851 		ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
852 			   (error) ? "failed" : "success");
853 	    if (!error) {
854 		atadev->mode = ATA_WDMA2;
855 		return;
856 	    }
857 	}
858 	break;
859 
860     case 0x4d30105a:	/* Promise Ultra/FastTrak 100 controllers */
861     case 0x0d30105a:	/* Promise OEM ATA100 controllers */
862 	if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 &&
863 	    !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){
864 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
865 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
866 	    if (bootverbose)
867 		ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
868 			   (error) ? "failed" : "success");
869 	    if (!error) {
870 		promise_timing(ch, devno, ATA_UDMA5);
871 		atadev->mode = ATA_UDMA5;
872 		return;
873 	    }
874 	}
875 	/* FALLTHROUGH */
876 
877     case 0x4d38105a:	/* Promise Ultra/FastTrak 66 controllers */
878 	if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 &&
879 	    !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){
880 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
881 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
882 	    if (bootverbose)
883 		ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
884 			   (error) ? "failed" : "success");
885 	    if (!error) {
886 		promise_timing(ch, devno, ATA_UDMA4);
887 		atadev->mode = ATA_UDMA4;
888 		return;
889 	    }
890 	}
891 	/* FALLTHROUGH */
892 
893     case 0x4d33105a:	/* Promise Ultra/FastTrak 33 controllers */
894 	if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) {
895 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
896 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
897 	    if (bootverbose)
898 		ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n",
899 			   (error) ? "failed" : "success");
900 	    if (!error) {
901 		promise_timing(ch, devno, ATA_UDMA2);
902 		atadev->mode = ATA_UDMA2;
903 		return;
904 	    }
905 	}
906 	if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) {
907 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
908 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
909 	    if (bootverbose)
910 		ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
911 			   (error) ? "failed" : "success");
912 	    if (!error) {
913 		promise_timing(ch, devno, ATA_WDMA2);
914 		atadev->mode = ATA_WDMA2;
915 		return;
916 	    }
917 	}
918 	error = ata_command(atadev, ATA_C_SETFEATURES, 0,
919 			    ATA_PIO0 + apiomode,
920 			    ATA_C_F_SETXFER, ATA_WAIT_READY);
921 	if (bootverbose)
922 	    ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n",
923 		       (error) ? "failed" : "success",
924 		       (apiomode >= 0) ? apiomode : 0);
925 	promise_timing(ch, devno, ATA_PIO0 + apiomode);
926 	atadev->mode = ATA_PIO0 + apiomode;
927 	return;
928 
929     case 0x00041103:	/* HighPoint HPT366/368/370/372 controllers */
930     case 0x00051103:	/* HighPoint HPT372 controllers */
931     case 0x00081103:	/* HighPoint HPT374 controllers */
932 	if (!ATAPI_DEVICE(ch, device) && udmamode >= 6 &&
933 	    ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) ||
934 	     (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01) ||
935 	     (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07)) &&
936 	    !(pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x01:0x02))) {
937 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
938 				ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
939 	    if (bootverbose)
940 		ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n",
941 			   (error) ? "failed" : "success");
942 	    if (!error) {
943 		hpt_timing(ch, devno, ATA_UDMA6);
944 		atadev->mode = ATA_UDMA6;
945 		return;
946 	    }
947 	}
948 	if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 &&
949 	    ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) ||
950 	     (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01) ||
951 	     (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07)) &&
952 	    !(pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x01:0x02))) {
953 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
954 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
955 	    if (bootverbose)
956 		ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n",
957 			   (error) ? "failed" : "success");
958 	    if (!error) {
959 		hpt_timing(ch, devno, ATA_UDMA5);
960 		atadev->mode = ATA_UDMA5;
961 		return;
962 	    }
963 	}
964 	if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 &&
965 	    !(pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x01:0x02))) {
966 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
967 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
968 	    if (bootverbose)
969 		ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n",
970 			   (error) ? "failed" : "success");
971 	    if (!error) {
972 		hpt_timing(ch, devno, ATA_UDMA4);
973 		atadev->mode = ATA_UDMA4;
974 		return;
975 	    }
976 	}
977 	if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) {
978 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
979 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
980 	    if (bootverbose)
981 		ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n",
982 			   (error) ? "failed" : "success");
983 	    if (!error) {
984 		hpt_timing(ch, devno, ATA_UDMA2);
985 		atadev->mode = ATA_UDMA2;
986 		return;
987 	    }
988 	}
989 	if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) {
990 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
991 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
992 	    if (bootverbose)
993 		ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n",
994 			   (error) ? "failed" : "success");
995 	    if (!error) {
996 		hpt_timing(ch, devno, ATA_WDMA2);
997 		atadev->mode = ATA_WDMA2;
998 		return;
999 	    }
1000 	}
1001 	error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1002 			    ATA_PIO0 + apiomode,
1003 			    ATA_C_F_SETXFER, ATA_WAIT_READY);
1004 	if (bootverbose)
1005 	    ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n",
1006 		       (error) ? "failed" : "success",
1007 		       (apiomode >= 0) ? apiomode : 0);
1008 	hpt_timing(ch, devno, ATA_PIO0 + apiomode);
1009 	atadev->mode = ATA_PIO0 + apiomode;
1010 	return;
1011 
1012     case 0x000116ca:	/* Cenatek Rocket Drive controller */
1013 	if (wdmamode >= 0 &&
1014 	    (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) &
1015 	     ((device==ATA_MASTER)?ATA_BMSTAT_DMA_MASTER:ATA_BMSTAT_DMA_SLAVE)))
1016 	    atadev->mode = ATA_DMA;
1017 	else
1018 	    atadev->mode = ATA_PIO;
1019 	return;
1020 
1021     default:		/* unknown controller chip */
1022 	/* better not try generic DMA on ATAPI devices it almost never works */
1023 	if ((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
1024 	    (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE))
1025 	    break;
1026 
1027 	/* if controller says its setup for DMA take the easy way out */
1028 	/* the downside is we dont know what DMA mode we are in */
1029 	if ((udmamode >= 0 || wdmamode >= 2) &&
1030 	    (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) &
1031 	     ((device==ATA_MASTER) ?
1032 	      ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
1033 	    atadev->mode = ATA_DMA;
1034 	    return;
1035 	}
1036 
1037 	/* well, we have no support for this, but try anyways */
1038 	if ((wdmamode >= 2 && apiomode >= 4) && ch->r_bmio) {
1039 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1040 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1041 	    if (bootverbose)
1042 		ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n",
1043 			   (error) ? "failed" : "success");
1044 	    if (!error) {
1045 		atadev->mode = ATA_WDMA2;
1046 		return;
1047 	    }
1048 	}
1049     }
1050     error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
1051 			ATA_C_F_SETXFER, ATA_WAIT_READY);
1052     if (bootverbose)
1053 	ata_prtdev(atadev, "%s setting PIO%d on generic chip\n",
1054 		   (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
1055     if (!error)
1056 	atadev->mode = ATA_PIO0 + apiomode;
1057     else {
1058 	if (bootverbose)
1059 	    ata_prtdev(atadev, "using PIO mode set by BIOS\n");
1060 	atadev->mode = ATA_PIO;
1061     }
1062 }
1063 
1064 int
1065 ata_dmasetup(struct ata_channel *ch, int device, struct ata_dmaentry *dmatab,
1066 	     caddr_t data, int32_t count)
1067 {
1068     u_int32_t dma_count, dma_base;
1069     int i = 0;
1070 
1071     if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) {
1072 	ata_printf(ch, device, "non aligned DMA transfer attempted\n");
1073 	return -1;
1074     }
1075 
1076     if (!count) {
1077 	ata_printf(ch, device, "zero length DMA transfer attempted\n");
1078 	return -1;
1079     }
1080 
1081     dma_base = vtophys(data);
1082     dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
1083     data += dma_count;
1084     count -= dma_count;
1085 
1086     while (count) {
1087 	dmatab[i].base = dma_base;
1088 	dmatab[i].count = (dma_count & 0xffff);
1089 	i++;
1090 	if (i >= ATA_DMA_ENTRIES) {
1091 	    ata_printf(ch, device, "too many segments in DMA table\n");
1092 	    return -1;
1093 	}
1094 	dma_base = vtophys(data);
1095 	dma_count = imin(count, PAGE_SIZE);
1096 	data += imin(count, PAGE_SIZE);
1097 	count -= imin(count, PAGE_SIZE);
1098     }
1099     dmatab[i].base = dma_base;
1100     dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
1101     return 0;
1102 }
1103 
1104 void
1105 ata_dmastart(struct ata_channel *ch, int device,
1106 	     struct ata_dmaentry *dmatab, int dir)
1107 {
1108     ch->flags |= ATA_DMA_ACTIVE;
1109     ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab));
1110     ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1111     ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1112 	 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) |
1113 	  (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1114     ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1115 	 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1116 }
1117 
1118 int
1119 ata_dmadone(struct ata_channel *ch)
1120 {
1121     int error;
1122 
1123     ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1124 		ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1125     ch->flags &= ~ATA_DMA_ACTIVE;
1126     error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
1127     ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1128 	     error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1129     return error & ATA_BMSTAT_MASK;
1130 }
1131 
1132 int
1133 ata_dmastatus(struct ata_channel *ch)
1134 {
1135     return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1136 }
1137 
1138 static void
1139 cyrix_timing(struct ata_channel *ch, int devno, int mode)
1140 {
1141     u_int32_t reg20 = 0x0000e132;
1142     u_int32_t reg24 = 0x00017771;
1143 
1144     switch (mode) {
1145     case ATA_PIO0:	reg20 = 0x0000e132; break;
1146     case ATA_PIO1:	reg20 = 0x00018121; break;
1147     case ATA_PIO2:	reg20 = 0x00024020; break;
1148     case ATA_PIO3:	reg20 = 0x00032010; break;
1149     case ATA_PIO4:	reg20 = 0x00040010; break;
1150     case ATA_WDMA2:	reg24 = 0x00002020; break;
1151     case ATA_UDMA2:	reg24 = 0x00911030; break;
1152     }
1153     ATA_OUTL(ch->r_bmio, (devno << 3) + 0x20, reg20);
1154     ATA_OUTL(ch->r_bmio, (devno << 3) + 0x24, reg24);
1155 }
1156 
1157 static void
1158 promise_timing(struct ata_channel *ch, int devno, int mode)
1159 {
1160     u_int32_t timing = 0;
1161     struct promise_timing {
1162 	u_int8_t  pa:4;
1163 	u_int8_t  prefetch:1;
1164 	u_int8_t  iordy:1;
1165 	u_int8_t  errdy:1;
1166 	u_int8_t  syncin:1;
1167 	u_int8_t  pb:5;
1168 	u_int8_t  mb:3;
1169 	u_int8_t  mc:4;
1170 	u_int8_t  dmaw:1;
1171 	u_int8_t  dmar:1;
1172 	u_int8_t  iordyp:1;
1173 	u_int8_t  dmarqp:1;
1174 	u_int8_t  reserved:8;
1175     } *t = (struct promise_timing*)&timing;
1176 
1177     t->iordy = 1; t->iordyp = 1;
1178     if (mode >= ATA_DMA) {
1179 	t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1180     }
1181 
1182     switch (ch->chiptype) {
1183     case 0x4d33105a:  /* Promise Ultra/Fasttrak 33 */
1184 	switch (mode) {
1185 	default:
1186 	case ATA_PIO0:	t->pa =	 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1187 	case ATA_PIO1:	t->pa =	 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1188 	case ATA_PIO2:	t->pa =	 3; t->pb =  8; t->mb = 7; t->mc = 15; break;
1189 	case ATA_PIO3:	t->pa =	 2; t->pb =  6; t->mb = 7; t->mc = 15; break;
1190 	case ATA_PIO4:	t->pa =	 1; t->pb =  4; t->mb = 7; t->mc = 15; break;
1191 	case ATA_WDMA2: t->pa =	 3; t->pb =  7; t->mb = 3; t->mc =  3; break;
1192 	case ATA_UDMA2: t->pa =	 3; t->pb =  7; t->mb = 1; t->mc =  1; break;
1193 	}
1194 	break;
1195 
1196     case 0x4d38105a:  /* Promise Ultra/Fasttrak 66 */
1197     case 0x4d30105a:  /* Promise Ultra/Fasttrak 100 */
1198     case 0x0d30105a:  /* Promise OEM ATA 100 */
1199 	switch (mode) {
1200 	default:
1201 	case ATA_PIO0:	t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1202 	case ATA_PIO1:	t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1203 	case ATA_PIO2:	t->pa =	 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1204 	case ATA_PIO3:	t->pa =	 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1205 	case ATA_PIO4:	t->pa =	 2; t->pb =  8; t->mb = 7; t->mc = 15; break;
1206 	case ATA_WDMA2: t->pa =	 6; t->pb = 14; t->mb = 6; t->mc =  6; break;
1207 	case ATA_UDMA2: t->pa =	 6; t->pb = 14; t->mb = 2; t->mc =  2; break;
1208 	case ATA_UDMA4: t->pa =	 3; t->pb =  7; t->mb = 1; t->mc =  1; break;
1209 	case ATA_UDMA5: t->pa =	 3; t->pb =  7; t->mb = 1; t->mc =  1; break;
1210 	}
1211 	break;
1212     }
1213     pci_write_config(device_get_parent(ch->dev), 0x60 + (devno<<2), timing, 4);
1214 }
1215 
1216 static void
1217 hpt_timing(struct ata_channel *ch, int devno, int mode)
1218 {
1219     device_t parent = device_get_parent(ch->dev);
1220     u_int32_t timing;
1221     if (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07) {
1222 	switch (mode) {						/* HPT374 */
1223 	case ATA_PIO0:	timing = 0x0ac1f48a; break;
1224 	case ATA_PIO1:	timing = 0x0ac1f465; break;
1225 	case ATA_PIO2:	timing = 0x0a81f454; break;
1226 	case ATA_PIO3:	timing = 0x0a81f443; break;
1227 	case ATA_PIO4:	timing = 0x0a81f442; break;
1228 	case ATA_WDMA2:	timing = 0x22808242; break;
1229 	case ATA_UDMA2:	timing = 0x120c8242; break;
1230 	case ATA_UDMA4:	timing = 0x12ac8242; break;
1231 	case ATA_UDMA5:	timing = 0x12848242; break;
1232 	case ATA_UDMA6:	timing = 0x12808242; break;
1233 	default:	timing = 0x0d029d5e;
1234 	}
1235 	pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1236 	pci_write_config(parent, 0x5b,
1237 			 (pci_read_config(parent, 0x5b, 1) & 0x01) | 0x20, 1);
1238     }
1239     else if ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) ||
1240 	     (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01)) {
1241 	switch (mode) {						/* HPT372 */
1242 	case ATA_PIO0:	timing = 0x0d029d5e; break;
1243 	case ATA_PIO1:	timing = 0x0d029d26; break;
1244 	case ATA_PIO2:	timing = 0x0c829ca6; break;
1245 	case ATA_PIO3:	timing = 0x0c829c84; break;
1246 	case ATA_PIO4:	timing = 0x0c829c62; break;
1247 	case ATA_WDMA2: timing = 0x2c829262; break;
1248 	case ATA_UDMA2: timing = 0x1c91dc62; break;
1249 	case ATA_UDMA4: timing = 0x1c8ddc62; break;
1250 	case ATA_UDMA5: timing = 0x1c6ddc62; break;
1251 	case ATA_UDMA6: timing = 0x1c81dc62; break;
1252 	default:	timing = 0x0d029d5e;
1253 	}
1254 	pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1255 	pci_write_config(parent, 0x5b,
1256 			 (pci_read_config(parent, 0x5b, 1) & 0x01) | 0x20, 1);
1257     }
1258     else if (ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x03) {
1259 	switch (mode) {						/* HPT370 */
1260 	case ATA_PIO0:	timing = 0x06914e57; break;
1261 	case ATA_PIO1:	timing = 0x06914e43; break;
1262 	case ATA_PIO2:	timing = 0x06514e33; break;
1263 	case ATA_PIO3:	timing = 0x06514e22; break;
1264 	case ATA_PIO4:	timing = 0x06514e21; break;
1265 	case ATA_WDMA2: timing = 0x26514e21; break;
1266 	case ATA_UDMA2: timing = 0x16494e31; break;
1267 	case ATA_UDMA4: timing = 0x16454e31; break;
1268 	case ATA_UDMA5: timing = 0x16454e31; break;
1269 	default:	timing = 0x06514e57;
1270 	}
1271 	pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1272 	pci_write_config(parent, 0x5b, 0x22, 1);
1273     }
1274     else {							/* HPT36[68] */
1275 	switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1276 	case 0x85:	/* 25Mhz */
1277 	    switch (mode) {
1278 	    case ATA_PIO0:	timing = 0xc0d08585; break;
1279 	    case ATA_PIO1:	timing = 0xc0d08572; break;
1280 	    case ATA_PIO2:	timing = 0xc0ca8542; break;
1281 	    case ATA_PIO3:	timing = 0xc0ca8532; break;
1282 	    case ATA_PIO4:	timing = 0xc0ca8521; break;
1283 	    case ATA_WDMA2:	timing = 0xa0ca8521; break;
1284 	    case ATA_UDMA2:	timing = 0x90cf8521; break;
1285 	    case ATA_UDMA4:	timing = 0x90c98521; break;
1286 	    default:		timing = 0x01208585;
1287 	    }
1288 	    break;
1289 	default:
1290 	case 0xa7:	/* 33MHz */
1291 	    switch (mode) {
1292 	    case ATA_PIO0:	timing = 0xc0d0a7aa; break;
1293 	    case ATA_PIO1:	timing = 0xc0d0a7a3; break;
1294 	    case ATA_PIO2:	timing = 0xc0d0a753; break;
1295 	    case ATA_PIO3:	timing = 0xc0c8a742; break;
1296 	    case ATA_PIO4:	timing = 0xc0c8a731; break;
1297 	    case ATA_WDMA2:	timing = 0xa0c8a731; break;
1298 	    case ATA_UDMA2:	timing = 0x90caa731; break;
1299 	    case ATA_UDMA4:	timing = 0x90c9a731; break;
1300 	    default:		timing = 0x0120a7a7;
1301 	    }
1302 	    break;
1303 	case 0xd9:	/* 40Mhz */
1304 	    switch (mode) {
1305 	    case ATA_PIO0:	timing = 0xc018d9d9; break;
1306 	    case ATA_PIO1:	timing = 0xc010d9c7; break;
1307 	    case ATA_PIO2:	timing = 0xc010d997; break;
1308 	    case ATA_PIO3:	timing = 0xc010d974; break;
1309 	    case ATA_PIO4:	timing = 0xc008d963; break;
1310 	    case ATA_WDMA2:	timing = 0xa008d943; break;
1311 	    case ATA_UDMA2:	timing = 0x900bd943; break;
1312 	    case ATA_UDMA4:	timing = 0x900fd943; break;
1313 	    default:		timing = 0x0120d9d9;
1314 	    }
1315 	}
1316 	pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4);
1317     }
1318 }
1319