1 /*- 2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include "pci.h" 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/ata.h> 35 #include <sys/bio.h> 36 #include <sys/malloc.h> 37 #include <sys/bus.h> 38 #include <sys/disk.h> 39 #include <sys/devicestat.h> 40 #include <vm/vm.h> 41 #include <vm/pmap.h> 42 #include <pci/pcivar.h> 43 #include <machine/bus.h> 44 #include <sys/rman.h> 45 #include <dev/ata/ata-all.h> 46 47 /* prototypes */ 48 static void cyrix_timing(struct ata_softc *, int, int); 49 static void promise_timing(struct ata_softc *, int, int); 50 static void hpt_timing(struct ata_softc *, int, int); 51 52 /* misc defines */ 53 #ifdef __alpha__ 54 #undef vtophys 55 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 56 #endif 57 58 void * 59 ata_dmaalloc(struct ata_softc *scp, int device) 60 { 61 void *dmatab; 62 63 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) { 64 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 65 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 66 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 67 free(dmatab, M_DEVBUF); 68 dmatab = NULL; 69 } 70 } 71 return dmatab; 72 } 73 74 void 75 ata_dmainit(struct ata_softc *scp, int device, 76 int apiomode, int wdmamode, int udmamode) 77 { 78 device_t parent = device_get_parent(scp->dev); 79 int devno = (scp->channel << 1) + ATA_DEV(device); 80 int error; 81 82 /* set our most pessimistic default mode */ 83 scp->mode[ATA_DEV(device)] = ATA_PIO; 84 85 if (!scp->r_bmio) 86 return; 87 88 /* if simplex controller, only allow DMA on primary channel */ 89 if (scp->channel == 1) { 90 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 91 ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 92 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 93 if (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 94 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 95 return; 96 } 97 } 98 99 /* DMA engine address alignment is usually 1 word (2 bytes) */ 100 scp->alignment = 0x1; 101 102 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) { 103 ata_printf(scp, device, 104 "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 105 udmamode = 2; 106 } 107 108 switch (scp->chiptype) { 109 110 case 0x244a8086: /* Intel ICH2 mobile */ 111 case 0x244b8086: /* Intel ICH2 */ 112 if (udmamode >= 5) { 113 int32_t mask48, new48; 114 int16_t word54; 115 116 word54 = pci_read_config(parent, 0x54, 2); 117 if (word54 & (0x10 << devno)) { 118 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 119 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 120 if (bootverbose) 121 ata_printf(scp, device, 122 "%s setting UDMA5 on Intel chip\n", 123 (error) ? "failed" : "success"); 124 if (!error) { 125 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 126 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 127 pci_write_config(parent, 0x48, 128 (pci_read_config(parent, 0x48, 4) & 129 ~mask48) | new48, 4); 130 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 131 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 132 return; 133 } 134 } 135 } 136 /* make sure eventual ATA100 mode from the BIOS is disabled */ 137 pci_write_config(parent, 0x54, 138 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 139 /* FALLTHROUGH */ 140 141 case 0x24118086: /* Intel ICH */ 142 if (udmamode >= 4) { 143 int32_t mask48, new48; 144 int16_t word54; 145 146 word54 = pci_read_config(parent, 0x54, 2); 147 if (word54 & (0x10 << devno)) { 148 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 149 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 150 if (bootverbose) 151 ata_printf(scp, device, 152 "%s setting UDMA4 on Intel chip\n", 153 (error) ? "failed" : "success"); 154 if (!error) { 155 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 156 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 157 pci_write_config(parent, 0x48, 158 (pci_read_config(parent, 0x48, 4) & 159 ~mask48) | new48, 4); 160 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 161 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 162 return; 163 } 164 } 165 } 166 /* make sure eventual ATA66 mode from the BIOS is disabled */ 167 pci_write_config(parent, 0x54, 168 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 169 /* FALLTHROUGH */ 170 171 case 0x71118086: /* Intel PIIX4 */ 172 case 0x71998086: /* Intel PIIX4e */ 173 case 0x24218086: /* Intel ICH0 */ 174 if (udmamode >= 2) { 175 int32_t mask48, new48; 176 177 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 178 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 179 if (bootverbose) 180 ata_printf(scp, device, "%s setting UDMA2 on Intel chip\n", 181 (error) ? "failed" : "success"); 182 if (!error) { 183 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 184 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 185 pci_write_config(parent, 0x48, 186 (pci_read_config(parent, 0x48, 4) & 187 ~mask48) | new48, 4); 188 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 189 return; 190 } 191 } 192 /* make sure eventual ATA33 mode from the BIOS is disabled */ 193 pci_write_config(parent, 0x48, 194 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 195 /* FALLTHROUGH */ 196 197 case 0x70108086: /* Intel PIIX3 */ 198 if (wdmamode >= 2 && apiomode >= 4) { 199 int32_t mask40, new40, mask44, new44; 200 201 /* if SITRE not set doit for both channels */ 202 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 203 new40 = pci_read_config(parent, 0x40, 4); 204 new44 = pci_read_config(parent, 0x44, 4); 205 if (!(new40 & 0x00004000)) { 206 new44 &= ~0x0000000f; 207 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 208 } 209 if (!(new40 & 0x40000000)) { 210 new44 &= ~0x000000f0; 211 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 212 } 213 new40 |= 0x40004000; 214 pci_write_config(parent, 0x40, new40, 4); 215 pci_write_config(parent, 0x44, new44, 4); 216 } 217 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 218 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 219 if (bootverbose) 220 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n", 221 (error) ? "failed" : "success"); 222 if (!error) { 223 if (device == ATA_MASTER) { 224 mask40 = 0x0000330f; 225 new40 = 0x00002307; 226 mask44 = 0; 227 new44 = 0; 228 } 229 else { 230 mask40 = 0x000000f0; 231 new40 = 0x00000070; 232 mask44 = 0x0000000f; 233 new44 = 0x0000000b; 234 } 235 if (scp->channel) { 236 mask40 <<= 16; 237 new40 <<= 16; 238 mask44 <<= 4; 239 new44 <<= 4; 240 } 241 pci_write_config(parent, 0x40, 242 (pci_read_config(parent, 0x40, 4) & ~mask40)| 243 new40, 4); 244 pci_write_config(parent, 0x44, 245 (pci_read_config(parent, 0x44, 4) & ~mask44)| 246 new44, 4); 247 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 248 return; 249 } 250 } 251 /* we could set PIO mode timings, but we assume the BIOS did that */ 252 break; 253 254 case 0x12308086: /* Intel PIIX */ 255 if (wdmamode >= 2 && apiomode >= 4) { 256 int32_t word40; 257 258 word40 = pci_read_config(parent, 0x40, 4); 259 word40 >>= scp->channel * 16; 260 261 /* Check for timing config usable for DMA on controller */ 262 if (!((word40 & 0x3300) == 0x2300 && 263 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 264 break; 265 266 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 267 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 268 if (bootverbose) 269 ata_printf(scp, device, 270 "%s setting WDMA2 on Intel chip\n", 271 (error) ? "failed" : "success"); 272 if (!error) { 273 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 274 return; 275 } 276 } 277 break; 278 279 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 280 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 281 if (pci_get_revid(parent) < 0xC2 && 282 scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 283 ata_printf(scp, device, 284 "Aladdin: two atapi devices on this channel, no DMA\n"); 285 break; 286 } 287 if (udmamode >= 5 && pci_get_revid(parent) >= 0xC4) { 288 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 289 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 290 if (bootverbose) 291 ata_printf(scp, device, 292 "%s setting UDMA5 on Acer chip\n", 293 (error) ? "failed" : "success"); 294 if (!error) { 295 int32_t word54 = pci_read_config(parent, 0x54, 4); 296 297 pci_write_config(parent, 0x4b, 298 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 299 word54 &= ~(0x000f000f << (devno << 2)); 300 word54 |= (0x000f0005 << (devno << 2)); 301 pci_write_config(parent, 0x54, word54, 4); 302 pci_write_config(parent, 0x53, 303 pci_read_config(parent, 0x53, 1) | 0x03, 1); 304 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 305 return; 306 } 307 } 308 if (udmamode >= 4 && pci_get_revid(parent) >= 0xC2) { 309 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 310 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 311 if (bootverbose) 312 ata_printf(scp, device, 313 "%s setting UDMA4 on Acer chip\n", 314 (error) ? "failed" : "success"); 315 if (!error) { 316 int32_t word54 = pci_read_config(parent, 0x54, 4); 317 318 pci_write_config(parent, 0x4b, 319 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 320 word54 &= ~(0x000f000f << (devno << 2)); 321 word54 |= (0x00080005 << (devno << 2)); 322 pci_write_config(parent, 0x54, word54, 4); 323 pci_write_config(parent, 0x53, 324 pci_read_config(parent, 0x53, 1) | 0x03, 1); 325 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 326 return; 327 } 328 } 329 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 330 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 331 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 332 if (bootverbose) 333 ata_printf(scp, device, 334 "%s setting UDMA2 on Acer chip\n", 335 (error) ? "failed" : "success"); 336 if (!error) { 337 int32_t word54 = pci_read_config(parent, 0x54, 4); 338 339 word54 &= ~(0x000f000f << (devno << 2)); 340 word54 |= (0x000a0005 << (devno << 2)); 341 pci_write_config(parent, 0x54, word54, 4); 342 pci_write_config(parent, 0x53, 343 pci_read_config(parent, 0x53, 1) | 0x03, 1); 344 scp->flags |= ATA_ATAPI_DMA_RO; 345 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 346 return; 347 } 348 } 349 350 /* make sure eventual UDMA mode from the BIOS is disabled */ 351 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 352 ~(0x0008 << (devno << 2)), 2); 353 354 if (wdmamode >= 2 && apiomode >= 4) { 355 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 356 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 357 if (bootverbose) 358 ata_printf(scp, device, 359 "%s setting WDMA2 on Acer chip\n", 360 (error) ? "failed" : "success"); 361 if (!error) { 362 pci_write_config(parent, 0x53, 363 pci_read_config(parent, 0x53, 1) | 0x03, 1); 364 scp->flags |= ATA_ATAPI_DMA_RO; 365 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 366 return; 367 } 368 } 369 pci_write_config(parent, 0x53, 370 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 371 /* we could set PIO mode timings, but we assume the BIOS did that */ 372 break; 373 374 case 0x74091022: /* AMD 756 */ 375 if (udmamode >= 4) { 376 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 377 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 378 if (bootverbose) 379 ata_printf(scp, device, 380 "%s setting UDMA4 on AMD chip\n", 381 (error) ? "failed" : "success"); 382 if (!error) { 383 pci_write_config(parent, 0x53 - devno, 0xc3, 1); 384 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 385 return; 386 } 387 } 388 goto via_82c586; 389 390 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 391 if (ata_find_dev(parent, 0x06861106, 0x40)) { /* 82C686b */ 392 if (udmamode >= 5) { 393 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 394 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 395 if (bootverbose) 396 ata_printf(scp, device, 397 "%s setting UDMA5 on VIA chip\n", 398 (error) ? "failed" : "success"); 399 if (!error) { 400 pci_write_config(parent, 0x53 - devno, 0xf0, 1); 401 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 402 return; 403 } 404 } 405 if (udmamode >= 4) { 406 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 407 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 408 if (bootverbose) 409 ata_printf(scp, device, 410 "%s setting UDMA4 on VIA chip\n", 411 (error) ? "failed" : "success"); 412 if (!error) { 413 pci_write_config(parent, 0x53 - devno, 0xf1, 1); 414 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 415 return; 416 } 417 } 418 if (udmamode >= 2) { 419 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 420 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 421 if (bootverbose) 422 ata_printf(scp, device, 423 "%s setting UDMA2 on VIA chip\n", 424 (error) ? "failed" : "success"); 425 if (!error) { 426 pci_write_config(parent, 0x53 - devno, 0xf4, 1); 427 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 428 return; 429 } 430 } 431 } 432 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 433 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 434 if (udmamode >= 4) { 435 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 436 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 437 if (bootverbose) 438 ata_printf(scp, device, 439 "%s setting UDMA4 on VIA chip\n", 440 (error) ? "failed" : "success"); 441 if (!error) { 442 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 443 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 444 return; 445 } 446 } 447 if (udmamode >= 2) { 448 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 449 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 450 if (bootverbose) 451 ata_printf(scp, device, 452 "%s setting UDMA2 on VIA chip\n", 453 (error) ? "failed" : "success"); 454 if (!error) { 455 pci_write_config(parent, 0x53 - devno, 0xea, 1); 456 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 457 return; 458 } 459 } 460 } 461 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 462 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 463 via_82c586: 464 if (udmamode >= 2) { 465 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 466 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 467 if (bootverbose) 468 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 469 (error) ? "failed" : "success", 470 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 471 if (!error) { 472 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 473 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 474 return; 475 } 476 } 477 } 478 if (wdmamode >= 2 && apiomode >= 4) { 479 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 480 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 481 if (bootverbose) 482 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 483 (error) ? "failed" : "success", 484 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 485 if (!error) { 486 pci_write_config(parent, 0x53 - devno, 0x82, 1); 487 pci_write_config(parent, 0x4b - devno, 0x31, 1); 488 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 489 return; 490 } 491 } 492 /* we could set PIO mode timings, but we assume the BIOS did that */ 493 break; 494 495 case 0x55131039: /* SiS 5591 */ 496 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 497 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 498 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 499 if (bootverbose) 500 ata_printf(scp, device, 501 "%s setting UDMA2 on SiS chip\n", 502 (error) ? "failed" : "success"); 503 if (!error) { 504 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 505 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 506 return; 507 } 508 } 509 if (wdmamode >=2 && apiomode >= 4) { 510 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 511 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 512 if (bootverbose) 513 ata_printf(scp, device, 514 "%s setting WDMA2 on SiS chip\n", 515 (error) ? "failed" : "success"); 516 if (!error) { 517 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 518 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 519 return; 520 } 521 } 522 /* we could set PIO mode timings, but we assume the BIOS did that */ 523 break; 524 525 case 0x06491095: /* CMD 649 ATA100 controller */ 526 if (udmamode >= 5) { 527 u_int8_t umode; 528 529 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 530 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 531 if (bootverbose) 532 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 533 (error) ? "failed" : "success"); 534 if (!error) { 535 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 536 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 537 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 538 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 539 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 540 return; 541 } 542 } 543 /* FALLTHROUGH */ 544 545 case 0x06481095: /* CMD 648 ATA66 controller */ 546 if (udmamode >= 4) { 547 u_int8_t umode; 548 549 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 550 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 551 if (bootverbose) 552 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 553 (error) ? "failed" : "success"); 554 if (!error) { 555 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 556 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 557 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 558 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 559 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 560 return; 561 } 562 } 563 if (udmamode >= 2) { 564 u_int8_t umode; 565 566 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 567 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 568 if (bootverbose) 569 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 570 (error) ? "failed" : "success"); 571 if (!error) { 572 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 573 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 574 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 575 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 576 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 577 return; 578 } 579 } 580 /* make sure eventual UDMA mode from the BIOS is disabled */ 581 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 582 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 583 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 584 /* FALLTHROUGH */ 585 586 case 0x06461095: /* CMD 646 ATA controller */ 587 if (wdmamode >= 2 && apiomode >= 4) { 588 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 589 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 590 if (bootverbose) 591 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 592 error ? "failed" : "success"); 593 if (!error) { 594 int32_t offset = (devno < 3) ? (devno << 1) : 7; 595 596 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 597 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 598 return; 599 } 600 } 601 /* we could set PIO mode timings, but we assume the BIOS did that */ 602 break; 603 604 case 0xc6931080: /* Cypress 82c693 ATA controller */ 605 if (wdmamode >= 2 && apiomode >= 4) { 606 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 607 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 608 if (bootverbose) 609 ata_printf(scp, device, 610 "%s setting WDMA2 on Cypress chip\n", 611 error ? "failed" : "success"); 612 if (!error) { 613 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 614 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 615 return; 616 } 617 } 618 /* we could set PIO mode timings, but we assume the BIOS did that */ 619 break; 620 621 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 622 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 623 if (udmamode >= 2) { 624 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 625 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 626 if (bootverbose) 627 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 628 (error) ? "failed" : "success"); 629 if (!error) { 630 cyrix_timing(scp, devno, ATA_UDMA2); 631 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 632 return; 633 } 634 } 635 if (wdmamode >= 2 && apiomode >= 4) { 636 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 637 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 638 if (bootverbose) 639 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 640 (error) ? "failed" : "success"); 641 if (!error) { 642 cyrix_timing(scp, devno, ATA_WDMA2); 643 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 644 return; 645 } 646 } 647 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 648 ata_pio2mode(apiomode), ATA_C_F_SETXFER, 649 ATA_WAIT_READY); 650 if (bootverbose) 651 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 652 (error) ? "failed" : "success", 653 ata_mode2str(ata_pio2mode(apiomode))); 654 cyrix_timing(scp, devno, ata_pio2mode(apiomode)); 655 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 656 return; 657 658 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 659 if (udmamode >= 2) { 660 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 661 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 662 if (bootverbose) 663 ata_printf(scp, device, 664 "%s setting UDMA2 on ServerWorks chip\n", 665 (error) ? "failed" : "success"); 666 if (!error) { 667 u_int16_t reg56; 668 669 pci_write_config(parent, 0x54, 670 pci_read_config(parent, 0x54, 1) | 671 (0x01 << devno), 1); 672 reg56 = pci_read_config(parent, 0x56, 2); 673 reg56 &= ~(0xf << (devno * 4)); 674 reg56 |= (0x2 << (devno * 4)); 675 pci_write_config(parent, 0x56, reg56, 2); 676 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 677 return; 678 } 679 } 680 if (wdmamode >= 2 && apiomode >= 4) { 681 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 682 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 683 if (bootverbose) 684 ata_printf(scp, device, 685 "%s setting WDMA2 on ServerWorks chip\n", 686 (error) ? "failed" : "success"); 687 if (!error) { 688 int offset = (scp->channel * 2) + (device == ATA_MASTER); 689 int word44 = pci_read_config(parent, 0x44, 4); 690 691 pci_write_config(parent, 0x54, 692 pci_read_config(parent, 0x54, 1) & 693 ~(0x01 << devno), 1); 694 word44 &= ~(0xff << (offset << 8)); 695 word44 |= (0x20 << (offset << 8)); 696 pci_write_config(parent, 0x44, 0x20, 4); 697 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 698 return; 699 } 700 } 701 /* we could set PIO mode timings, but we assume the BIOS did that */ 702 break; 703 704 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 705 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 706 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 707 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 708 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 709 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 710 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 711 break; 712 713 if (udmamode >= 5 && 714 (scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 715 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 716 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 717 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 718 if (bootverbose) 719 ata_printf(scp, device, 720 "%s setting UDMA5 on Promise chip\n", 721 (error) ? "failed" : "success"); 722 if (!error) { 723 promise_timing(scp, devno, ATA_UDMA5); 724 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 725 return; 726 } 727 } 728 if (udmamode >= 4 && (scp->chiptype == 0x4d38105a || 729 scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 730 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 731 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 732 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 733 if (bootverbose) 734 ata_printf(scp, device, 735 "%s setting UDMA4 on Promise chip\n", 736 (error) ? "failed" : "success"); 737 if (!error) { 738 promise_timing(scp, devno, ATA_UDMA4); 739 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 740 return; 741 } 742 } 743 if (udmamode >= 2) { 744 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 745 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 746 if (bootverbose) 747 ata_printf(scp, device, 748 "%s setting UDMA2 on Promise chip\n", 749 (error) ? "failed" : "success"); 750 if (!error) { 751 promise_timing(scp, devno, ATA_UDMA2); 752 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 753 return; 754 } 755 } 756 if (wdmamode >= 2 && apiomode >= 4) { 757 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 758 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 759 if (bootverbose) 760 ata_printf(scp, device, 761 "%s setting WDMA2 on Promise chip\n", 762 (error) ? "failed" : "success"); 763 if (!error) { 764 promise_timing(scp, devno, ATA_WDMA2); 765 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 766 return; 767 } 768 } 769 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 770 ata_pio2mode(apiomode), 771 ATA_C_F_SETXFER, ATA_WAIT_READY); 772 if (bootverbose) 773 ata_printf(scp, device, 774 "%s setting PIO%d on Promise chip\n", 775 (error) ? "failed" : "success", 776 (apiomode >= 0) ? apiomode : 0); 777 promise_timing(scp, devno, ata_pio2mode(apiomode)); 778 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 779 return; 780 781 case 0x00041103: /* HighPoint HPT366/368/370 controllers */ 782 /* no ATAPI devices for now */ 783 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 784 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 785 break; 786 787 if (udmamode >=5 && pci_get_revid(parent) >= 0x03 && 788 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 789 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 790 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 791 if (bootverbose) 792 ata_printf(scp, device, 793 "%s setting UDMA5 on HighPoint chip\n", 794 (error) ? "failed" : "success"); 795 if (!error) { 796 hpt_timing(scp, devno, ATA_UDMA5); 797 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 798 return; 799 } 800 } 801 if (udmamode >=4 && 802 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 803 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 804 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 805 if (bootverbose) 806 ata_printf(scp, device, 807 "%s setting UDMA4 on HighPoint chip\n", 808 (error) ? "failed" : "success"); 809 if (!error) { 810 hpt_timing(scp, devno, ATA_UDMA4); 811 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 812 return; 813 } 814 } 815 if (udmamode >= 2) { 816 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 817 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 818 if (bootverbose) 819 ata_printf(scp, device, 820 "%s setting UDMA2 on HighPoint chip\n", 821 (error) ? "failed" : "success"); 822 if (!error) { 823 hpt_timing(scp, devno, ATA_UDMA2); 824 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 825 return; 826 } 827 } 828 if (wdmamode >= 2 && apiomode >= 4) { 829 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 830 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 831 if (bootverbose) 832 ata_printf(scp, device, 833 "%s setting WDMA2 on HighPoint chip\n", 834 (error) ? "failed" : "success"); 835 if (!error) { 836 hpt_timing(scp, devno, ATA_WDMA2); 837 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 838 return; 839 } 840 } 841 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 842 ata_pio2mode(apiomode), 843 ATA_C_F_SETXFER, ATA_WAIT_READY); 844 if (bootverbose) 845 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 846 (error) ? "failed" : "success", 847 (apiomode >= 0) ? apiomode : 0); 848 hpt_timing(scp, devno, ata_pio2mode(apiomode)); 849 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 850 return; 851 852 default: /* unknown controller chip */ 853 /* better not try generic DMA on ATAPI devices it almost never works */ 854 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 855 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 856 break; 857 858 /* if controller says its setup for DMA take the easy way out */ 859 /* the downside is we dont know what DMA mode we are in */ 860 if ((udmamode >= 0 || wdmamode > 1) && 861 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 862 ((device==ATA_MASTER) ? 863 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 864 scp->mode[ATA_DEV(device)] = ATA_DMA; 865 return; 866 } 867 868 /* well, we have no support for this, but try anyways */ 869 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) { 870 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 871 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 872 if (bootverbose) 873 ata_printf(scp, device, 874 "%s setting WDMA2 on generic chip\n", 875 (error) ? "failed" : "success"); 876 if (!error) { 877 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 878 return; 879 } 880 } 881 } 882 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 883 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 884 if (bootverbose) 885 ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 886 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 887 if (!error) 888 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 889 else { 890 if (bootverbose) 891 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 892 scp->mode[ATA_DEV(device)] = ATA_PIO; 893 } 894 } 895 896 int 897 ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 898 caddr_t data, int32_t count) 899 { 900 u_int32_t dma_count, dma_base; 901 int i = 0; 902 903 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 904 ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 905 return -1; 906 } 907 908 if (!count) { 909 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 910 return -1; 911 } 912 913 dma_base = vtophys(data); 914 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 915 data += dma_count; 916 count -= dma_count; 917 918 while (count) { 919 dmatab[i].base = dma_base; 920 dmatab[i].count = (dma_count & 0xffff); 921 i++; 922 if (i >= ATA_DMA_ENTRIES) { 923 ata_printf(scp, device, "too many segments in DMA table\n"); 924 return -1; 925 } 926 dma_base = vtophys(data); 927 dma_count = min(count, PAGE_SIZE); 928 data += min(count, PAGE_SIZE); 929 count -= min(count, PAGE_SIZE); 930 } 931 dmatab[i].base = dma_base; 932 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 933 return 0; 934 } 935 936 void 937 ata_dmastart(struct ata_softc *scp, int device, 938 struct ata_dmaentry *dmatab, int dir) 939 { 940 scp->flags |= ATA_DMA_ACTIVE; 941 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab)); 942 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 943 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 944 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) | 945 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 946 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 947 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 948 } 949 950 int 951 ata_dmadone(struct ata_softc *scp) 952 { 953 int error; 954 955 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 956 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 957 scp->flags &= ~ATA_DMA_ACTIVE; 958 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT); 959 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 960 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 961 return error & ATA_BMSTAT_MASK; 962 } 963 964 int 965 ata_dmastatus(struct ata_softc *scp) 966 { 967 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 968 } 969 970 static void 971 cyrix_timing(struct ata_softc *scp, int devno, int mode) 972 { 973 u_int32_t reg20 = 0x0000e132; 974 u_int32_t reg24 = 0x00017771; 975 976 switch (mode) { 977 case ATA_PIO0: reg20 = 0x0000e132; break; 978 case ATA_PIO1: reg20 = 0x00018121; break; 979 case ATA_PIO2: reg20 = 0x00024020; break; 980 case ATA_PIO3: reg20 = 0x00032010; break; 981 case ATA_PIO4: reg20 = 0x00040010; break; 982 case ATA_WDMA2: reg24 = 0x00002020; break; 983 case ATA_UDMA2: reg24 = 0x00911030; break; 984 } 985 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20); 986 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24); 987 } 988 989 static void 990 promise_timing(struct ata_softc *scp, int devno, int mode) 991 { 992 u_int32_t timing = 0; 993 struct promise_timing { 994 u_int8_t pa:4; 995 u_int8_t prefetch:1; 996 u_int8_t iordy:1; 997 u_int8_t errdy:1; 998 u_int8_t syncin:1; 999 u_int8_t pb:5; 1000 u_int8_t mb:3; 1001 u_int8_t mc:4; 1002 u_int8_t dmaw:1; 1003 u_int8_t dmar:1; 1004 u_int8_t iordyp:1; 1005 u_int8_t dmarqp:1; 1006 u_int8_t reserved:8; 1007 } *t = (struct promise_timing*)&timing; 1008 1009 t->iordy = 1; t->iordyp = 1; 1010 if (mode >= ATA_DMA) { 1011 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1012 } 1013 1014 switch (scp->chiptype) { 1015 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1016 switch (mode) { 1017 default: 1018 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1019 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1020 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1021 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1022 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1023 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1024 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1025 } 1026 break; 1027 1028 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1029 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1030 case 0x0d30105a: /* Promise OEM ATA 100 */ 1031 switch (mode) { 1032 default: 1033 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1034 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1035 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1036 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1037 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1038 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1039 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1040 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1041 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1042 } 1043 break; 1044 } 1045 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 1046 } 1047 1048 static void 1049 hpt_timing(struct ata_softc *scp, int devno, int mode) 1050 { 1051 device_t parent = device_get_parent(scp->dev); 1052 u_int32_t timing; 1053 1054 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 1055 switch (mode) { 1056 case ATA_PIO0: timing = 0x06914e57; break; 1057 case ATA_PIO1: timing = 0x06914e43; break; 1058 case ATA_PIO2: timing = 0x06514e33; break; 1059 case ATA_PIO3: timing = 0x06514e22; break; 1060 case ATA_PIO4: timing = 0x06514e21; break; 1061 case ATA_WDMA2: timing = 0x26514e21; break; 1062 case ATA_UDMA2: timing = 0x16494e31; break; 1063 case ATA_UDMA4: timing = 0x16454e31; break; 1064 case ATA_UDMA5: timing = 0x16454e31; break; 1065 default: timing = 0x06514e57; 1066 } 1067 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1068 pci_write_config(parent, 0x5b, 0x22, 1); 1069 } 1070 else { /* HPT36[68] */ 1071 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1072 case 0x85: /* 25Mhz */ 1073 switch (mode) { 1074 case ATA_PIO0: timing = 0xc0d08585; break; 1075 case ATA_PIO1: timing = 0xc0d08572; break; 1076 case ATA_PIO2: timing = 0xc0ca8542; break; 1077 case ATA_PIO3: timing = 0xc0ca8532; break; 1078 case ATA_PIO4: timing = 0xc0ca8521; break; 1079 case ATA_WDMA2: timing = 0xa0ca8521; break; 1080 case ATA_UDMA2: timing = 0x90cf8521; break; 1081 case ATA_UDMA4: timing = 0x90c98521; break; 1082 default: timing = 0x01208585; 1083 } 1084 break; 1085 default: 1086 case 0xa7: /* 33MHz */ 1087 switch (mode) { 1088 case ATA_PIO0: timing = 0xc0d0a7aa; break; 1089 case ATA_PIO1: timing = 0xc0d0a7a3; break; 1090 case ATA_PIO2: timing = 0xc0d0a753; break; 1091 case ATA_PIO3: timing = 0xc0c8a742; break; 1092 case ATA_PIO4: timing = 0xc0c8a731; break; 1093 case ATA_WDMA2: timing = 0xa0c8a731; break; 1094 case ATA_UDMA2: timing = 0x90caa731; break; 1095 case ATA_UDMA4: timing = 0x90c9a731; break; 1096 default: timing = 0x0120a7a7; 1097 } 1098 break; 1099 case 0xd9: /* 40Mhz */ 1100 switch (mode) { 1101 case ATA_PIO0: timing = 0xc018d9d9; break; 1102 case ATA_PIO1: timing = 0xc010d9c7; break; 1103 case ATA_PIO2: timing = 0xc010d997; break; 1104 case ATA_PIO3: timing = 0xc010d974; break; 1105 case ATA_PIO4: timing = 0xc008d963; break; 1106 case ATA_WDMA2: timing = 0xa008d943; break; 1107 case ATA_UDMA2: timing = 0x900bd943; break; 1108 case ATA_UDMA4: timing = 0x900fd943; break; 1109 default: timing = 0x0120d9d9; 1110 } 1111 } 1112 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 1113 } 1114 } 1115