1 /*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include "pci.h" 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/buf.h> 35 #include <sys/malloc.h> 36 #include <sys/bus.h> 37 #include <sys/disk.h> 38 #include <sys/devicestat.h> 39 #include <vm/vm.h> 40 #include <vm/pmap.h> 41 #if NPCI > 0 42 #include <pci/pcivar.h> 43 #endif 44 #include <dev/ata/ata-all.h> 45 #include <dev/ata/ata-disk.h> 46 47 #if NPCI > 0 48 49 /* prototypes */ 50 static void promise_timing(struct ata_softc *, int32_t, int32_t); 51 static void hpt366_timing(struct ata_softc *, int32_t, int32_t); 52 53 /* misc defines */ 54 #ifdef __alpha__ 55 #undef vtophys 56 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 57 #endif 58 59 void 60 ata_dmainit(struct ata_softc *scp, int32_t device, 61 int32_t apiomode, int32_t wdmamode, int32_t udmamode) 62 { 63 device_t parent = device_get_parent(scp->dev); 64 int32_t devno = (scp->unit << 1) + ATA_DEV(device); 65 int32_t error; 66 67 /* set our most pessimistic default mode */ 68 scp->mode[ATA_DEV(device)] = ATA_PIO; 69 70 if (!scp->bmaddr) 71 return; 72 73 /* if simplex controller, only allow DMA on primary channel */ 74 if (scp->unit == 1) { 75 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 76 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 77 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 78 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 79 return; 80 } 81 } 82 83 if (!scp->dmatab[ATA_DEV(device)]) { 84 void *dmatab; 85 86 if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) 87 return; 88 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 89 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 90 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 91 free(dmatab, M_DEVBUF); 92 return; 93 } 94 scp->dmatab[ATA_DEV(device)] = dmatab; 95 } 96 97 switch (scp->chiptype) { 98 99 case 0x24118086: /* Intel ICH */ 100 if (udmamode >= 4) { 101 int32_t mask48, new48; 102 int16_t word54; 103 104 word54 = pci_read_config(parent, 0x54, 2); 105 if (word54 & (0x10 << devno)) { 106 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 107 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 108 if (bootverbose) 109 ata_printf(scp, device, 110 "%s setting up UDMA4 mode on ICH chip\n", 111 (error) ? "failed" : "success"); 112 if (!error) { 113 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 114 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 115 pci_write_config(parent, 0x48, 116 (pci_read_config(parent, 0x48, 4) & 117 ~mask48) | new48, 4); 118 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 119 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 120 return; 121 } 122 } 123 } 124 /* FALLTHROUGH */ 125 126 case 0x71118086: /* Intel PIIX4 */ 127 case 0x71998086: /* Intel PIIX4e */ 128 case 0x24218086: /* Intel ICH0 */ 129 if (udmamode >= 2) { 130 int32_t mask48, new48; 131 132 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 133 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 134 if (bootverbose) 135 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 136 (error) ? "failed" : "success", 137 (scp->chiptype == 0x24118086) ? "ICH" : 138 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 139 if (!error) { 140 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 141 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 142 pci_write_config(parent, 0x48, 143 (pci_read_config(parent, 0x48, 4) & 144 ~mask48) | new48, 4); 145 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 146 return; 147 } 148 } 149 /* FALLTHROUGH */ 150 151 case 0x70108086: /* Intel PIIX3 */ 152 if (wdmamode >= 2 && apiomode >= 4) { 153 int32_t mask40, new40, mask44, new44; 154 155 /* if SITRE not set doit for both channels */ 156 if (!((pci_read_config(parent, 0x40, 4)>>(scp->unit<<8))&0x4000)){ 157 new40 = pci_read_config(parent, 0x40, 4); 158 new44 = pci_read_config(parent, 0x44, 4); 159 if (!(new40 & 0x00004000)) { 160 new44 &= ~0x0000000f; 161 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 162 } 163 if (!(new40 & 0x40000000)) { 164 new44 &= ~0x000000f0; 165 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 166 } 167 new40 |= 0x40004000; 168 pci_write_config(parent, 0x40, new40, 4); 169 pci_write_config(parent, 0x44, new44, 4); 170 } 171 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 172 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 173 if (bootverbose) 174 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 175 (error) ? "failed" : "success", 176 (scp->chiptype == 0x70108086) ? "PIIX3" : 177 (scp->chiptype == 0x24118086) ? "ICH" : 178 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 179 if (!error) { 180 if (device == ATA_MASTER) { 181 mask40 = 0x0000330f; 182 new40 = 0x00002307; 183 mask44 = 0; 184 new44 = 0; 185 } 186 else { 187 mask40 = 0x000000f0; 188 new40 = 0x00000070; 189 mask44 = 0x0000000f; 190 new44 = 0x0000000b; 191 } 192 if (scp->unit) { 193 mask40 <<= 16; 194 new40 <<= 16; 195 mask44 <<= 4; 196 new44 <<= 4; 197 } 198 pci_write_config(parent, 0x40, 199 (pci_read_config(parent, 0x40, 4) & ~mask40)| 200 new40, 4); 201 pci_write_config(parent, 0x44, 202 (pci_read_config(parent, 0x44, 4) & ~mask44)| 203 new44, 4); 204 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 205 return; 206 } 207 } 208 /* we could set PIO mode timings, but we assume the BIOS did that */ 209 break; 210 211 case 0x12308086: /* Intel PIIX */ 212 if (wdmamode >= 2 && apiomode >= 4) { 213 int32_t word40; 214 215 word40 = pci_read_config(parent, 0x40, 4); 216 word40 >>= scp->unit * 16; 217 218 /* Check for timing config usable for DMA on controller */ 219 if (!((word40 & 0x3300) == 0x2300 && 220 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 221 break; 222 223 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 224 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 225 if (bootverbose) 226 ata_printf(scp, device, 227 "%s setting up WDMA2 mode on PIIX chip\n", 228 (error) ? "failed" : "success"); 229 if (!error) { 230 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 231 return; 232 } 233 } 234 break; 235 236 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 237 /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 238 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 239 ata_printf(scp, device, 240 "Aladdin: two atapi devices on this channel, no DMA\n"); 241 break; 242 } 243 if (udmamode >= 2) { 244 int32_t word54 = pci_read_config(parent, 0x54, 4); 245 246 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 247 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 248 if (bootverbose) 249 ata_printf(scp, device, 250 "%s setting up UDMA2 mode on Aladdin chip\n", 251 (error) ? "failed" : "success"); 252 if (!error) { 253 word54 |= 0x5555; 254 word54 |= (0x0a << (16 + (scp->unit << 3) + (device << 2))); 255 pci_write_config(parent, 0x54, word54, 4); 256 pci_write_config(parent, 0x53, 257 pci_read_config(parent, 0x53, 1) | 0x03, 1); 258 scp->flags |= ATA_ATAPI_DMA_RO; 259 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 260 return; 261 } 262 } 263 if (wdmamode >= 2 && apiomode >= 4) { 264 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 265 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 266 if (bootverbose) 267 ata_printf(scp, device, 268 "%s setting up WDMA2 mode on Aladdin chip\n", 269 (error) ? "failed" : "success"); 270 if (!error) { 271 pci_write_config(parent, 0x53, 272 pci_read_config(parent, 0x53, 1) | 0x03, 1); 273 scp->flags |= ATA_ATAPI_DMA_RO; 274 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 275 return; 276 } 277 } 278 /* we could set PIO mode timings, but we assume the BIOS did that */ 279 break; 280 281 case 0x06861106: /* VIA 82C686 */ 282 if (udmamode >= 4) { 283 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 284 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 285 if (bootverbose) 286 ata_printf(scp, device, 287 "%s setting up UDMA4 mode on VIA chip\n", 288 (error) ? "failed" : "success"); 289 if (!error) { 290 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 291 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 292 return; 293 } 294 } 295 if (udmamode >= 2) { 296 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 297 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 298 if (bootverbose) 299 ata_printf(scp, device, 300 "%s setting up UDMA2 mode on VIA chip\n", 301 (error) ? "failed" : "success"); 302 if (!error) { 303 pci_write_config(parent, 0x53 - devno, 0xea, 1); 304 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 305 return; 306 } 307 } 308 goto via_generic; 309 310 case 0x74091022: /* AMD 756 */ 311 if (udmamode >= 4) { 312 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 313 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 314 if (bootverbose) 315 ata_printf(scp, device, 316 "%s setting up UDMA4 mode on AMD chip\n", 317 (error) ? "failed" : "success"); 318 if (!error) { 319 pci_write_config(parent, 0x53 - devno, 0xc3, 1); 320 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 321 return; 322 } 323 } 324 /* FALLTHROUGH */ 325 326 case 0x05961106: /* VIA 82C596 */ 327 case 0x05861106: /* VIA 82C586 */ 328 329 /* UDMA2 mode only on 82C586 > rev1, 82C596, AMD 756 */ 330 if ((udmamode >= 2 && scp->chiptype == 0x05861106 && 331 pci_read_config(scp->dev, 0x08, 1) >= 0x01) || 332 (udmamode >= 2 && scp->chiptype == 0x05961106) || 333 (udmamode >= 2 && scp->chiptype == 0x74091022)) { 334 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 335 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 336 if (bootverbose) 337 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 338 (error) ? "failed" : "success", 339 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 340 if (!error) { 341 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 342 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 343 return; 344 } 345 } 346 /* FALLTHROUGH */ 347 348 case 0x05711106: /* VIA 82C571 */ 349 via_generic: 350 if (wdmamode >= 2 && apiomode >= 4) { 351 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 352 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 353 if (bootverbose) 354 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 355 (error) ? "failed" : "success", 356 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 357 if (!error) { 358 pci_write_config(parent, 0x53 - devno, 0x82, 1); 359 pci_write_config(parent, 0x4b - devno, 0x31, 1); 360 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 361 return; 362 } 363 } 364 /* we could set PIO mode timings, but we assume the BIOS did that */ 365 break; 366 367 case 0x55131039: /* SiS 5591 */ 368 if (udmamode >= 2) { 369 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 370 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 371 if (bootverbose) 372 ata_printf(scp, device, 373 "%s setting up UDMA2 mode on SiS chip\n", 374 (error) ? "failed" : "success"); 375 if (!error) { 376 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 377 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 378 return; 379 } 380 } 381 if (wdmamode >=2 && apiomode >= 4) { 382 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 383 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 384 if (bootverbose) 385 ata_printf(scp, device, 386 "%s setting up WDMA2 mode on SiS chip\n", 387 (error) ? "failed" : "success"); 388 if (!error) { 389 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 390 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 391 return; 392 } 393 } 394 /* we could set PIO mode timings, but we assume the BIOS did that */ 395 break; 396 397 case 0x06461095: /* CMD 646 ATA controller */ 398 if (wdmamode >= 2 && apiomode >= 4) { 399 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 400 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 401 if (bootverbose) 402 ata_printf(scp, device, 403 "%s setting up WDMA2 mode on CMD646 chip\n", 404 error ? "failed" : "success"); 405 if (!error) { 406 int32_t offset = (devno < 3) ? (devno << 1) : 7; 407 408 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 409 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 410 return; 411 } 412 } 413 /* we could set PIO mode timings, but we assume the BIOS did that */ 414 break; 415 416 case 0xc6931080: /* Cypress 82c693 ATA controller */ 417 if (wdmamode >= 2 && apiomode >= 4) { 418 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 419 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 420 if (bootverbose) 421 ata_printf(scp, device, 422 "%s setting up WDMA2 mode on Cypress chip\n", 423 error ? "failed" : "success"); 424 if (!error) { 425 pci_write_config(scp->dev, scp->unit ? 0x4e : 0x4c, 0x2020, 2); 426 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 427 return; 428 } 429 } 430 /* we could set PIO mode timings, but we assume the BIOS did that */ 431 break; 432 433 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */ 434 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */ 435 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 436 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 437 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 438 break; 439 440 if (udmamode >=4 && scp->chiptype == 0x4d38105a && 441 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 442 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 443 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 444 if (bootverbose) 445 ata_printf(scp, device, 446 "%s setting up UDMA4 mode on Promise chip\n", 447 (error) ? "failed" : "success"); 448 if (!error) { 449 promise_timing(scp, devno, ATA_UDMA4); 450 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 451 return; 452 } 453 } 454 if (udmamode >= 2) { 455 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 456 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 457 if (bootverbose) 458 ata_printf(scp, device, 459 "%s setting up UDMA2 mode on Promise chip\n", 460 (error) ? "failed" : "success"); 461 if (!error) { 462 promise_timing(scp, devno, ATA_UDMA2); 463 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 464 return; 465 } 466 } 467 if (wdmamode >= 2 && apiomode >= 4) { 468 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 469 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 470 if (bootverbose) 471 ata_printf(scp, device, 472 "%s setting up WDMA2 mode on Promise chip\n", 473 (error) ? "failed" : "success"); 474 if (!error) { 475 promise_timing(scp, devno, ATA_WDMA2); 476 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 477 return; 478 } 479 } 480 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 481 ata_pio2mode(apiomode), 482 ATA_C_F_SETXFER, ATA_WAIT_READY); 483 if (bootverbose) 484 ata_printf(scp, device, 485 "%s setting up PIO%d mode on Promise chip\n", 486 (error) ? "failed" : "success", 487 (apiomode >= 0) ? apiomode : 0); 488 promise_timing(scp, devno, ata_pio2mode(apiomode)); 489 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 490 return; 491 492 case 0x00041103: /* HighPoint HPT366 controller */ 493 /* no ATAPI devices for now */ 494 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 495 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 496 break; 497 498 if (udmamode >=4 && !(pci_read_config(parent, 0x5a, 1) & 0x2)) { 499 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 500 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 501 if (bootverbose) 502 ata_printf(scp, device, 503 "%s setting up UDMA4 mode on HPT366 chip\n", 504 (error) ? "failed" : "success"); 505 if (!error) { 506 hpt366_timing(scp, devno, ATA_UDMA4); 507 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 508 return; 509 } 510 } 511 if (udmamode >= 2) { 512 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 513 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 514 if (bootverbose) 515 ata_printf(scp, device, 516 "%s setting up UDMA2 mode on HPT366 chip\n", 517 (error) ? "failed" : "success"); 518 if (!error) { 519 hpt366_timing(scp, devno, ATA_UDMA2); 520 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 521 return; 522 } 523 } 524 if (wdmamode >= 2 && apiomode >= 4) { 525 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 526 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 527 if (bootverbose) 528 ata_printf(scp, device, 529 "%s setting up WDMA2 mode on HPT366 chip\n", 530 (error) ? "failed" : "success"); 531 if (!error) { 532 hpt366_timing(scp, devno, ATA_WDMA2); 533 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 534 return; 535 } 536 } 537 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 538 ata_pio2mode(apiomode), 539 ATA_C_F_SETXFER, ATA_WAIT_READY); 540 if (bootverbose) 541 ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n", 542 (error) ? "failed" : "success", 543 (apiomode >= 0) ? apiomode : 0); 544 hpt366_timing(scp, devno, ata_pio2mode(apiomode)); 545 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 546 return; 547 548 default: /* unknown controller chip */ 549 /* better not try generic DMA on ATAPI devices it almost never works */ 550 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 551 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 552 break; 553 554 /* if controller says its setup for DMA take the easy way out */ 555 /* the downside is we dont know what DMA mode we are in */ 556 if ((udmamode >= 0 || wdmamode > 1) && 557 (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 558 ((device==ATA_MASTER) ? 559 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 560 scp->mode[ATA_DEV(device)] = ATA_DMA; 561 return; 562 } 563 564 /* well, we have no support for this, but try anyways */ 565 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) { 566 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 567 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 568 if (bootverbose) 569 ata_printf(scp, device, 570 "%s setting up WDMA2 mode on generic chip\n", 571 (error) ? "failed" : "success"); 572 if (!error) { 573 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 574 return; 575 } 576 } 577 } 578 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 579 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 580 if (bootverbose) 581 ata_printf(scp, device, "%s setting up PIO%d mode on generic chip\n", 582 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 583 if (!error) 584 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 585 else 586 if (bootverbose) 587 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 588 } 589 590 int32_t 591 ata_dmasetup(struct ata_softc *scp, int32_t device, 592 int8_t *data, int32_t count, int32_t flags) 593 { 594 struct ata_dmaentry *dmatab; 595 u_int32_t dma_count, dma_base; 596 int32_t i = 0; 597 598 if (((uintptr_t)data & 1) || (count & 1)) 599 return -1; 600 601 if (!count) { 602 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 603 return -1; 604 } 605 606 dmatab = scp->dmatab[ATA_DEV(device)]; 607 dma_base = vtophys(data); 608 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 609 data += dma_count; 610 count -= dma_count; 611 612 while (count) { 613 dmatab[i].base = dma_base; 614 dmatab[i].count = (dma_count & 0xffff); 615 i++; 616 if (i >= ATA_DMA_ENTRIES) { 617 ata_printf(scp, device, "too many segments in DMA table\n"); 618 return -1; 619 } 620 dma_base = vtophys(data); 621 dma_count = min(count, PAGE_SIZE); 622 data += min(count, PAGE_SIZE); 623 count -= min(count, PAGE_SIZE); 624 } 625 dmatab[i].base = dma_base; 626 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 627 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 628 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0); 629 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 630 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 631 return 0; 632 } 633 634 void 635 ata_dmastart(struct ata_softc *scp) 636 { 637 scp->flags |= ATA_DMA_ACTIVE; 638 outb(scp->bmaddr + ATA_BMCMD_PORT, 639 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 640 } 641 642 int32_t 643 ata_dmadone(struct ata_softc *scp) 644 { 645 outb(scp->bmaddr + ATA_BMCMD_PORT, 646 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 647 scp->flags &= ~ATA_DMA_ACTIVE; 648 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 649 } 650 651 int32_t 652 ata_dmastatus(struct ata_softc *scp) 653 { 654 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 655 } 656 657 static void 658 promise_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 659 { 660 u_int32_t timing = 0; 661 struct promise_timing { 662 u_int8_t pa:4; 663 u_int8_t prefetch:1; 664 u_int8_t iordy:1; 665 u_int8_t errdy:1; 666 u_int8_t syncin:1; 667 u_int8_t pb:5; 668 u_int8_t mb:3; 669 u_int8_t mc:4; 670 u_int8_t dmaw:1; 671 u_int8_t dmar:1; 672 u_int8_t iordyp:1; 673 u_int8_t dmarqp:1; 674 u_int8_t reserved:8; 675 } *t = (struct promise_timing*)&timing; 676 677 t->iordy = 1; t->iordyp = 1; 678 if (mode >= ATA_DMA) { 679 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 680 } 681 682 switch (scp->chiptype) { 683 case 0x4d33105a: /* Promise 33's */ 684 switch (mode) { 685 default: 686 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 687 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 688 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 689 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 690 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 691 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 692 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 693 } 694 break; 695 696 case 0x4d38105a: /* Promise 66's */ 697 switch (mode) { 698 default: 699 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 700 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 701 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 702 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 703 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 704 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 705 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 706 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 707 } 708 break; 709 } 710 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 711 } 712 713 static void 714 hpt366_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 715 { 716 device_t parent = device_get_parent(scp->dev); 717 u_int32_t timing; 718 719 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 720 case 0x85: /* 25Mhz */ 721 switch (mode) { 722 case ATA_PIO0: timing = 0xc0d08585; break; 723 case ATA_PIO1: timing = 0xc0d08572; break; 724 case ATA_PIO2: timing = 0xc0ca8542; break; 725 case ATA_PIO3: timing = 0xc0ca8532; break; 726 case ATA_PIO4: timing = 0xc0ca8521; break; 727 case ATA_WDMA2: timing = 0xa0ca8521; break; 728 case ATA_UDMA2: timing = 0x90cf8521; break; 729 case ATA_UDMA4: timing = 0x90c98521; break; 730 default: timing = 0x01208585; 731 } 732 break; 733 default: 734 case 0xa7: /* 33MHz */ 735 switch (mode) { 736 case ATA_PIO0: timing = 0xc0d0a7aa; break; 737 case ATA_PIO1: timing = 0xc0d0a7a3; break; 738 case ATA_PIO2: timing = 0xc0d0a753; break; 739 case ATA_PIO3: timing = 0xc0c8a742; break; 740 case ATA_PIO4: timing = 0xc0c8a731; break; 741 case ATA_WDMA2: timing = 0xa0c8a731; break; 742 case ATA_UDMA2: timing = 0x90caa731; break; 743 case ATA_UDMA4: timing = 0x90c9a731; break; 744 default: timing = 0x0120a7a7; 745 } 746 break; 747 case 0xd9: /* 40Mhz */ 748 switch (mode) { 749 case ATA_PIO0: timing = 0xc018d9d9; break; 750 case ATA_PIO1: timing = 0xc010d9c7; break; 751 case ATA_PIO2: timing = 0xc010d997; break; 752 case ATA_PIO3: timing = 0xc010d974; break; 753 case ATA_PIO4: timing = 0xc008d963; break; 754 case ATA_WDMA2: timing = 0xa008d943; break; 755 case ATA_UDMA2: timing = 0x900bd943; break; 756 case ATA_UDMA4: timing = 0x900fd943; break; 757 default: timing = 0x0120d9d9; 758 } 759 } 760 pci_write_config(parent, 0x40 + (devno << 2) , (timing & ~0x80000000), 4); 761 } 762 763 #else /* NPCI > 0 */ 764 765 void 766 ata_dmainit(struct ata_softc *scp, int32_t device, 767 int32_t piomode, int32_t wdmamode, int32_t udmamode) 768 { 769 } 770 771 int32_t 772 ata_dmasetup(struct ata_softc *scp, int32_t device, 773 int8_t *data, int32_t count, int32_t flags) 774 { 775 return -1; 776 } 777 778 void 779 ata_dmastart(struct ata_softc *scp) 780 { 781 } 782 783 int32_t 784 ata_dmadone(struct ata_softc *scp) 785 { 786 return -1; 787 } 788 789 int32_t 790 ata_dmastatus(struct ata_softc *scp) 791 { 792 return -1; 793 } 794 795 #endif /* NPCI > 0 */ 796