1 /*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include "pci.h" 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bio.h> 35 #include <sys/malloc.h> 36 #include <sys/bus.h> 37 #include <sys/disk.h> 38 #include <sys/devicestat.h> 39 #include <vm/vm.h> 40 #include <vm/pmap.h> 41 #if NPCI > 0 42 #include <pci/pcivar.h> 43 #endif 44 #include <machine/bus.h> 45 #include <dev/ata/ata-all.h> 46 47 #if NPCI > 0 48 49 /* prototypes */ 50 static void cyrix_timing(struct ata_softc *, int, int); 51 static void promise_timing(struct ata_softc *, int, int); 52 static void hpt_timing(struct ata_softc *, int, int); 53 54 /* misc defines */ 55 #ifdef __alpha__ 56 #undef vtophys 57 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 58 #endif 59 60 void * 61 ata_dmaalloc(struct ata_softc *scp, int device) 62 { 63 void *dmatab; 64 65 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) { 66 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 67 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 68 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 69 free(dmatab, M_DEVBUF); 70 dmatab = NULL; 71 } 72 } 73 return dmatab; 74 } 75 76 void 77 ata_dmainit(struct ata_softc *scp, int device, 78 int apiomode, int wdmamode, int udmamode) 79 { 80 device_t parent = device_get_parent(scp->dev); 81 int devno = (scp->channel << 1) + ATA_DEV(device); 82 int error; 83 84 /* set our most pessimistic default mode */ 85 scp->mode[ATA_DEV(device)] = ATA_PIO; 86 87 if (!scp->bmaddr) 88 return; 89 90 /* if simplex controller, only allow DMA on primary channel */ 91 if (scp->channel == 1) { 92 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 93 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 94 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 95 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 96 return; 97 } 98 } 99 100 /* DMA engine address alignment is usually 1 word (2 bytes) */ 101 scp->alignment = 0x1; 102 103 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) { 104 ata_printf(scp, device, 105 "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 106 udmamode = 2; 107 } 108 109 switch (scp->chiptype) { 110 111 case 0x244b8086: /* Intel ICH2 */ 112 if (udmamode >= 5) { 113 int32_t mask48, new48; 114 int16_t word54; 115 116 word54 = pci_read_config(parent, 0x54, 2); 117 if (word54 & (0x10 << devno)) { 118 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 119 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 120 if (bootverbose) 121 ata_printf(scp, device, 122 "%s setting UDMA5 on ICH2 chip\n", 123 (error) ? "failed" : "success"); 124 if (!error) { 125 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 126 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 127 pci_write_config(parent, 0x48, 128 (pci_read_config(parent, 0x48, 4) & 129 ~mask48) | new48, 4); 130 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 131 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 132 return; 133 } 134 } 135 } 136 /* make sure eventual ATA100 mode from the BIOS is disabled */ 137 pci_write_config(parent, 0x54, 138 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 139 /* FALLTHROUGH */ 140 141 case 0x24118086: /* Intel ICH */ 142 if (udmamode >= 4) { 143 int32_t mask48, new48; 144 int16_t word54; 145 146 word54 = pci_read_config(parent, 0x54, 2); 147 if (word54 & (0x10 << devno)) { 148 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 149 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 150 if (bootverbose) 151 ata_printf(scp, device, 152 "%s setting UDMA4 on ICH%s chip\n", 153 (error) ? "failed" : "success", 154 (scp->chiptype == 0x244b8086) ? "2" : ""); 155 if (!error) { 156 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 157 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 158 pci_write_config(parent, 0x48, 159 (pci_read_config(parent, 0x48, 4) & 160 ~mask48) | new48, 4); 161 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 162 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 163 return; 164 } 165 } 166 } 167 /* make sure eventual ATA66 mode from the BIOS is disabled */ 168 pci_write_config(parent, 0x54, 169 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 170 /* FALLTHROUGH */ 171 172 case 0x71118086: /* Intel PIIX4 */ 173 case 0x71998086: /* Intel PIIX4e */ 174 case 0x24218086: /* Intel ICH0 */ 175 if (udmamode >= 2) { 176 int32_t mask48, new48; 177 178 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 179 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 180 if (bootverbose) 181 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 182 (error) ? "failed" : "success", 183 (scp->chiptype == 0x244b8086) ? "ICH2" : 184 (scp->chiptype == 0x24118086) ? "ICH" : 185 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 186 if (!error) { 187 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 188 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 189 pci_write_config(parent, 0x48, 190 (pci_read_config(parent, 0x48, 4) & 191 ~mask48) | new48, 4); 192 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 193 return; 194 } 195 } 196 /* make sure eventual ATA33 mode from the BIOS is disabled */ 197 pci_write_config(parent, 0x48, 198 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 199 /* FALLTHROUGH */ 200 201 case 0x70108086: /* Intel PIIX3 */ 202 if (wdmamode >= 2 && apiomode >= 4) { 203 int32_t mask40, new40, mask44, new44; 204 205 /* if SITRE not set doit for both channels */ 206 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 207 new40 = pci_read_config(parent, 0x40, 4); 208 new44 = pci_read_config(parent, 0x44, 4); 209 if (!(new40 & 0x00004000)) { 210 new44 &= ~0x0000000f; 211 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 212 } 213 if (!(new40 & 0x40000000)) { 214 new44 &= ~0x000000f0; 215 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 216 } 217 new40 |= 0x40004000; 218 pci_write_config(parent, 0x40, new40, 4); 219 pci_write_config(parent, 0x44, new44, 4); 220 } 221 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 222 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 223 if (bootverbose) 224 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 225 (error) ? "failed" : "success", 226 (scp->chiptype == 0x244b8086) ? "ICH2" : 227 (scp->chiptype == 0x24118086) ? "ICH" : 228 (scp->chiptype == 0x24218086) ? "ICH0" : 229 (scp->chiptype == 0x70108086) ? "PIIX3":"PIIX4"); 230 if (!error) { 231 if (device == ATA_MASTER) { 232 mask40 = 0x0000330f; 233 new40 = 0x00002307; 234 mask44 = 0; 235 new44 = 0; 236 } 237 else { 238 mask40 = 0x000000f0; 239 new40 = 0x00000070; 240 mask44 = 0x0000000f; 241 new44 = 0x0000000b; 242 } 243 if (scp->channel) { 244 mask40 <<= 16; 245 new40 <<= 16; 246 mask44 <<= 4; 247 new44 <<= 4; 248 } 249 pci_write_config(parent, 0x40, 250 (pci_read_config(parent, 0x40, 4) & ~mask40)| 251 new40, 4); 252 pci_write_config(parent, 0x44, 253 (pci_read_config(parent, 0x44, 4) & ~mask44)| 254 new44, 4); 255 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 256 return; 257 } 258 } 259 /* we could set PIO mode timings, but we assume the BIOS did that */ 260 break; 261 262 case 0x12308086: /* Intel PIIX */ 263 if (wdmamode >= 2 && apiomode >= 4) { 264 int32_t word40; 265 266 word40 = pci_read_config(parent, 0x40, 4); 267 word40 >>= scp->channel * 16; 268 269 /* Check for timing config usable for DMA on controller */ 270 if (!((word40 & 0x3300) == 0x2300 && 271 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 272 break; 273 274 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 275 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 276 if (bootverbose) 277 ata_printf(scp, device, 278 "%s setting WDMA2 on PIIX chip\n", 279 (error) ? "failed" : "success"); 280 if (!error) { 281 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 282 return; 283 } 284 } 285 break; 286 287 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 288 /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 289 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 290 ata_printf(scp, device, 291 "Aladdin: two atapi devices on this channel, no DMA\n"); 292 break; 293 } 294 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 295 int32_t word54 = pci_read_config(parent, 0x54, 4); 296 297 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 298 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 299 if (bootverbose) 300 ata_printf(scp, device, 301 "%s setting UDMA2 on Aladdin chip\n", 302 (error) ? "failed" : "success"); 303 if (!error) { 304 word54 &= ~(0x000f000f << (devno << 2)); 305 word54 |= (0x000a0005 << (devno << 2)); 306 pci_write_config(parent, 0x54, word54, 4); 307 pci_write_config(parent, 0x53, 308 pci_read_config(parent, 0x53, 1) | 0x03, 1); 309 scp->flags |= ATA_ATAPI_DMA_RO; 310 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 311 return; 312 } 313 } 314 315 /* make sure eventual UDMA mode from the BIOS is disabled */ 316 pci_write_config(parent, 0x54, 317 pci_read_config(parent, 0x54, 4) & ~0x88880000, 4); 318 319 if (wdmamode >= 2 && apiomode >= 4) { 320 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 321 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 322 if (bootverbose) 323 ata_printf(scp, device, 324 "%s setting WDMA2 on Aladdin chip\n", 325 (error) ? "failed" : "success"); 326 if (!error) { 327 pci_write_config(parent, 0x53, 328 pci_read_config(parent, 0x53, 1) | 0x03, 1); 329 scp->flags |= ATA_ATAPI_DMA_RO; 330 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 331 return; 332 } 333 } 334 pci_write_config(parent, 0x53, 335 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 336 /* we could set PIO mode timings, but we assume the BIOS did that */ 337 break; 338 339 case 0x74091022: /* AMD 756 */ 340 if (udmamode >= 4) { 341 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 342 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 343 if (bootverbose) 344 ata_printf(scp, device, 345 "%s setting UDMA4 on AMD chip\n", 346 (error) ? "failed" : "success"); 347 if (!error) { 348 pci_write_config(parent, 0x53 - devno, 0xc3, 1); 349 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 350 return; 351 } 352 } 353 goto via_82c586; 354 355 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 356 if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 357 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 358 359 if (udmamode >= 4) { 360 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 361 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 362 if (bootverbose) 363 ata_printf(scp, device, 364 "%s setting UDMA4 on VIA chip\n", 365 (error) ? "failed" : "success"); 366 if (!error) { 367 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 368 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 369 return; 370 } 371 } 372 if (udmamode >= 2) { 373 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 374 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 375 if (bootverbose) 376 ata_printf(scp, device, 377 "%s setting UDMA2 on VIA chip\n", 378 (error) ? "failed" : "success"); 379 if (!error) { 380 pci_write_config(parent, 0x53 - devno, 0xea, 1); 381 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 382 return; 383 } 384 } 385 } 386 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 387 ata_find_dev(parent, 0x05861106, 0x02)) { /* 82C586b */ 388 via_82c586: 389 if (udmamode >= 2) { 390 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 391 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 392 if (bootverbose) 393 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 394 (error) ? "failed" : "success", 395 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 396 if (!error) { 397 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 398 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 399 return; 400 } 401 } 402 } 403 if (wdmamode >= 2 && apiomode >= 4) { 404 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 405 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 406 if (bootverbose) 407 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 408 (error) ? "failed" : "success", 409 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 410 if (!error) { 411 pci_write_config(parent, 0x53 - devno, 0x82, 1); 412 pci_write_config(parent, 0x4b - devno, 0x31, 1); 413 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 414 return; 415 } 416 } 417 /* we could set PIO mode timings, but we assume the BIOS did that */ 418 break; 419 420 case 0x55131039: /* SiS 5591 */ 421 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 422 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 423 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 424 if (bootverbose) 425 ata_printf(scp, device, 426 "%s setting UDMA2 on SiS chip\n", 427 (error) ? "failed" : "success"); 428 if (!error) { 429 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 430 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 431 return; 432 } 433 } 434 if (wdmamode >=2 && apiomode >= 4) { 435 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 436 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 437 if (bootverbose) 438 ata_printf(scp, device, 439 "%s setting WDMA2 on SiS chip\n", 440 (error) ? "failed" : "success"); 441 if (!error) { 442 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 443 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 444 return; 445 } 446 } 447 /* we could set PIO mode timings, but we assume the BIOS did that */ 448 break; 449 450 case 0x06491095: /* CMD 649 ATA100 controller */ 451 if (udmamode >= 5) { 452 u_int8_t umode; 453 454 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 455 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 456 if (bootverbose) 457 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 458 (error) ? "failed" : "success"); 459 if (!error) { 460 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 461 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 462 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 463 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 464 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 465 return; 466 } 467 } 468 /* FALLTHROUGH */ 469 470 case 0x06481095: /* CMD 648 ATA66 controller */ 471 if (udmamode >= 4) { 472 u_int8_t umode; 473 474 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 475 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 476 if (bootverbose) 477 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 478 (error) ? "failed" : "success"); 479 if (!error) { 480 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 481 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 482 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 483 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 484 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 485 return; 486 } 487 } 488 if (udmamode >= 2) { 489 u_int8_t umode; 490 491 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 492 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 493 if (bootverbose) 494 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 495 (error) ? "failed" : "success"); 496 if (!error) { 497 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 498 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 499 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 500 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 501 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 502 return; 503 } 504 } 505 /* make sure eventual UDMA mode from the BIOS is disabled */ 506 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 507 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 508 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 509 /* FALLTHROUGH */ 510 511 case 0x06461095: /* CMD 646 ATA controller */ 512 if (wdmamode >= 2 && apiomode >= 4) { 513 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 514 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 515 if (bootverbose) 516 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 517 error ? "failed" : "success"); 518 if (!error) { 519 int32_t offset = (devno < 3) ? (devno << 1) : 7; 520 521 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 522 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 523 return; 524 } 525 } 526 /* we could set PIO mode timings, but we assume the BIOS did that */ 527 break; 528 529 case 0xc6931080: /* Cypress 82c693 ATA controller */ 530 if (wdmamode >= 2 && apiomode >= 4) { 531 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 532 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 533 if (bootverbose) 534 ata_printf(scp, device, 535 "%s setting WDMA2 on Cypress chip\n", 536 error ? "failed" : "success"); 537 if (!error) { 538 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 539 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 540 return; 541 } 542 } 543 /* we could set PIO mode timings, but we assume the BIOS did that */ 544 break; 545 546 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 547 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 548 if (udmamode >= 2) { 549 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 550 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 551 if (bootverbose) 552 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 553 (error) ? "failed" : "success"); 554 if (!error) { 555 cyrix_timing(scp, devno, ATA_UDMA2); 556 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 557 return; 558 } 559 } 560 if (wdmamode >= 2 && apiomode >= 4) { 561 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 562 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 563 if (bootverbose) 564 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 565 (error) ? "failed" : "success"); 566 if (!error) { 567 cyrix_timing(scp, devno, ATA_WDMA2); 568 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 569 return; 570 } 571 } 572 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 573 ata_pio2mode(apiomode), ATA_C_F_SETXFER, 574 ATA_WAIT_READY); 575 if (bootverbose) 576 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 577 (error) ? "failed" : "success", 578 ata_mode2str(ata_pio2mode(apiomode))); 579 cyrix_timing(scp, devno, ata_pio2mode(apiomode)); 580 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 581 return; 582 583 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 584 if (udmamode >= 2) { 585 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 586 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 587 if (bootverbose) 588 ata_printf(scp, device, 589 "%s setting UDMA2 on ServerWorks chip\n", 590 (error) ? "failed" : "success"); 591 if (!error) { 592 u_int16_t reg56; 593 594 pci_write_config(parent, 0x54, 595 pci_read_config(parent, 0x54, 1) | 596 (0x01 << devno), 1); 597 reg56 = pci_read_config(parent, 0x56, 2); 598 reg56 &= ~(0xf << (devno * 4)); 599 reg56 |= (0x2 << (devno * 4)); 600 pci_write_config(parent, 0x56, reg56, 2); 601 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 602 return; 603 } 604 } 605 if (wdmamode >= 2 && apiomode >= 4) { 606 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 607 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 608 if (bootverbose) 609 ata_printf(scp, device, 610 "%s setting WDMA2 on ServerWorks chip\n", 611 (error) ? "failed" : "success"); 612 if (!error) { 613 int offset = (scp->channel * 2) + (device == ATA_MASTER); 614 int word44 = pci_read_config(parent, 0x44, 4); 615 616 pci_write_config(parent, 0x54, 617 pci_read_config(parent, 0x54, 1) & 618 ~(0x01 << devno), 1); 619 word44 &= ~(0xff << (offset << 8)); 620 word44 |= (0x20 << (offset << 8)); 621 pci_write_config(parent, 0x44, 0x20, 4); 622 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 623 return; 624 } 625 } 626 /* we could set PIO mode timings, but we assume the BIOS did that */ 627 break; 628 629 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 630 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 631 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 632 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 633 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 634 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 635 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 636 break; 637 638 if (udmamode >= 5 && 639 (scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 640 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 641 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 642 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 643 if (bootverbose) 644 ata_printf(scp, device, 645 "%s setting UDMA5 on Promise chip\n", 646 (error) ? "failed" : "success"); 647 if (!error) { 648 promise_timing(scp, devno, ATA_UDMA5); 649 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 650 return; 651 } 652 } 653 if (udmamode >= 4 && (scp->chiptype == 0x4d38105a || 654 scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 655 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 656 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 657 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 658 if (bootverbose) 659 ata_printf(scp, device, 660 "%s setting UDMA4 on Promise chip\n", 661 (error) ? "failed" : "success"); 662 if (!error) { 663 promise_timing(scp, devno, ATA_UDMA4); 664 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 665 return; 666 } 667 } 668 if (udmamode >= 2) { 669 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 670 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 671 if (bootverbose) 672 ata_printf(scp, device, 673 "%s setting UDMA2 on Promise chip\n", 674 (error) ? "failed" : "success"); 675 if (!error) { 676 promise_timing(scp, devno, ATA_UDMA2); 677 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 678 return; 679 } 680 } 681 if (wdmamode >= 2 && apiomode >= 4) { 682 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 683 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 684 if (bootverbose) 685 ata_printf(scp, device, 686 "%s setting WDMA2 on Promise chip\n", 687 (error) ? "failed" : "success"); 688 if (!error) { 689 promise_timing(scp, devno, ATA_WDMA2); 690 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 691 return; 692 } 693 } 694 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 695 ata_pio2mode(apiomode), 696 ATA_C_F_SETXFER, ATA_WAIT_READY); 697 if (bootverbose) 698 ata_printf(scp, device, 699 "%s setting PIO%d on Promise chip\n", 700 (error) ? "failed" : "success", 701 (apiomode >= 0) ? apiomode : 0); 702 promise_timing(scp, devno, ata_pio2mode(apiomode)); 703 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 704 return; 705 706 case 0x00041103: /* HighPoint HPT366/368/370 controllers */ 707 /* no ATAPI devices for now */ 708 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 709 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 710 break; 711 712 if (udmamode >=5 && pci_get_revid(parent) >= 0x03 && 713 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 714 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 715 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 716 if (bootverbose) 717 ata_printf(scp, device, 718 "%s setting UDMA5 on HighPoint chip\n", 719 (error) ? "failed" : "success"); 720 if (!error) { 721 hpt_timing(scp, devno, ATA_UDMA5); 722 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 723 return; 724 } 725 } 726 if (udmamode >=4 && 727 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 728 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 729 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 730 if (bootverbose) 731 ata_printf(scp, device, 732 "%s setting UDMA4 on HighPoint chip\n", 733 (error) ? "failed" : "success"); 734 if (!error) { 735 hpt_timing(scp, devno, ATA_UDMA4); 736 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 737 return; 738 } 739 } 740 if (udmamode >= 2) { 741 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 742 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 743 if (bootverbose) 744 ata_printf(scp, device, 745 "%s setting UDMA2 on HighPoint chip\n", 746 (error) ? "failed" : "success"); 747 if (!error) { 748 hpt_timing(scp, devno, ATA_UDMA2); 749 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 750 return; 751 } 752 } 753 if (wdmamode >= 2 && apiomode >= 4) { 754 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 755 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 756 if (bootverbose) 757 ata_printf(scp, device, 758 "%s setting WDMA2 on HighPoint chip\n", 759 (error) ? "failed" : "success"); 760 if (!error) { 761 hpt_timing(scp, devno, ATA_WDMA2); 762 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 763 return; 764 } 765 } 766 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 767 ata_pio2mode(apiomode), 768 ATA_C_F_SETXFER, ATA_WAIT_READY); 769 if (bootverbose) 770 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 771 (error) ? "failed" : "success", 772 (apiomode >= 0) ? apiomode : 0); 773 hpt_timing(scp, devno, ata_pio2mode(apiomode)); 774 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 775 return; 776 777 default: /* unknown controller chip */ 778 /* better not try generic DMA on ATAPI devices it almost never works */ 779 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 780 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 781 break; 782 783 /* if controller says its setup for DMA take the easy way out */ 784 /* the downside is we dont know what DMA mode we are in */ 785 if ((udmamode >= 0 || wdmamode > 1) && 786 (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 787 ((device==ATA_MASTER) ? 788 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 789 scp->mode[ATA_DEV(device)] = ATA_DMA; 790 return; 791 } 792 793 /* well, we have no support for this, but try anyways */ 794 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) { 795 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 796 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 797 if (bootverbose) 798 ata_printf(scp, device, 799 "%s setting WDMA2 on generic chip\n", 800 (error) ? "failed" : "success"); 801 if (!error) { 802 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 803 return; 804 } 805 } 806 } 807 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 808 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 809 if (bootverbose) 810 ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 811 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 812 if (!error) 813 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 814 else { 815 if (bootverbose) 816 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 817 scp->mode[ATA_DEV(device)] = ATA_PIO; 818 } 819 } 820 821 int 822 ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 823 caddr_t data, int32_t count) 824 { 825 u_int32_t dma_count, dma_base; 826 int i = 0; 827 828 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 829 ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 830 return -1; 831 } 832 833 if (!count) { 834 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 835 return -1; 836 } 837 838 dma_base = vtophys(data); 839 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 840 data += dma_count; 841 count -= dma_count; 842 843 while (count) { 844 dmatab[i].base = dma_base; 845 dmatab[i].count = (dma_count & 0xffff); 846 i++; 847 if (i >= ATA_DMA_ENTRIES) { 848 ata_printf(scp, device, "too many segments in DMA table\n"); 849 return -1; 850 } 851 dma_base = vtophys(data); 852 dma_count = min(count, PAGE_SIZE); 853 data += min(count, PAGE_SIZE); 854 count -= min(count, PAGE_SIZE); 855 } 856 dmatab[i].base = dma_base; 857 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 858 return 0; 859 } 860 861 void 862 ata_dmastart(struct ata_softc *scp, int device, 863 struct ata_dmaentry *dmatab, int dir) 864 { 865 scp->flags |= ATA_DMA_ACTIVE; 866 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 867 outb(scp->bmaddr + ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 868 outb(scp->bmaddr + ATA_BMSTAT_PORT, 869 (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 870 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 871 outb(scp->bmaddr + ATA_BMCMD_PORT, 872 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 873 } 874 875 int 876 ata_dmadone(struct ata_softc *scp) 877 { 878 outb(scp->bmaddr + ATA_BMCMD_PORT, 879 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 880 scp->flags &= ~ATA_DMA_ACTIVE; 881 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 882 } 883 884 int 885 ata_dmastatus(struct ata_softc *scp) 886 { 887 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 888 } 889 890 static void 891 cyrix_timing(struct ata_softc *scp, int devno, int mode) 892 { 893 u_int32_t reg20 = 0x0000e132; 894 u_int32_t reg24 = 0x00017771; 895 896 switch (mode) { 897 case ATA_PIO0: reg20 = 0x0000e132; break; 898 case ATA_PIO1: reg20 = 0x00018121; break; 899 case ATA_PIO2: reg20 = 0x00024020; break; 900 case ATA_PIO3: reg20 = 0x00032010; break; 901 case ATA_PIO4: reg20 = 0x00040010; break; 902 case ATA_WDMA2: reg24 = 0x00002020; break; 903 case ATA_UDMA2: reg24 = 0x00911030; break; 904 } 905 outl(scp->bmaddr + (devno << 3) + 0x20, reg20); 906 outl(scp->bmaddr + (devno << 3) + 0x24, reg24); 907 } 908 909 static void 910 promise_timing(struct ata_softc *scp, int devno, int mode) 911 { 912 u_int32_t timing = 0; 913 struct promise_timing { 914 u_int8_t pa:4; 915 u_int8_t prefetch:1; 916 u_int8_t iordy:1; 917 u_int8_t errdy:1; 918 u_int8_t syncin:1; 919 u_int8_t pb:5; 920 u_int8_t mb:3; 921 u_int8_t mc:4; 922 u_int8_t dmaw:1; 923 u_int8_t dmar:1; 924 u_int8_t iordyp:1; 925 u_int8_t dmarqp:1; 926 u_int8_t reserved:8; 927 } *t = (struct promise_timing*)&timing; 928 929 t->iordy = 1; t->iordyp = 1; 930 if (mode >= ATA_DMA) { 931 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 932 } 933 934 switch (scp->chiptype) { 935 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 936 switch (mode) { 937 default: 938 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 939 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 940 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 941 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 942 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 943 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 944 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 945 } 946 break; 947 948 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 949 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 950 case 0x0d30105a: /* Promise OEM ATA 100 */ 951 switch (mode) { 952 default: 953 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 954 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 955 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 956 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 957 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 958 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 959 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 960 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 961 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 962 } 963 break; 964 } 965 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 966 } 967 968 static void 969 hpt_timing(struct ata_softc *scp, int devno, int mode) 970 { 971 device_t parent = device_get_parent(scp->dev); 972 u_int32_t timing; 973 974 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 975 switch (mode) { 976 case ATA_PIO0: timing = 0x06914e57; break; 977 case ATA_PIO1: timing = 0x06914e43; break; 978 case ATA_PIO2: timing = 0x06514e33; break; 979 case ATA_PIO3: timing = 0x06514e22; break; 980 case ATA_PIO4: timing = 0x06514e21; break; 981 case ATA_WDMA2: timing = 0x26514e21; break; 982 case ATA_UDMA2: timing = 0x16494e31; break; 983 case ATA_UDMA4: timing = 0x16454e31; break; 984 case ATA_UDMA5: timing = 0x16454e31; break; 985 default: timing = 0x06514e57; 986 } 987 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 988 pci_write_config(parent, 0x5b, 0x22, 1); 989 } 990 else { /* HPT36[68] */ 991 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 992 case 0x85: /* 25Mhz */ 993 switch (mode) { 994 case ATA_PIO0: timing = 0xc0d08585; break; 995 case ATA_PIO1: timing = 0xc0d08572; break; 996 case ATA_PIO2: timing = 0xc0ca8542; break; 997 case ATA_PIO3: timing = 0xc0ca8532; break; 998 case ATA_PIO4: timing = 0xc0ca8521; break; 999 case ATA_WDMA2: timing = 0xa0ca8521; break; 1000 case ATA_UDMA2: timing = 0x90cf8521; break; 1001 case ATA_UDMA4: timing = 0x90c98521; break; 1002 default: timing = 0x01208585; 1003 } 1004 break; 1005 default: 1006 case 0xa7: /* 33MHz */ 1007 switch (mode) { 1008 case ATA_PIO0: timing = 0xc0d0a7aa; break; 1009 case ATA_PIO1: timing = 0xc0d0a7a3; break; 1010 case ATA_PIO2: timing = 0xc0d0a753; break; 1011 case ATA_PIO3: timing = 0xc0c8a742; break; 1012 case ATA_PIO4: timing = 0xc0c8a731; break; 1013 case ATA_WDMA2: timing = 0xa0c8a731; break; 1014 case ATA_UDMA2: timing = 0x90caa731; break; 1015 case ATA_UDMA4: timing = 0x90c9a731; break; 1016 default: timing = 0x0120a7a7; 1017 } 1018 break; 1019 case 0xd9: /* 40Mhz */ 1020 switch (mode) { 1021 case ATA_PIO0: timing = 0xc018d9d9; break; 1022 case ATA_PIO1: timing = 0xc010d9c7; break; 1023 case ATA_PIO2: timing = 0xc010d997; break; 1024 case ATA_PIO3: timing = 0xc010d974; break; 1025 case ATA_PIO4: timing = 0xc008d963; break; 1026 case ATA_WDMA2: timing = 0xa008d943; break; 1027 case ATA_UDMA2: timing = 0x900bd943; break; 1028 case ATA_UDMA4: timing = 0x900fd943; break; 1029 default: timing = 0x0120d9d9; 1030 } 1031 } 1032 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 1033 } 1034 } 1035 1036 #else /* NPCI > 0 */ 1037 1038 void * 1039 ata_dmaalloc(struct ata_softc *scp, int device) 1040 { 1041 return 0; 1042 } 1043 1044 void 1045 ata_dmainit(struct ata_softc *scp, int device, 1046 int piomode, int wdmamode, int udmamode) 1047 { 1048 } 1049 1050 int 1051 ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 1052 caddr_t data, int32_t count) 1053 { 1054 return -1; 1055 } 1056 1057 void 1058 ata_dmastart(struct ata_softc *scp, int device, 1059 struct ata_dmaentry *dmatab, int dir) 1060 { 1061 } 1062 1063 int 1064 ata_dmadone(struct ata_softc *scp) 1065 { 1066 return -1; 1067 } 1068 1069 int 1070 ata_dmastatus(struct ata_softc *scp) 1071 { 1072 return -1; 1073 } 1074 1075 #endif /* NPCI > 0 */ 1076