1 /*- 2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/ata.h> 34 #include <sys/bio.h> 35 #include <sys/malloc.h> 36 #include <sys/bus.h> 37 #include <sys/disk.h> 38 #include <sys/devicestat.h> 39 #include <vm/vm.h> 40 #include <vm/pmap.h> 41 #include <pci/pcivar.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/ata/ata-all.h> 45 46 /* prototypes */ 47 static void cyrix_timing(struct ata_channel *, int, int); 48 static void promise_timing(struct ata_channel *, int, int); 49 static void hpt_timing(struct ata_channel *, int, int); 50 static int hpt_cable80(struct ata_channel *); 51 52 /* misc defines */ 53 #ifdef __alpha__ 54 #undef vtophys 55 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 56 #endif 57 #define ATAPI_DEVICE(ch, device) \ 58 ((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || \ 59 (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE)) 60 61 void * 62 ata_dmaalloc(struct ata_channel *ch, int device) 63 { 64 void *dmatab; 65 66 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) { 67 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 68 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 69 ata_printf(ch, device, "dmatab crosses page boundary, no DMA\n"); 70 free(dmatab, M_DEVBUF); 71 dmatab = NULL; 72 } 73 } 74 return dmatab; 75 } 76 77 void 78 ata_dmainit(struct ata_channel *ch, int device, 79 int apiomode, int wdmamode, int udmamode) 80 { 81 struct ata_device *atadev = &ch->device[ATA_DEV(device)]; 82 device_t parent = device_get_parent(ch->dev); 83 int devno = (ch->unit << 1) + ATA_DEV(device); 84 int error; 85 86 /* set our most pessimistic default mode */ 87 atadev->mode = ATA_PIO; 88 89 if (!ch->r_bmio) 90 return; 91 92 /* if simplex controller, only allow DMA on primary channel */ 93 if (ch->unit == 1) { 94 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 95 ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & 96 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 97 if (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 98 ata_prtdev(atadev, "simplex device, DMA on primary only\n"); 99 return; 100 } 101 } 102 103 /* DMA engine address alignment is usually 1 word (2 bytes) */ 104 ch->alignment = 0x1; 105 106 #if 1 107 if (udmamode > 2 && !ch->device[ATA_DEV(device)].param->hwres_cblid) { 108 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n"); 109 udmamode = 2; 110 } 111 #endif 112 switch (ch->chiptype) { 113 114 case 0x248a8086: /* Intel ICH3 mobile */ 115 case 0x248b8086: /* Intel ICH3 */ 116 case 0x244a8086: /* Intel ICH2 mobile */ 117 case 0x244b8086: /* Intel ICH2 */ 118 if (udmamode >= 5) { 119 int32_t mask48, new48; 120 int16_t word54; 121 122 word54 = pci_read_config(parent, 0x54, 2); 123 if (word54 & (0x10 << devno)) { 124 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 125 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 126 if (bootverbose) 127 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n", 128 (error) ? "failed" : "success"); 129 if (!error) { 130 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 131 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 132 pci_write_config(parent, 0x48, 133 (pci_read_config(parent, 0x48, 4) & 134 ~mask48) | new48, 4); 135 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 136 atadev->mode = ATA_UDMA5; 137 return; 138 } 139 } 140 } 141 /* make sure eventual ATA100 mode from the BIOS is disabled */ 142 pci_write_config(parent, 0x54, 143 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 144 /* FALLTHROUGH */ 145 146 case 0x24118086: /* Intel ICH */ 147 case 0x76018086: /* Intel ICH */ 148 if (udmamode >= 4) { 149 int32_t mask48, new48; 150 int16_t word54; 151 152 word54 = pci_read_config(parent, 0x54, 2); 153 if (word54 & (0x10 << devno)) { 154 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 155 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 156 if (bootverbose) 157 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n", 158 (error) ? "failed" : "success"); 159 if (!error) { 160 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 161 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 162 pci_write_config(parent, 0x48, 163 (pci_read_config(parent, 0x48, 4) & 164 ~mask48) | new48, 4); 165 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 166 atadev->mode = ATA_UDMA4; 167 return; 168 } 169 } 170 } 171 /* make sure eventual ATA66 mode from the BIOS is disabled */ 172 pci_write_config(parent, 0x54, 173 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 174 /* FALLTHROUGH */ 175 176 case 0x71118086: /* Intel PIIX4 */ 177 case 0x84CA8086: /* Intel PIIX4 */ 178 case 0x71998086: /* Intel PIIX4e */ 179 case 0x24218086: /* Intel ICH0 */ 180 if (udmamode >= 2) { 181 int32_t mask48, new48; 182 183 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 184 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 185 if (bootverbose) 186 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n", 187 (error) ? "failed" : "success"); 188 if (!error) { 189 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 190 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 191 pci_write_config(parent, 0x48, 192 (pci_read_config(parent, 0x48, 4) & 193 ~mask48) | new48, 4); 194 atadev->mode = ATA_UDMA2; 195 return; 196 } 197 } 198 /* make sure eventual ATA33 mode from the BIOS is disabled */ 199 pci_write_config(parent, 0x48, 200 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 201 /* FALLTHROUGH */ 202 203 case 0x70108086: /* Intel PIIX3 */ 204 if (wdmamode >= 2 && apiomode >= 4) { 205 int32_t mask40, new40, mask44, new44; 206 207 /* if SITRE not set doit for both channels */ 208 if (!((pci_read_config(parent,0x40,4)>>(ch->unit<<8))&0x4000)) { 209 new40 = pci_read_config(parent, 0x40, 4); 210 new44 = pci_read_config(parent, 0x44, 4); 211 if (!(new40 & 0x00004000)) { 212 new44 &= ~0x0000000f; 213 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 214 } 215 if (!(new40 & 0x40000000)) { 216 new44 &= ~0x000000f0; 217 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 218 } 219 new40 |= 0x40004000; 220 pci_write_config(parent, 0x40, new40, 4); 221 pci_write_config(parent, 0x44, new44, 4); 222 } 223 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 224 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 225 if (bootverbose) 226 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n", 227 (error) ? "failed" : "success"); 228 if (!error) { 229 if (device == ATA_MASTER) { 230 mask40 = 0x0000330f; 231 new40 = 0x00002307; 232 mask44 = 0; 233 new44 = 0; 234 } 235 else { 236 mask40 = 0x000000f0; 237 new40 = 0x00000070; 238 mask44 = 0x0000000f; 239 new44 = 0x0000000b; 240 } 241 if (ch->unit) { 242 mask40 <<= 16; 243 new40 <<= 16; 244 mask44 <<= 4; 245 new44 <<= 4; 246 } 247 pci_write_config(parent, 0x40, 248 (pci_read_config(parent, 0x40, 4) & ~mask40)| 249 new40, 4); 250 pci_write_config(parent, 0x44, 251 (pci_read_config(parent, 0x44, 4) & ~mask44)| 252 new44, 4); 253 atadev->mode = ATA_WDMA2; 254 return; 255 } 256 } 257 /* we could set PIO mode timings, but we assume the BIOS did that */ 258 break; 259 260 case 0x12308086: /* Intel PIIX */ 261 if (wdmamode >= 2 && apiomode >= 4) { 262 int32_t word40; 263 264 word40 = pci_read_config(parent, 0x40, 4); 265 word40 >>= ch->unit * 16; 266 267 /* Check for timing config usable for DMA on controller */ 268 if (!((word40 & 0x3300) == 0x2300 && 269 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 270 break; 271 272 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 273 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 274 if (bootverbose) 275 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n", 276 (error) ? "failed" : "success"); 277 if (!error) { 278 atadev->mode = ATA_WDMA2; 279 return; 280 } 281 } 282 break; 283 284 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 285 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 286 if (pci_get_revid(parent) < 0xc2 && 287 ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) { 288 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n"); 289 break; 290 } 291 if (udmamode >= 5 && pci_get_revid(parent) >= 0xc4) { 292 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 293 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 294 if (bootverbose) 295 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n", 296 (error) ? "failed" : "success"); 297 if (!error) { 298 int32_t word54 = pci_read_config(parent, 0x54, 4); 299 300 pci_write_config(parent, 0x4b, 301 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 302 word54 &= ~(0x000f000f << (devno << 2)); 303 word54 |= (0x000f0005 << (devno << 2)); 304 pci_write_config(parent, 0x54, word54, 4); 305 pci_write_config(parent, 0x53, 306 pci_read_config(parent, 0x53, 1) | 0x03, 1); 307 atadev->mode = ATA_UDMA5; 308 return; 309 } 310 } 311 if (udmamode >= 4 && pci_get_revid(parent) >= 0xc2) { 312 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 313 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 314 if (bootverbose) 315 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n", 316 (error) ? "failed" : "success"); 317 if (!error) { 318 int32_t word54 = pci_read_config(parent, 0x54, 4); 319 320 pci_write_config(parent, 0x4b, 321 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 322 word54 &= ~(0x000f000f << (devno << 2)); 323 word54 |= (0x00080005 << (devno << 2)); 324 pci_write_config(parent, 0x54, word54, 4); 325 pci_write_config(parent, 0x53, 326 pci_read_config(parent, 0x53, 1) | 0x03, 1); 327 atadev->mode = ATA_UDMA4; 328 return; 329 } 330 } 331 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 332 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 333 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 334 if (bootverbose) 335 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n", 336 (error) ? "failed" : "success"); 337 if (!error) { 338 int32_t word54 = pci_read_config(parent, 0x54, 4); 339 340 word54 &= ~(0x000f000f << (devno << 2)); 341 word54 |= (0x000a0005 << (devno << 2)); 342 pci_write_config(parent, 0x54, word54, 4); 343 pci_write_config(parent, 0x53, 344 pci_read_config(parent, 0x53, 1) | 0x03, 1); 345 ch->flags |= ATA_ATAPI_DMA_RO; 346 atadev->mode = ATA_UDMA2; 347 return; 348 } 349 } 350 351 /* make sure eventual UDMA mode from the BIOS is disabled */ 352 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 353 ~(0x0008 << (devno << 2)), 2); 354 355 if (wdmamode >= 2 && apiomode >= 4) { 356 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 357 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 358 if (bootverbose) 359 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n", 360 (error) ? "failed" : "success"); 361 if (!error) { 362 pci_write_config(parent, 0x53, 363 pci_read_config(parent, 0x53, 1) | 0x03, 1); 364 ch->flags |= ATA_ATAPI_DMA_RO; 365 atadev->mode = ATA_WDMA2; 366 return; 367 } 368 } 369 pci_write_config(parent, 0x53, 370 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 371 /* we could set PIO mode timings, but we assume the BIOS did that */ 372 break; 373 374 case 0x74111022: /* AMD 766 */ 375 if (udmamode >= 5) { 376 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 377 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 378 if (bootverbose) 379 ata_prtdev(atadev, "%s setting UDMA5 on AMD chip\n", 380 (error) ? "failed" : "success"); 381 if (!error) { 382 pci_write_config(parent, 0x53 - devno, 0xc6, 1); 383 atadev->mode = ATA_UDMA5; 384 return; 385 } 386 } 387 /* FALLTHROUGH */ 388 389 case 0x74091022: /* AMD 756 */ 390 if (udmamode >= 4) { 391 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 392 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 393 if (bootverbose) 394 ata_prtdev(atadev, "%s setting UDMA4 on AMD chip\n", 395 (error) ? "failed" : "success"); 396 if (!error) { 397 pci_write_config(parent, 0x53 - devno, 0xc5, 1); 398 atadev->mode = ATA_UDMA4; 399 return; 400 } 401 } 402 goto via_82c586; 403 404 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 , 8231, 8233 */ 405 { 406 int via_modes[4][7] = { 407 { 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* ATA33 */ 408 { 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 }, /* ATA66 */ 409 { 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 }, /* ATA100 */ 410 { 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 }}; /* ATA133 */ 411 int *reg_val = NULL; 412 413 if (ata_find_dev(parent, 0x31471106, 0x40)) { /* 8233a */ 414 udmamode = imin(udmamode, 6); 415 reg_val = via_modes[3]; 416 } 417 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */ 418 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */ 419 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */ 420 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */ 421 udmamode = imin(udmamode, 5); 422 reg_val = via_modes[2]; 423 } 424 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */ 425 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 426 udmamode = imin(udmamode, 4); 427 reg_val = via_modes[1]; 428 } 429 else if (ata_find_dev(parent, 0x06861106, 0x0)) { /* 82C686 */ 430 udmamode = imin(udmamode, 2); 431 reg_val = via_modes[1]; 432 } 433 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 434 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 435 via_82c586: 436 udmamode = imin(udmamode, 2); 437 reg_val = via_modes[0]; 438 } 439 else 440 udmamode = 0; 441 442 if (udmamode >= 6) { 443 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 444 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 445 if (bootverbose) 446 ata_prtdev(atadev, "%s setting UDMA6 on VIA chip\n", 447 (error) ? "failed" : "success"); 448 if (!error) { 449 pci_write_config(parent, 0x53 - devno, reg_val[6], 1); 450 atadev->mode = ATA_UDMA6; 451 return; 452 } 453 } 454 if (udmamode >= 5) { 455 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 456 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 457 if (bootverbose) 458 ata_prtdev(atadev, "%s setting UDMA5 on VIA chip\n", 459 (error) ? "failed" : "success"); 460 if (!error) { 461 pci_write_config(parent, 0x53 - devno, reg_val[5], 1); 462 atadev->mode = ATA_UDMA5; 463 return; 464 } 465 } 466 if (udmamode >= 4) { 467 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 468 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 469 if (bootverbose) 470 ata_prtdev(atadev, "%s setting UDMA4 on VIA chip\n", 471 (error) ? "failed" : "success"); 472 if (!error) { 473 pci_write_config(parent, 0x53 - devno, reg_val[4], 1); 474 atadev->mode = ATA_UDMA4; 475 return; 476 } 477 } 478 if (udmamode >= 2) { 479 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 480 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 481 if (bootverbose) 482 ata_prtdev(atadev, "%s setting UDMA2 on VIA chip\n", 483 (error) ? "failed" : "success"); 484 if (!error) { 485 pci_write_config(parent, 0x53 - devno, reg_val[2], 1); 486 atadev->mode = ATA_UDMA2; 487 return; 488 } 489 } 490 491 } 492 if (wdmamode >= 2 && apiomode >= 4) { 493 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 494 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 495 if (bootverbose) 496 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n", 497 (error) ? "failed" : "success", 498 (ch->chiptype == 0x74091022) ? "AMD" : "VIA"); 499 if (!error) { 500 pci_write_config(parent, 0x53 - devno, 0x0b, 1); 501 pci_write_config(parent, 0x4b - devno, 0x31, 1); 502 atadev->mode = ATA_WDMA2; 503 return; 504 } 505 } 506 /* we could set PIO mode timings, but we assume the BIOS did that */ 507 break; 508 509 case 0x55131039: /* SiS 5591 */ 510 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */ 511 ata_find_dev(parent, 0x06331039, 0x00) || /* SiS 633 */ 512 ata_find_dev(parent, 0x06351039, 0x00) || /* SiS 635 */ 513 ata_find_dev(parent, 0x06401039, 0x00) || /* SiS 640 */ 514 ata_find_dev(parent, 0x06451039, 0x00) || /* SiS 645 */ 515 ata_find_dev(parent, 0x06501039, 0x00) || /* SiS 650 */ 516 ata_find_dev(parent, 0x07301039, 0x00) || /* SiS 730 */ 517 ata_find_dev(parent, 0x07331039, 0x00) || /* SiS 733 */ 518 ata_find_dev(parent, 0x07351039, 0x00) || /* SiS 735 */ 519 ata_find_dev(parent, 0x07401039, 0x00) || /* SiS 740 */ 520 ata_find_dev(parent, 0x07451039, 0x00) || /* SiS 745 */ 521 ata_find_dev(parent, 0x07501039, 0x00)) { /* SiS 750 */ 522 int8_t reg = 0x40 + (devno << 1); 523 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 524 525 if (udmamode >= 5) { 526 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 527 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 528 if (bootverbose) 529 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n", 530 (error) ? "failed" : "success"); 531 if (!error) { 532 pci_write_config(parent, reg, val | 0x8000, 2); 533 atadev->mode = ATA_UDMA5; 534 return; 535 } 536 } 537 if (udmamode >= 4) { 538 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 539 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 540 if (bootverbose) 541 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n", 542 (error) ? "failed" : "success"); 543 if (!error) { 544 pci_write_config(parent, reg, val | 0x9000, 2); 545 atadev->mode = ATA_UDMA4; 546 return; 547 } 548 } 549 if (udmamode >= 2) { 550 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 551 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 552 if (bootverbose) 553 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 554 (error) ? "failed" : "success"); 555 if (!error) { 556 pci_write_config(parent, reg, val | 0xb000, 2); 557 atadev->mode = ATA_UDMA2; 558 return; 559 } 560 } 561 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */ 562 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */ 563 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */ 564 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */ 565 int8_t reg = 0x40 + (devno << 1); 566 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 567 568 if (udmamode >= 4) { 569 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 570 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 571 if (bootverbose) 572 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n", 573 (error) ? "failed" : "success"); 574 if (!error) { 575 pci_write_config(parent, reg, val | 0x9000, 2); 576 atadev->mode = ATA_UDMA4; 577 return; 578 } 579 } 580 if (udmamode >= 2) { 581 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 582 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 583 if (bootverbose) 584 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 585 (error) ? "failed" : "success"); 586 if (!error) { 587 pci_write_config(parent, reg, val | 0xa000, 2); 588 atadev->mode = ATA_UDMA2; 589 return; 590 } 591 } 592 } else if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 593 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 594 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 595 if (bootverbose) 596 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 597 (error) ? "failed" : "success"); 598 if (!error) { 599 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 600 atadev->mode = ATA_UDMA2; 601 return; 602 } 603 } 604 if (wdmamode >=2 && apiomode >= 4) { 605 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 606 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 607 if (bootverbose) 608 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n", 609 (error) ? "failed" : "success"); 610 if (!error) { 611 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 612 atadev->mode = ATA_WDMA2; 613 return; 614 } 615 } 616 /* we could set PIO mode timings, but we assume the BIOS did that */ 617 break; 618 619 case 0x06491095: /* CMD 649 ATA100 controller */ 620 if (udmamode >= 5) { 621 u_int8_t umode; 622 623 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 624 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 625 if (bootverbose) 626 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n", 627 (error) ? "failed" : "success"); 628 if (!error) { 629 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1); 630 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 631 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 632 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1); 633 atadev->mode = ATA_UDMA5; 634 return; 635 } 636 } 637 /* FALLTHROUGH */ 638 639 case 0x06481095: /* CMD 648 ATA66 controller */ 640 if (udmamode >= 4) { 641 u_int8_t umode; 642 643 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 644 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 645 if (bootverbose) 646 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n", 647 (error) ? "failed" : "success"); 648 if (!error) { 649 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1); 650 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 651 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 652 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1); 653 atadev->mode = ATA_UDMA4; 654 return; 655 } 656 } 657 if (udmamode >= 2) { 658 u_int8_t umode; 659 660 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 661 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 662 if (bootverbose) 663 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n", 664 (error) ? "failed" : "success"); 665 if (!error) { 666 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1); 667 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 668 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 669 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1); 670 atadev->mode = ATA_UDMA2; 671 return; 672 } 673 } 674 /* make sure eventual UDMA mode from the BIOS is disabled */ 675 pci_write_config(parent, ch->unit ? 0x7b : 0x73, 676 pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1)& 677 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 678 /* FALLTHROUGH */ 679 680 case 0x06461095: /* CMD 646 ATA controller */ 681 if (wdmamode >= 2 && apiomode >= 4) { 682 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 683 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 684 if (bootverbose) 685 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n", 686 error ? "failed" : "success"); 687 if (!error) { 688 int32_t offset = (devno < 3) ? (devno << 1) : 7; 689 690 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 691 atadev->mode = ATA_WDMA2; 692 return; 693 } 694 } 695 /* we could set PIO mode timings, but we assume the BIOS did that */ 696 break; 697 698 case 0xc6931080: /* Cypress 82c693 ATA controller */ 699 if (wdmamode >= 2 && apiomode >= 4) { 700 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 701 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 702 if (bootverbose) 703 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n", 704 error ? "failed" : "success"); 705 if (!error) { 706 pci_write_config(ch->dev, ch->unit ? 0x4e:0x4c, 0x2020, 2); 707 atadev->mode = ATA_WDMA2; 708 return; 709 } 710 } 711 /* we could set PIO mode timings, but we assume the BIOS did that */ 712 break; 713 714 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 715 ch->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 716 if (udmamode >= 2) { 717 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 718 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 719 if (bootverbose) 720 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n", 721 (error) ? "failed" : "success"); 722 if (!error) { 723 cyrix_timing(ch, devno, ATA_UDMA2); 724 atadev->mode = ATA_UDMA2; 725 return; 726 } 727 } 728 if (wdmamode >= 2 && apiomode >= 4) { 729 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 730 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 731 if (bootverbose) 732 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n", 733 (error) ? "failed" : "success"); 734 if (!error) { 735 cyrix_timing(ch, devno, ATA_WDMA2); 736 atadev->mode = ATA_WDMA2; 737 return; 738 } 739 } 740 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 741 ATA_PIO0 + apiomode, ATA_C_F_SETXFER, 742 ATA_WAIT_READY); 743 if (bootverbose) 744 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n", 745 (error) ? "failed" : "success", 746 ata_mode2str(ATA_PIO0 + apiomode)); 747 cyrix_timing(ch, devno, ATA_PIO0 + apiomode); 748 atadev->mode = ATA_PIO0 + apiomode; 749 return; 750 751 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */ 752 if (udmamode >= 5 && pci_get_revid(parent) >= 0x92) { 753 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 754 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 755 if (bootverbose) 756 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n", 757 (error) ? "failed" : "success"); 758 if (!error) { 759 u_int16_t reg56; 760 761 pci_write_config(parent, 0x54, 762 pci_read_config(parent, 0x54, 1) | 763 (0x01 << devno), 1); 764 reg56 = pci_read_config(parent, 0x56, 2); 765 reg56 &= ~(0xf << (devno * 4)); 766 reg56 |= (0x5 << (devno * 4)); 767 pci_write_config(parent, 0x56, reg56, 2); 768 atadev->mode = ATA_UDMA5; 769 return; 770 } 771 } 772 if (udmamode >= 4) { 773 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 774 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 775 if (bootverbose) 776 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n", 777 (error) ? "failed" : "success"); 778 if (!error) { 779 u_int16_t reg56; 780 781 pci_write_config(parent, 0x54, 782 pci_read_config(parent, 0x54, 1) | 783 (0x01 << devno), 1); 784 reg56 = pci_read_config(parent, 0x56, 2); 785 reg56 &= ~(0xf << (devno * 4)); 786 reg56 |= (0x4 << (devno * 4)); 787 pci_write_config(parent, 0x56, reg56, 2); 788 atadev->mode = ATA_UDMA4; 789 return; 790 } 791 } 792 /* FALLTHROUGH */ 793 794 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 795 if (udmamode >= 2) { 796 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 797 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 798 if (bootverbose) 799 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n", 800 (error) ? "failed" : "success"); 801 if (!error) { 802 u_int16_t reg56; 803 804 pci_write_config(parent, 0x54, 805 pci_read_config(parent, 0x54, 1) | 806 (0x01 << devno), 1); 807 reg56 = pci_read_config(parent, 0x56, 2); 808 reg56 &= ~(0xf << (devno * 4)); 809 reg56 |= (0x2 << (devno * 4)); 810 pci_write_config(parent, 0x56, reg56, 2); 811 atadev->mode = ATA_UDMA2; 812 return; 813 } 814 } 815 if (wdmamode >= 2 && apiomode >= 4) { 816 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 817 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 818 if (bootverbose) 819 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n", 820 (error) ? "failed" : "success"); 821 if (!error) { 822 int offset = (ch->unit * 2) + (device == ATA_MASTER); 823 int word44 = pci_read_config(parent, 0x44, 4); 824 825 pci_write_config(parent, 0x54, 826 pci_read_config(parent, 0x54, 1) & 827 ~(0x01 << devno), 1); 828 word44 &= ~(0xff << (offset << 8)); 829 word44 |= (0x20 << (offset << 8)); 830 pci_write_config(parent, 0x44, 0x20, 4); 831 atadev->mode = ATA_WDMA2; 832 return; 833 } 834 } 835 /* we could set PIO mode timings, but we assume the BIOS did that */ 836 break; 837 838 case 0x4d69105a: /* Promise TX2 ATA133 controllers */ 839 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 840 if (udmamode >= 6 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 841 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 842 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 843 if (bootverbose) 844 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n", 845 (error) ? "failed" : "success"); 846 if (!error) { 847 atadev->mode = ATA_UDMA6; 848 return; 849 } 850 } 851 /* FALLTHROUGH */ 852 853 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 854 case 0x6268105a: /* Promise TX2 ATA100 controllers */ 855 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 856 if (udmamode >= 5 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 857 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 858 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 859 if (bootverbose) 860 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n", 861 (error) ? "failed" : "success"); 862 if (!error) { 863 atadev->mode = ATA_UDMA5; 864 return; 865 } 866 } 867 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 868 if (udmamode >= 4 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 869 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 870 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 871 if (bootverbose) 872 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n", 873 (error) ? "failed" : "success"); 874 if (!error) { 875 atadev->mode = ATA_UDMA4; 876 return; 877 } 878 } 879 if (udmamode >= 2) { 880 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 881 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 882 if (bootverbose) 883 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n", 884 (error) ? "failed" : "success"); 885 if (!error) { 886 atadev->mode = ATA_UDMA2; 887 return; 888 } 889 } 890 if (wdmamode >= 2 && apiomode >= 4) { 891 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 892 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 893 if (bootverbose) 894 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n", 895 (error) ? "failed" : "success"); 896 if (!error) { 897 atadev->mode = ATA_WDMA2; 898 return; 899 } 900 } 901 break; 902 903 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 904 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 905 if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 && 906 !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){ 907 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 908 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 909 if (bootverbose) 910 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n", 911 (error) ? "failed" : "success"); 912 if (!error) { 913 promise_timing(ch, devno, ATA_UDMA5); 914 atadev->mode = ATA_UDMA5; 915 return; 916 } 917 } 918 /* FALLTHROUGH */ 919 920 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 921 if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 && 922 !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){ 923 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 924 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 925 if (bootverbose) 926 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n", 927 (error) ? "failed" : "success"); 928 if (!error) { 929 promise_timing(ch, devno, ATA_UDMA4); 930 atadev->mode = ATA_UDMA4; 931 return; 932 } 933 } 934 /* FALLTHROUGH */ 935 936 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 937 if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) { 938 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 939 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 940 if (bootverbose) 941 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n", 942 (error) ? "failed" : "success"); 943 if (!error) { 944 promise_timing(ch, devno, ATA_UDMA2); 945 atadev->mode = ATA_UDMA2; 946 return; 947 } 948 } 949 if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) { 950 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 951 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 952 if (bootverbose) 953 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n", 954 (error) ? "failed" : "success"); 955 if (!error) { 956 promise_timing(ch, devno, ATA_WDMA2); 957 atadev->mode = ATA_WDMA2; 958 return; 959 } 960 } 961 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 962 ATA_PIO0 + apiomode, 963 ATA_C_F_SETXFER, ATA_WAIT_READY); 964 if (bootverbose) 965 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n", 966 (error) ? "failed" : "success", 967 (apiomode >= 0) ? apiomode : 0); 968 promise_timing(ch, devno, ATA_PIO0 + apiomode); 969 atadev->mode = ATA_PIO0 + apiomode; 970 return; 971 972 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */ 973 case 0x00051103: /* HighPoint HPT372 controllers */ 974 case 0x00081103: /* HighPoint HPT374 controllers */ 975 if (!ATAPI_DEVICE(ch, device) && udmamode >= 6 && hpt_cable80(ch) && 976 ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) || 977 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01) || 978 (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07))) { 979 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 980 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 981 if (bootverbose) 982 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n", 983 (error) ? "failed" : "success"); 984 if (!error) { 985 hpt_timing(ch, devno, ATA_UDMA6); 986 atadev->mode = ATA_UDMA6; 987 return; 988 } 989 } 990 if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 && hpt_cable80(ch) && 991 ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) || 992 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01) || 993 (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07))) { 994 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 995 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 996 if (bootverbose) 997 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n", 998 (error) ? "failed" : "success"); 999 if (!error) { 1000 hpt_timing(ch, devno, ATA_UDMA5); 1001 atadev->mode = ATA_UDMA5; 1002 return; 1003 } 1004 } 1005 if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 && hpt_cable80(ch)) { 1006 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1007 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1008 if (bootverbose) 1009 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n", 1010 (error) ? "failed" : "success"); 1011 if (!error) { 1012 hpt_timing(ch, devno, ATA_UDMA4); 1013 atadev->mode = ATA_UDMA4; 1014 return; 1015 } 1016 } 1017 if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) { 1018 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1019 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1020 if (bootverbose) 1021 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n", 1022 (error) ? "failed" : "success"); 1023 if (!error) { 1024 hpt_timing(ch, devno, ATA_UDMA2); 1025 atadev->mode = ATA_UDMA2; 1026 return; 1027 } 1028 } 1029 if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) { 1030 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1031 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1032 if (bootverbose) 1033 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n", 1034 (error) ? "failed" : "success"); 1035 if (!error) { 1036 hpt_timing(ch, devno, ATA_WDMA2); 1037 atadev->mode = ATA_WDMA2; 1038 return; 1039 } 1040 } 1041 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1042 ATA_PIO0 + apiomode, 1043 ATA_C_F_SETXFER, ATA_WAIT_READY); 1044 if (bootverbose) 1045 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n", 1046 (error) ? "failed" : "success", 1047 (apiomode >= 0) ? apiomode : 0); 1048 hpt_timing(ch, devno, ATA_PIO0 + apiomode); 1049 atadev->mode = ATA_PIO0 + apiomode; 1050 return; 1051 1052 case 0x000116ca: /* Cenatek Rocket Drive controller */ 1053 if (wdmamode >= 0 && 1054 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & 1055 ((device==ATA_MASTER)?ATA_BMSTAT_DMA_MASTER:ATA_BMSTAT_DMA_SLAVE))) 1056 atadev->mode = ATA_DMA; 1057 else 1058 atadev->mode = ATA_PIO; 1059 return; 1060 1061 default: /* unknown controller chip */ 1062 /* better not try generic DMA on ATAPI devices it almost never works */ 1063 if ((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || 1064 (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE)) 1065 break; 1066 1067 /* if controller says its setup for DMA take the easy way out */ 1068 /* the downside is we dont know what DMA mode we are in */ 1069 if ((udmamode >= 0 || wdmamode >= 2) && 1070 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & 1071 ((device==ATA_MASTER) ? 1072 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 1073 atadev->mode = ATA_DMA; 1074 return; 1075 } 1076 1077 /* well, we have no support for this, but try anyways */ 1078 if ((wdmamode >= 2 && apiomode >= 4) && ch->r_bmio) { 1079 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1080 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1081 if (bootverbose) 1082 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n", 1083 (error) ? "failed" : "success"); 1084 if (!error) { 1085 atadev->mode = ATA_WDMA2; 1086 return; 1087 } 1088 } 1089 } 1090 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode, 1091 ATA_C_F_SETXFER, ATA_WAIT_READY); 1092 if (bootverbose) 1093 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n", 1094 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 1095 if (!error) 1096 atadev->mode = ATA_PIO0 + apiomode; 1097 else { 1098 if (bootverbose) 1099 ata_prtdev(atadev, "using PIO mode set by BIOS\n"); 1100 atadev->mode = ATA_PIO; 1101 } 1102 } 1103 1104 int 1105 ata_dmasetup(struct ata_channel *ch, int device, struct ata_dmaentry *dmatab, 1106 caddr_t data, int32_t count) 1107 { 1108 u_int32_t dma_count, dma_base; 1109 int i = 0; 1110 1111 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) { 1112 ata_printf(ch, device, "non aligned DMA transfer attempted\n"); 1113 return -1; 1114 } 1115 1116 if (!count) { 1117 ata_printf(ch, device, "zero length DMA transfer attempted\n"); 1118 return -1; 1119 } 1120 1121 dma_base = vtophys(data); 1122 dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 1123 data += dma_count; 1124 count -= dma_count; 1125 1126 while (count) { 1127 dmatab[i].base = dma_base; 1128 dmatab[i].count = (dma_count & 0xffff); 1129 i++; 1130 if (i >= ATA_DMA_ENTRIES) { 1131 ata_printf(ch, device, "too many segments in DMA table\n"); 1132 return -1; 1133 } 1134 dma_base = vtophys(data); 1135 dma_count = imin(count, PAGE_SIZE); 1136 data += imin(count, PAGE_SIZE); 1137 count -= imin(count, PAGE_SIZE); 1138 } 1139 dmatab[i].base = dma_base; 1140 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 1141 return 0; 1142 } 1143 1144 void 1145 ata_dmastart(struct ata_channel *ch, int device, 1146 struct ata_dmaentry *dmatab, int dir) 1147 { 1148 ch->flags |= ATA_DMA_ACTIVE; 1149 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab)); 1150 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 1151 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 1152 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) | 1153 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 1154 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 1155 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 1156 } 1157 1158 int 1159 ata_dmadone(struct ata_channel *ch) 1160 { 1161 int error; 1162 1163 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 1164 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 1165 ch->flags &= ~ATA_DMA_ACTIVE; 1166 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT); 1167 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 1168 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 1169 return error & ATA_BMSTAT_MASK; 1170 } 1171 1172 int 1173 ata_dmastatus(struct ata_channel *ch) 1174 { 1175 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 1176 } 1177 1178 static void 1179 cyrix_timing(struct ata_channel *ch, int devno, int mode) 1180 { 1181 u_int32_t reg20 = 0x0000e132; 1182 u_int32_t reg24 = 0x00017771; 1183 1184 switch (mode) { 1185 case ATA_PIO0: reg20 = 0x0000e132; break; 1186 case ATA_PIO1: reg20 = 0x00018121; break; 1187 case ATA_PIO2: reg20 = 0x00024020; break; 1188 case ATA_PIO3: reg20 = 0x00032010; break; 1189 case ATA_PIO4: reg20 = 0x00040010; break; 1190 case ATA_WDMA2: reg24 = 0x00002020; break; 1191 case ATA_UDMA2: reg24 = 0x00911030; break; 1192 } 1193 ATA_OUTL(ch->r_bmio, (devno << 3) + 0x20, reg20); 1194 ATA_OUTL(ch->r_bmio, (devno << 3) + 0x24, reg24); 1195 } 1196 1197 static void 1198 promise_timing(struct ata_channel *ch, int devno, int mode) 1199 { 1200 u_int32_t timing = 0; 1201 struct promise_timing { 1202 u_int8_t pa:4; 1203 u_int8_t prefetch:1; 1204 u_int8_t iordy:1; 1205 u_int8_t errdy:1; 1206 u_int8_t syncin:1; 1207 u_int8_t pb:5; 1208 u_int8_t mb:3; 1209 u_int8_t mc:4; 1210 u_int8_t dmaw:1; 1211 u_int8_t dmar:1; 1212 u_int8_t iordyp:1; 1213 u_int8_t dmarqp:1; 1214 u_int8_t reserved:8; 1215 } *t = (struct promise_timing*)&timing; 1216 1217 t->iordy = 1; t->iordyp = 1; 1218 if (mode >= ATA_DMA) { 1219 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1220 } 1221 1222 switch (ch->chiptype) { 1223 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1224 switch (mode) { 1225 default: 1226 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1227 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1228 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1229 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1230 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1231 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1232 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1233 } 1234 break; 1235 1236 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1237 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1238 case 0x0d30105a: /* Promise OEM ATA 100 */ 1239 switch (mode) { 1240 default: 1241 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1242 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1243 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1244 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1245 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1246 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1247 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1248 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1249 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1250 } 1251 break; 1252 } 1253 pci_write_config(device_get_parent(ch->dev), 0x60 + (devno<<2), timing, 4); 1254 } 1255 1256 static void 1257 hpt_timing(struct ata_channel *ch, int devno, int mode) 1258 { 1259 device_t parent = device_get_parent(ch->dev); 1260 u_int32_t timing; 1261 1262 if (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07) { 1263 switch (mode) { /* HPT374 */ 1264 case ATA_PIO0: timing = 0x0ac1f48a; break; 1265 case ATA_PIO1: timing = 0x0ac1f465; break; 1266 case ATA_PIO2: timing = 0x0a81f454; break; 1267 case ATA_PIO3: timing = 0x0a81f443; break; 1268 case ATA_PIO4: timing = 0x0a81f442; break; 1269 case ATA_WDMA2: timing = 0x22808242; break; 1270 case ATA_UDMA2: timing = 0x120c8242; break; 1271 case ATA_UDMA4: timing = 0x12ac8242; break; 1272 case ATA_UDMA5: timing = 0x12848242; break; 1273 case ATA_UDMA6: timing = 0x12808242; break; 1274 default: timing = 0x0d029d5e; 1275 } 1276 } 1277 else if ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) || 1278 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01)) { 1279 switch (mode) { /* HPT372 */ 1280 case ATA_PIO0: timing = 0x0d029d5e; break; 1281 case ATA_PIO1: timing = 0x0d029d26; break; 1282 case ATA_PIO2: timing = 0x0c829ca6; break; 1283 case ATA_PIO3: timing = 0x0c829c84; break; 1284 case ATA_PIO4: timing = 0x0c829c62; break; 1285 case ATA_WDMA2: timing = 0x2c829262; break; 1286 case ATA_UDMA2: timing = 0x1c91dc62; break; 1287 case ATA_UDMA4: timing = 0x1c8ddc62; break; 1288 case ATA_UDMA5: timing = 0x1c6ddc62; break; 1289 case ATA_UDMA6: timing = 0x1c81dc62; break; 1290 default: timing = 0x0d029d5e; 1291 } 1292 } 1293 else if (ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x03) { 1294 switch (mode) { /* HPT370 */ 1295 case ATA_PIO0: timing = 0x06914e57; break; 1296 case ATA_PIO1: timing = 0x06914e43; break; 1297 case ATA_PIO2: timing = 0x06514e33; break; 1298 case ATA_PIO3: timing = 0x06514e22; break; 1299 case ATA_PIO4: timing = 0x06514e21; break; 1300 case ATA_WDMA2: timing = 0x26514e21; break; 1301 case ATA_UDMA2: timing = 0x16494e31; break; 1302 case ATA_UDMA4: timing = 0x16454e31; break; 1303 case ATA_UDMA5: timing = 0x16454e31; break; 1304 default: timing = 0x06514e57; 1305 } 1306 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1307 } 1308 else { /* HPT36[68] */ 1309 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1310 case 0x85: /* 25Mhz */ 1311 switch (mode) { 1312 case ATA_PIO0: timing = 0x40d08585; break; 1313 case ATA_PIO1: timing = 0x40d08572; break; 1314 case ATA_PIO2: timing = 0x40ca8542; break; 1315 case ATA_PIO3: timing = 0x40ca8532; break; 1316 case ATA_PIO4: timing = 0x40ca8521; break; 1317 case ATA_WDMA2: timing = 0x20ca8521; break; 1318 case ATA_UDMA2: timing = 0x10cf8521; break; 1319 case ATA_UDMA4: timing = 0x10c98521; break; 1320 default: timing = 0x01208585; 1321 } 1322 break; 1323 default: 1324 case 0xa7: /* 33MHz */ 1325 switch (mode) { 1326 case ATA_PIO0: timing = 0x40d0a7aa; break; 1327 case ATA_PIO1: timing = 0x40d0a7a3; break; 1328 case ATA_PIO2: timing = 0x40d0a753; break; 1329 case ATA_PIO3: timing = 0x40c8a742; break; 1330 case ATA_PIO4: timing = 0x40c8a731; break; 1331 case ATA_WDMA2: timing = 0x20c8a731; break; 1332 case ATA_UDMA2: timing = 0x10caa731; break; 1333 case ATA_UDMA4: timing = 0x10c9a731; break; 1334 default: timing = 0x0120a7a7; 1335 } 1336 break; 1337 case 0xd9: /* 40Mhz */ 1338 switch (mode) { 1339 case ATA_PIO0: timing = 0x4018d9d9; break; 1340 case ATA_PIO1: timing = 0x4010d9c7; break; 1341 case ATA_PIO2: timing = 0x4010d997; break; 1342 case ATA_PIO3: timing = 0x4010d974; break; 1343 case ATA_PIO4: timing = 0x4008d963; break; 1344 case ATA_WDMA2: timing = 0x2008d943; break; 1345 case ATA_UDMA2: timing = 0x100bd943; break; 1346 case ATA_UDMA4: timing = 0x100fd943; break; 1347 default: timing = 0x0120d9d9; 1348 } 1349 } 1350 } 1351 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1352 } 1353 1354 static int 1355 hpt_cable80(struct ata_channel *ch) 1356 { 1357 device_t parent = device_get_parent(ch->dev); 1358 u_int8_t reg, val, res; 1359 1360 if (ch->chiptype == 0x00081103 && pci_get_function(parent) == 1) { 1361 reg = ch->unit ? 0x57 : 0x53; 1362 val = pci_read_config(parent, reg, 1); 1363 pci_write_config(parent, reg, val | 0x80, 1); 1364 } 1365 else { 1366 reg = 0x5b; 1367 val = pci_read_config(parent, reg, 1); 1368 pci_write_config(parent, reg, val & 0xfe, 1); 1369 } 1370 res = pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x01 : 0x02); 1371 pci_write_config(parent, reg, val, 1); 1372 return !res; 1373 } 1374