1 /*- 2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include "pci.h" 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/ata.h> 35 #include <sys/bio.h> 36 #include <sys/malloc.h> 37 #include <sys/bus.h> 38 #include <sys/disk.h> 39 #include <sys/devicestat.h> 40 #include <vm/vm.h> 41 #include <vm/pmap.h> 42 #include <pci/pcivar.h> 43 #include <machine/bus.h> 44 #include <sys/rman.h> 45 #include <dev/ata/ata-all.h> 46 47 /* prototypes */ 48 static void cyrix_timing(struct ata_softc *, int, int); 49 static void promise_timing(struct ata_softc *, int, int); 50 static void hpt_timing(struct ata_softc *, int, int); 51 52 /* misc defines */ 53 #ifdef __alpha__ 54 #undef vtophys 55 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 56 #endif 57 #define ATAPI_DEVICE(scp, device) \ 58 ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || \ 59 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 60 61 62 void * 63 ata_dmaalloc(struct ata_softc *scp, int device) 64 { 65 void *dmatab; 66 67 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) { 68 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 69 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 70 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 71 free(dmatab, M_DEVBUF); 72 dmatab = NULL; 73 } 74 } 75 return dmatab; 76 } 77 78 void 79 ata_dmainit(struct ata_softc *scp, int device, 80 int apiomode, int wdmamode, int udmamode) 81 { 82 device_t parent = device_get_parent(scp->dev); 83 int devno = (scp->channel << 1) + ATA_DEV(device); 84 int error; 85 86 /* set our most pessimistic default mode */ 87 scp->mode[ATA_DEV(device)] = ATA_PIO; 88 89 if (!scp->r_bmio) 90 return; 91 92 /* if simplex controller, only allow DMA on primary channel */ 93 if (scp->channel == 1) { 94 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 95 ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 96 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 97 if (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 98 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 99 return; 100 } 101 } 102 103 /* DMA engine address alignment is usually 1 word (2 bytes) */ 104 scp->alignment = 0x1; 105 106 #if 1 107 if (udmamode > 2 && !ATA_PARAM(scp, device)->hwres_cblid) { 108 ata_printf(scp, device, 109 "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 110 udmamode = 2; 111 } 112 #endif 113 switch (scp->chiptype) { 114 115 case 0x248a8086: /* Intel ICH3 mobile */ 116 case 0x248b8086: /* Intel ICH3 */ 117 case 0x244a8086: /* Intel ICH2 mobile */ 118 case 0x244b8086: /* Intel ICH2 */ 119 if (udmamode >= 5) { 120 int32_t mask48, new48; 121 int16_t word54; 122 123 word54 = pci_read_config(parent, 0x54, 2); 124 if (word54 & (0x10 << devno)) { 125 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 126 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 127 if (bootverbose) 128 ata_printf(scp, device, 129 "%s setting UDMA5 on Intel chip\n", 130 (error) ? "failed" : "success"); 131 if (!error) { 132 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 133 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 134 pci_write_config(parent, 0x48, 135 (pci_read_config(parent, 0x48, 4) & 136 ~mask48) | new48, 4); 137 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 138 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 139 return; 140 } 141 } 142 } 143 /* make sure eventual ATA100 mode from the BIOS is disabled */ 144 pci_write_config(parent, 0x54, 145 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 146 /* FALLTHROUGH */ 147 148 case 0x24118086: /* Intel ICH */ 149 case 0x76018086: /* Intel ICH */ 150 if (udmamode >= 4) { 151 int32_t mask48, new48; 152 int16_t word54; 153 154 word54 = pci_read_config(parent, 0x54, 2); 155 if (word54 & (0x10 << devno)) { 156 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 157 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 158 if (bootverbose) 159 ata_printf(scp, device, 160 "%s setting UDMA4 on Intel chip\n", 161 (error) ? "failed" : "success"); 162 if (!error) { 163 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 164 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 165 pci_write_config(parent, 0x48, 166 (pci_read_config(parent, 0x48, 4) & 167 ~mask48) | new48, 4); 168 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 169 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 170 return; 171 } 172 } 173 } 174 /* make sure eventual ATA66 mode from the BIOS is disabled */ 175 pci_write_config(parent, 0x54, 176 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 177 /* FALLTHROUGH */ 178 179 case 0x71118086: /* Intel PIIX4 */ 180 case 0x84CA8086: /* Intel PIIX4 */ 181 case 0x71998086: /* Intel PIIX4e */ 182 case 0x24218086: /* Intel ICH0 */ 183 if (udmamode >= 2) { 184 int32_t mask48, new48; 185 186 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 187 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 188 if (bootverbose) 189 ata_printf(scp, device, "%s setting UDMA2 on Intel chip\n", 190 (error) ? "failed" : "success"); 191 if (!error) { 192 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 193 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 194 pci_write_config(parent, 0x48, 195 (pci_read_config(parent, 0x48, 4) & 196 ~mask48) | new48, 4); 197 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 198 return; 199 } 200 } 201 /* make sure eventual ATA33 mode from the BIOS is disabled */ 202 pci_write_config(parent, 0x48, 203 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 204 /* FALLTHROUGH */ 205 206 case 0x70108086: /* Intel PIIX3 */ 207 if (wdmamode >= 2 && apiomode >= 4) { 208 int32_t mask40, new40, mask44, new44; 209 210 /* if SITRE not set doit for both channels */ 211 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 212 new40 = pci_read_config(parent, 0x40, 4); 213 new44 = pci_read_config(parent, 0x44, 4); 214 if (!(new40 & 0x00004000)) { 215 new44 &= ~0x0000000f; 216 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 217 } 218 if (!(new40 & 0x40000000)) { 219 new44 &= ~0x000000f0; 220 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 221 } 222 new40 |= 0x40004000; 223 pci_write_config(parent, 0x40, new40, 4); 224 pci_write_config(parent, 0x44, new44, 4); 225 } 226 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 227 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 228 if (bootverbose) 229 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n", 230 (error) ? "failed" : "success"); 231 if (!error) { 232 if (device == ATA_MASTER) { 233 mask40 = 0x0000330f; 234 new40 = 0x00002307; 235 mask44 = 0; 236 new44 = 0; 237 } 238 else { 239 mask40 = 0x000000f0; 240 new40 = 0x00000070; 241 mask44 = 0x0000000f; 242 new44 = 0x0000000b; 243 } 244 if (scp->channel) { 245 mask40 <<= 16; 246 new40 <<= 16; 247 mask44 <<= 4; 248 new44 <<= 4; 249 } 250 pci_write_config(parent, 0x40, 251 (pci_read_config(parent, 0x40, 4) & ~mask40)| 252 new40, 4); 253 pci_write_config(parent, 0x44, 254 (pci_read_config(parent, 0x44, 4) & ~mask44)| 255 new44, 4); 256 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 257 return; 258 } 259 } 260 /* we could set PIO mode timings, but we assume the BIOS did that */ 261 break; 262 263 case 0x12308086: /* Intel PIIX */ 264 if (wdmamode >= 2 && apiomode >= 4) { 265 int32_t word40; 266 267 word40 = pci_read_config(parent, 0x40, 4); 268 word40 >>= scp->channel * 16; 269 270 /* Check for timing config usable for DMA on controller */ 271 if (!((word40 & 0x3300) == 0x2300 && 272 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 273 break; 274 275 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 276 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 277 if (bootverbose) 278 ata_printf(scp, device, 279 "%s setting WDMA2 on Intel chip\n", 280 (error) ? "failed" : "success"); 281 if (!error) { 282 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 283 return; 284 } 285 } 286 break; 287 288 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 289 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 290 if (pci_get_revid(parent) < 0xc2 && 291 scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 292 ata_printf(scp, device, 293 "Aladdin: two atapi devices on this channel, no DMA\n"); 294 break; 295 } 296 if (udmamode >= 5 && pci_get_revid(parent) >= 0xc4) { 297 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 298 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 299 if (bootverbose) 300 ata_printf(scp, device, 301 "%s setting UDMA5 on Acer chip\n", 302 (error) ? "failed" : "success"); 303 if (!error) { 304 int32_t word54 = pci_read_config(parent, 0x54, 4); 305 306 pci_write_config(parent, 0x4b, 307 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 308 word54 &= ~(0x000f000f << (devno << 2)); 309 word54 |= (0x000f0005 << (devno << 2)); 310 pci_write_config(parent, 0x54, word54, 4); 311 pci_write_config(parent, 0x53, 312 pci_read_config(parent, 0x53, 1) | 0x03, 1); 313 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 314 return; 315 } 316 } 317 if (udmamode >= 4 && pci_get_revid(parent) >= 0xc2) { 318 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 319 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 320 if (bootverbose) 321 ata_printf(scp, device, 322 "%s setting UDMA4 on Acer chip\n", 323 (error) ? "failed" : "success"); 324 if (!error) { 325 int32_t word54 = pci_read_config(parent, 0x54, 4); 326 327 pci_write_config(parent, 0x4b, 328 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 329 word54 &= ~(0x000f000f << (devno << 2)); 330 word54 |= (0x00080005 << (devno << 2)); 331 pci_write_config(parent, 0x54, word54, 4); 332 pci_write_config(parent, 0x53, 333 pci_read_config(parent, 0x53, 1) | 0x03, 1); 334 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 335 return; 336 } 337 } 338 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 339 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 340 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 341 if (bootverbose) 342 ata_printf(scp, device, 343 "%s setting UDMA2 on Acer chip\n", 344 (error) ? "failed" : "success"); 345 if (!error) { 346 int32_t word54 = pci_read_config(parent, 0x54, 4); 347 348 word54 &= ~(0x000f000f << (devno << 2)); 349 word54 |= (0x000a0005 << (devno << 2)); 350 pci_write_config(parent, 0x54, word54, 4); 351 pci_write_config(parent, 0x53, 352 pci_read_config(parent, 0x53, 1) | 0x03, 1); 353 scp->flags |= ATA_ATAPI_DMA_RO; 354 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 355 return; 356 } 357 } 358 359 /* make sure eventual UDMA mode from the BIOS is disabled */ 360 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 361 ~(0x0008 << (devno << 2)), 2); 362 363 if (wdmamode >= 2 && apiomode >= 4) { 364 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 365 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 366 if (bootverbose) 367 ata_printf(scp, device, 368 "%s setting WDMA2 on Acer chip\n", 369 (error) ? "failed" : "success"); 370 if (!error) { 371 pci_write_config(parent, 0x53, 372 pci_read_config(parent, 0x53, 1) | 0x03, 1); 373 scp->flags |= ATA_ATAPI_DMA_RO; 374 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 375 return; 376 } 377 } 378 pci_write_config(parent, 0x53, 379 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 380 /* we could set PIO mode timings, but we assume the BIOS did that */ 381 break; 382 383 case 0x74111022: /* AMD 766 */ 384 if (udmamode >= 5) { 385 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 386 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 387 if (bootverbose) 388 ata_printf(scp, device, 389 "%s setting UDMA5 on AMD chip\n", 390 (error) ? "failed" : "success"); 391 if (!error) { 392 pci_write_config(parent, 0x53 - devno, 0xc6, 1); 393 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 394 return; 395 } 396 } 397 /* FALLTHROUGH */ 398 399 case 0x74091022: /* AMD 756 */ 400 if (udmamode >= 4) { 401 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 402 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 403 if (bootverbose) 404 ata_printf(scp, device, 405 "%s setting UDMA4 on AMD chip\n", 406 (error) ? "failed" : "success"); 407 if (!error) { 408 pci_write_config(parent, 0x53 - devno, 0xc5, 1); 409 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 410 return; 411 } 412 } 413 goto via_82c586; 414 415 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 416 if (ata_find_dev(parent, 0x06861106, 0x40) || 417 ata_find_dev(parent, 0x82311106, 0) || 418 ata_find_dev(parent, 0x30741106, 0)) { /* 82C686b */ 419 if (udmamode >= 5) { 420 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 421 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 422 if (bootverbose) 423 ata_printf(scp, device, 424 "%s setting UDMA5 on VIA chip\n", 425 (error) ? "failed" : "success"); 426 if (!error) { 427 pci_write_config(parent, 0x53 - devno, 0xf0, 1); 428 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 429 return; 430 } 431 } 432 if (udmamode >= 4) { 433 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 434 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 435 if (bootverbose) 436 ata_printf(scp, device, 437 "%s setting UDMA4 on VIA chip\n", 438 (error) ? "failed" : "success"); 439 if (!error) { 440 pci_write_config(parent, 0x53 - devno, 0xf1, 1); 441 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 442 return; 443 } 444 } 445 if (udmamode >= 2) { 446 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 447 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 448 if (bootverbose) 449 ata_printf(scp, device, 450 "%s setting UDMA2 on VIA chip\n", 451 (error) ? "failed" : "success"); 452 if (!error) { 453 pci_write_config(parent, 0x53 - devno, 0xf4, 1); 454 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 455 return; 456 } 457 } 458 } 459 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 460 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 461 if (udmamode >= 4) { 462 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 463 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 464 if (bootverbose) 465 ata_printf(scp, device, 466 "%s setting UDMA4 on VIA chip\n", 467 (error) ? "failed" : "success"); 468 if (!error) { 469 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 470 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 471 return; 472 } 473 } 474 if (udmamode >= 2) { 475 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 476 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 477 if (bootverbose) 478 ata_printf(scp, device, 479 "%s setting UDMA2 on VIA chip\n", 480 (error) ? "failed" : "success"); 481 if (!error) { 482 pci_write_config(parent, 0x53 - devno, 0xea, 1); 483 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 484 return; 485 } 486 } 487 } 488 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 489 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 490 via_82c586: 491 if (udmamode >= 2) { 492 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 493 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 494 if (bootverbose) 495 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 496 (error) ? "failed" : "success", 497 ((scp->chiptype == 0x74091022) || 498 (scp->chiptype == 0x74111022)) ? "AMD" : "VIA"); 499 if (!error) { 500 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 501 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 502 return; 503 } 504 } 505 } 506 if (wdmamode >= 2 && apiomode >= 4) { 507 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 508 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 509 if (bootverbose) 510 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 511 (error) ? "failed" : "success", 512 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 513 if (!error) { 514 pci_write_config(parent, 0x53 - devno, 0x0b, 1); 515 pci_write_config(parent, 0x4b - devno, 0x31, 1); 516 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 517 return; 518 } 519 } 520 /* we could set PIO mode timings, but we assume the BIOS did that */ 521 break; 522 523 case 0x55131039: /* SiS 5591 */ 524 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */ 525 ata_find_dev(parent, 0x06331039, 0x00) || /* SiS 633 */ 526 ata_find_dev(parent, 0x06351039, 0x00) || /* SiS 635 */ 527 ata_find_dev(parent, 0x06451039, 0x00) || /* SiS 635 */ 528 ata_find_dev(parent, 0x07301039, 0x00) || /* SiS 730 */ 529 ata_find_dev(parent, 0x07331039, 0x00) || /* SiS 733 */ 530 ata_find_dev(parent, 0x07351039, 0x00)) { /* SiS 735 */ 531 int8_t reg = 0x40 + (devno << 1); 532 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 533 534 if (udmamode >= 5) { 535 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 536 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 537 if (bootverbose) 538 ata_printf(scp, device, 539 "%s setting UDMA5 on SiS chip\n", 540 (error) ? "failed" : "success"); 541 if (!error) { 542 pci_write_config(parent, reg, val | 0x8000, 2); 543 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 544 return; 545 } 546 } 547 if (udmamode >= 4) { 548 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 549 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 550 if (bootverbose) 551 ata_printf(scp, device, 552 "%s setting UDMA4 on SiS chip\n", 553 (error) ? "failed" : "success"); 554 if (!error) { 555 pci_write_config(parent, reg, val | 0x9000, 2); 556 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 557 return; 558 } 559 } 560 if (udmamode >= 2) { 561 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 562 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 563 if (bootverbose) 564 ata_printf(scp, device, 565 "%s setting UDMA2 on SiS chip\n", 566 (error) ? "failed" : "success"); 567 if (!error) { 568 pci_write_config(parent, reg, val | 0xb000, 2); 569 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 570 return; 571 } 572 } 573 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */ 574 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */ 575 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */ 576 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */ 577 int8_t reg = 0x40 + (devno << 1); 578 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 579 580 if (udmamode >= 4) { 581 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 582 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 583 if (bootverbose) 584 ata_printf(scp, device, 585 "%s setting UDMA4 on SiS chip\n", 586 (error) ? "failed" : "success"); 587 if (!error) { 588 pci_write_config(parent, reg, val | 0x9000, 2); 589 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 590 return; 591 } 592 } 593 if (udmamode >= 2) { 594 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 595 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 596 if (bootverbose) 597 ata_printf(scp, device, 598 "%s setting UDMA2 on SiS chip\n", 599 (error) ? "failed" : "success"); 600 if (!error) { 601 pci_write_config(parent, reg, val | 0xa000, 2); 602 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 603 return; 604 } 605 } 606 } else { /* SiS 5591 */ 607 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 608 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 609 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 610 if (bootverbose) 611 ata_printf(scp, device, 612 "%s setting UDMA2 on SiS chip\n", 613 (error) ? "failed" : "success"); 614 if (!error) { 615 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 616 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 617 return; 618 } 619 } 620 } 621 if (wdmamode >=2 && apiomode >= 4) { 622 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 623 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 624 if (bootverbose) 625 ata_printf(scp, device, 626 "%s setting WDMA2 on SiS chip\n", 627 (error) ? "failed" : "success"); 628 if (!error) { 629 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 630 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 631 return; 632 } 633 } 634 /* we could set PIO mode timings, but we assume the BIOS did that */ 635 break; 636 637 case 0x06491095: /* CMD 649 ATA100 controller */ 638 if (udmamode >= 5) { 639 u_int8_t umode; 640 641 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 642 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 643 if (bootverbose) 644 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 645 (error) ? "failed" : "success"); 646 if (!error) { 647 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 648 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 649 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 650 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 651 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 652 return; 653 } 654 } 655 /* FALLTHROUGH */ 656 657 case 0x06481095: /* CMD 648 ATA66 controller */ 658 if (udmamode >= 4) { 659 u_int8_t umode; 660 661 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 662 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 663 if (bootverbose) 664 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 665 (error) ? "failed" : "success"); 666 if (!error) { 667 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 668 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 669 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 670 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 671 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 672 return; 673 } 674 } 675 if (udmamode >= 2) { 676 u_int8_t umode; 677 678 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 679 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 680 if (bootverbose) 681 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 682 (error) ? "failed" : "success"); 683 if (!error) { 684 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 685 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 686 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 687 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 688 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 689 return; 690 } 691 } 692 /* make sure eventual UDMA mode from the BIOS is disabled */ 693 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 694 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 695 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 696 /* FALLTHROUGH */ 697 698 case 0x06461095: /* CMD 646 ATA controller */ 699 if (wdmamode >= 2 && apiomode >= 4) { 700 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 701 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 702 if (bootverbose) 703 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 704 error ? "failed" : "success"); 705 if (!error) { 706 int32_t offset = (devno < 3) ? (devno << 1) : 7; 707 708 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 709 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 710 return; 711 } 712 } 713 /* we could set PIO mode timings, but we assume the BIOS did that */ 714 break; 715 716 case 0xc6931080: /* Cypress 82c693 ATA controller */ 717 if (wdmamode >= 2 && apiomode >= 4) { 718 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 719 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 720 if (bootverbose) 721 ata_printf(scp, device, 722 "%s setting WDMA2 on Cypress chip\n", 723 error ? "failed" : "success"); 724 if (!error) { 725 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 726 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 727 return; 728 } 729 } 730 /* we could set PIO mode timings, but we assume the BIOS did that */ 731 break; 732 733 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 734 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 735 if (udmamode >= 2) { 736 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 737 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 738 if (bootverbose) 739 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 740 (error) ? "failed" : "success"); 741 if (!error) { 742 cyrix_timing(scp, devno, ATA_UDMA2); 743 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 744 return; 745 } 746 } 747 if (wdmamode >= 2 && apiomode >= 4) { 748 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 749 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 750 if (bootverbose) 751 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 752 (error) ? "failed" : "success"); 753 if (!error) { 754 cyrix_timing(scp, devno, ATA_WDMA2); 755 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 756 return; 757 } 758 } 759 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 760 ATA_PIO0 + apiomode, ATA_C_F_SETXFER, 761 ATA_WAIT_READY); 762 if (bootverbose) 763 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 764 (error) ? "failed" : "success", 765 ata_mode2str(ATA_PIO0 + apiomode)); 766 cyrix_timing(scp, devno, ATA_PIO0 + apiomode); 767 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 768 return; 769 770 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 771 if (udmamode >= 2) { 772 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 773 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 774 if (bootverbose) 775 ata_printf(scp, device, 776 "%s setting UDMA2 on ServerWorks chip\n", 777 (error) ? "failed" : "success"); 778 if (!error) { 779 u_int16_t reg56; 780 781 pci_write_config(parent, 0x54, 782 pci_read_config(parent, 0x54, 1) | 783 (0x01 << devno), 1); 784 reg56 = pci_read_config(parent, 0x56, 2); 785 reg56 &= ~(0xf << (devno * 4)); 786 reg56 |= (0x2 << (devno * 4)); 787 pci_write_config(parent, 0x56, reg56, 2); 788 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 789 return; 790 } 791 } 792 if (wdmamode >= 2 && apiomode >= 4) { 793 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 794 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 795 if (bootverbose) 796 ata_printf(scp, device, 797 "%s setting WDMA2 on ServerWorks chip\n", 798 (error) ? "failed" : "success"); 799 if (!error) { 800 int offset = (scp->channel * 2) + (device == ATA_MASTER); 801 int word44 = pci_read_config(parent, 0x44, 4); 802 803 pci_write_config(parent, 0x54, 804 pci_read_config(parent, 0x54, 1) & 805 ~(0x01 << devno), 1); 806 word44 &= ~(0xff << (offset << 8)); 807 word44 |= (0x20 << (offset << 8)); 808 pci_write_config(parent, 0x44, 0x20, 4); 809 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 810 return; 811 } 812 } 813 /* we could set PIO mode timings, but we assume the BIOS did that */ 814 break; 815 816 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 817 case 0x6268105a: /* Promise TX2v2 ATA100 controllers */ 818 case 0x4d69105a: /* Promise ATA133 controllers */ 819 ATA_OUTB(scp->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 820 if (udmamode >= 4 && !(ATA_INB(scp->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 821 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 822 ATA_UDMA + udmamode, ATA_C_F_SETXFER, 823 ATA_WAIT_READY); 824 if (bootverbose) 825 ata_printf(scp, device, "%s setting %s on Promise chip\n", 826 (error) ? "failed" : "success", 827 ata_mode2str(ATA_UDMA + udmamode)); 828 if (!error) { 829 scp->mode[ATA_DEV(device)] = ATA_UDMA + udmamode; 830 return; 831 } 832 } 833 if (udmamode >= 2) { 834 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 835 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 836 if (bootverbose) 837 ata_printf(scp, device, "%s setting %s on Promise chip\n", 838 (error) ? "failed" : "success", "UDMA2"); 839 if (!error) { 840 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 841 return; 842 } 843 } 844 if (wdmamode >= 2 && apiomode >= 4) { 845 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 846 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 847 if (bootverbose) 848 ata_printf(scp, device, "%s setting %s on Promise chip\n", 849 (error) ? "failed" : "success", "WDMA2"); 850 if (!error) { 851 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 852 return; 853 } 854 } 855 break; 856 857 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 858 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 859 if (!ATAPI_DEVICE(scp, device) && udmamode >= 5 && 860 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 861 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 862 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 863 if (bootverbose) 864 ata_printf(scp, device, 865 "%s setting UDMA5 on Promise chip\n", 866 (error) ? "failed" : "success"); 867 if (!error) { 868 promise_timing(scp, devno, ATA_UDMA5); 869 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 870 return; 871 } 872 } 873 /* FALLTHROUGH */ 874 875 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 876 if (!ATAPI_DEVICE(scp, device) && udmamode >= 4 && 877 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 878 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 879 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 880 if (bootverbose) 881 ata_printf(scp, device, 882 "%s setting UDMA4 on Promise chip\n", 883 (error) ? "failed" : "success"); 884 if (!error) { 885 promise_timing(scp, devno, ATA_UDMA4); 886 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 887 return; 888 } 889 } 890 /* FALLTHROUGH */ 891 892 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 893 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) { 894 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 895 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 896 if (bootverbose) 897 ata_printf(scp, device, 898 "%s setting UDMA2 on Promise chip\n", 899 (error) ? "failed" : "success"); 900 if (!error) { 901 promise_timing(scp, devno, ATA_UDMA2); 902 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 903 return; 904 } 905 } 906 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) { 907 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 908 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 909 if (bootverbose) 910 ata_printf(scp, device, 911 "%s setting WDMA2 on Promise chip\n", 912 (error) ? "failed" : "success"); 913 if (!error) { 914 promise_timing(scp, devno, ATA_WDMA2); 915 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 916 return; 917 } 918 } 919 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 920 ATA_PIO0 + apiomode, 921 ATA_C_F_SETXFER, ATA_WAIT_READY); 922 if (bootverbose) 923 ata_printf(scp, device, 924 "%s setting PIO%d on Promise chip\n", 925 (error) ? "failed" : "success", 926 (apiomode >= 0) ? apiomode : 0); 927 promise_timing(scp, devno, ATA_PIO0 + apiomode); 928 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 929 return; 930 931 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */ 932 if (!ATAPI_DEVICE(scp, device) && 933 udmamode >= 6 && pci_get_revid(parent) >= 0x05 && 934 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 935 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 936 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 937 if (bootverbose) 938 ata_printf(scp, device, 939 "%s setting UDMA6 on HighPoint chip\n", 940 (error) ? "failed" : "success"); 941 if (!error) { 942 hpt_timing(scp, devno, ATA_UDMA6); 943 scp->mode[ATA_DEV(device)] = ATA_UDMA6; 944 return; 945 } 946 } 947 if (!ATAPI_DEVICE(scp, device) && 948 udmamode >=5 && pci_get_revid(parent) >= 0x03 && 949 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 950 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 951 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 952 if (bootverbose) 953 ata_printf(scp, device, 954 "%s setting UDMA5 on HighPoint chip\n", 955 (error) ? "failed" : "success"); 956 if (!error) { 957 hpt_timing(scp, devno, ATA_UDMA5); 958 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 959 return; 960 } 961 } 962 if (!ATAPI_DEVICE(scp, device) && udmamode >=4 && 963 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 964 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 965 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 966 if (bootverbose) 967 ata_printf(scp, device, 968 "%s setting UDMA4 on HighPoint chip\n", 969 (error) ? "failed" : "success"); 970 if (!error) { 971 hpt_timing(scp, devno, ATA_UDMA4); 972 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 973 return; 974 } 975 } 976 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) { 977 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 978 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 979 if (bootverbose) 980 ata_printf(scp, device, 981 "%s setting UDMA2 on HighPoint chip\n", 982 (error) ? "failed" : "success"); 983 if (!error) { 984 hpt_timing(scp, devno, ATA_UDMA2); 985 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 986 return; 987 } 988 } 989 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) { 990 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 991 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 992 if (bootverbose) 993 ata_printf(scp, device, 994 "%s setting WDMA2 on HighPoint chip\n", 995 (error) ? "failed" : "success"); 996 if (!error) { 997 hpt_timing(scp, devno, ATA_WDMA2); 998 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 999 return; 1000 } 1001 } 1002 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 1003 ATA_PIO0 + apiomode, 1004 ATA_C_F_SETXFER, ATA_WAIT_READY); 1005 if (bootverbose) 1006 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 1007 (error) ? "failed" : "success", 1008 (apiomode >= 0) ? apiomode : 0); 1009 hpt_timing(scp, devno, ATA_PIO0 + apiomode); 1010 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 1011 return; 1012 1013 default: /* unknown controller chip */ 1014 /* better not try generic DMA on ATAPI devices it almost never works */ 1015 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 1016 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 1017 break; 1018 1019 /* if controller says its setup for DMA take the easy way out */ 1020 /* the downside is we dont know what DMA mode we are in */ 1021 if ((udmamode >= 0 || wdmamode > 1) && 1022 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 1023 ((device==ATA_MASTER) ? 1024 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 1025 scp->mode[ATA_DEV(device)] = ATA_DMA; 1026 return; 1027 } 1028 1029 /* well, we have no support for this, but try anyways */ 1030 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) { 1031 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 1032 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1033 if (bootverbose) 1034 ata_printf(scp, device, 1035 "%s setting WDMA2 on generic chip\n", 1036 (error) ? "failed" : "success"); 1037 if (!error) { 1038 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 1039 return; 1040 } 1041 } 1042 } 1043 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode, 1044 ATA_C_F_SETXFER,ATA_WAIT_READY); 1045 if (bootverbose) 1046 ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 1047 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 1048 if (!error) 1049 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 1050 else { 1051 if (bootverbose) 1052 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 1053 scp->mode[ATA_DEV(device)] = ATA_PIO; 1054 } 1055 } 1056 1057 int 1058 ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 1059 caddr_t data, int32_t count) 1060 { 1061 u_int32_t dma_count, dma_base; 1062 int i = 0; 1063 1064 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 1065 ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 1066 return -1; 1067 } 1068 1069 if (!count) { 1070 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 1071 return -1; 1072 } 1073 1074 dma_base = vtophys(data); 1075 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 1076 data += dma_count; 1077 count -= dma_count; 1078 1079 while (count) { 1080 dmatab[i].base = dma_base; 1081 dmatab[i].count = (dma_count & 0xffff); 1082 i++; 1083 if (i >= ATA_DMA_ENTRIES) { 1084 ata_printf(scp, device, "too many segments in DMA table\n"); 1085 return -1; 1086 } 1087 dma_base = vtophys(data); 1088 dma_count = min(count, PAGE_SIZE); 1089 data += min(count, PAGE_SIZE); 1090 count -= min(count, PAGE_SIZE); 1091 } 1092 dmatab[i].base = dma_base; 1093 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 1094 return 0; 1095 } 1096 1097 void 1098 ata_dmastart(struct ata_softc *scp, int device, 1099 struct ata_dmaentry *dmatab, int dir) 1100 { 1101 scp->flags |= ATA_DMA_ACTIVE; 1102 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab)); 1103 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 1104 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 1105 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) | 1106 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 1107 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 1108 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 1109 } 1110 1111 int 1112 ata_dmadone(struct ata_softc *scp) 1113 { 1114 int error; 1115 1116 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 1117 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 1118 scp->flags &= ~ATA_DMA_ACTIVE; 1119 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT); 1120 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 1121 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 1122 return error & ATA_BMSTAT_MASK; 1123 } 1124 1125 int 1126 ata_dmastatus(struct ata_softc *scp) 1127 { 1128 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 1129 } 1130 1131 static void 1132 cyrix_timing(struct ata_softc *scp, int devno, int mode) 1133 { 1134 u_int32_t reg20 = 0x0000e132; 1135 u_int32_t reg24 = 0x00017771; 1136 1137 switch (mode) { 1138 case ATA_PIO0: reg20 = 0x0000e132; break; 1139 case ATA_PIO1: reg20 = 0x00018121; break; 1140 case ATA_PIO2: reg20 = 0x00024020; break; 1141 case ATA_PIO3: reg20 = 0x00032010; break; 1142 case ATA_PIO4: reg20 = 0x00040010; break; 1143 case ATA_WDMA2: reg24 = 0x00002020; break; 1144 case ATA_UDMA2: reg24 = 0x00911030; break; 1145 } 1146 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20); 1147 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24); 1148 } 1149 1150 static void 1151 promise_timing(struct ata_softc *scp, int devno, int mode) 1152 { 1153 u_int32_t timing = 0; 1154 struct promise_timing { 1155 u_int8_t pa:4; 1156 u_int8_t prefetch:1; 1157 u_int8_t iordy:1; 1158 u_int8_t errdy:1; 1159 u_int8_t syncin:1; 1160 u_int8_t pb:5; 1161 u_int8_t mb:3; 1162 u_int8_t mc:4; 1163 u_int8_t dmaw:1; 1164 u_int8_t dmar:1; 1165 u_int8_t iordyp:1; 1166 u_int8_t dmarqp:1; 1167 u_int8_t reserved:8; 1168 } *t = (struct promise_timing*)&timing; 1169 1170 t->iordy = 1; t->iordyp = 1; 1171 if (mode >= ATA_DMA) { 1172 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1173 } 1174 1175 switch (scp->chiptype) { 1176 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1177 switch (mode) { 1178 default: 1179 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1180 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1181 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1182 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1183 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1184 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1185 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1186 } 1187 break; 1188 1189 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1190 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1191 case 0x0d30105a: /* Promise OEM ATA 100 */ 1192 switch (mode) { 1193 default: 1194 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1195 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1196 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1197 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1198 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1199 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1200 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1201 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1202 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1203 } 1204 break; 1205 } 1206 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 1207 } 1208 1209 static void 1210 hpt_timing(struct ata_softc *scp, int devno, int mode) 1211 { 1212 device_t parent = device_get_parent(scp->dev); 1213 u_int32_t timing; 1214 if (pci_get_revid(parent) >= 0x05) { /* HPT372 */ 1215 switch (mode) { 1216 case ATA_PIO0: timing = 0x0d029d5e; break; 1217 case ATA_PIO1: timing = 0x0d029d26; break; 1218 case ATA_PIO2: timing = 0x0c829ca6; break; 1219 case ATA_PIO3: timing = 0x0c829c84; break; 1220 case ATA_PIO4: timing = 0x0c829c62; break; 1221 case ATA_WDMA2: timing = 0x2c829262; break; 1222 case ATA_UDMA2: timing = 0x1c91dc62; break; 1223 case ATA_UDMA4: timing = 0x1c8ddc62; break; 1224 case ATA_UDMA5: timing = 0x1c6ddc62; break; 1225 case ATA_UDMA6: timing = 0x1c81dc62; break; 1226 default: timing = 0x0d029d5e; 1227 } 1228 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1229 pci_write_config(parent, 0x5b, 0x20, 1); 1230 } 1231 else if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 1232 switch (mode) { 1233 case ATA_PIO0: timing = 0x06914e57; break; 1234 case ATA_PIO1: timing = 0x06914e43; break; 1235 case ATA_PIO2: timing = 0x06514e33; break; 1236 case ATA_PIO3: timing = 0x06514e22; break; 1237 case ATA_PIO4: timing = 0x06514e21; break; 1238 case ATA_WDMA2: timing = 0x26514e21; break; 1239 case ATA_UDMA2: timing = 0x16494e31; break; 1240 case ATA_UDMA4: timing = 0x16454e31; break; 1241 case ATA_UDMA5: timing = 0x16454e31; break; 1242 default: timing = 0x06514e57; 1243 } 1244 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1245 pci_write_config(parent, 0x5b, 0x22, 1); 1246 } 1247 else { /* HPT36[68] */ 1248 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1249 case 0x85: /* 25Mhz */ 1250 switch (mode) { 1251 case ATA_PIO0: timing = 0xc0d08585; break; 1252 case ATA_PIO1: timing = 0xc0d08572; break; 1253 case ATA_PIO2: timing = 0xc0ca8542; break; 1254 case ATA_PIO3: timing = 0xc0ca8532; break; 1255 case ATA_PIO4: timing = 0xc0ca8521; break; 1256 case ATA_WDMA2: timing = 0xa0ca8521; break; 1257 case ATA_UDMA2: timing = 0x90cf8521; break; 1258 case ATA_UDMA4: timing = 0x90c98521; break; 1259 default: timing = 0x01208585; 1260 } 1261 break; 1262 default: 1263 case 0xa7: /* 33MHz */ 1264 switch (mode) { 1265 case ATA_PIO0: timing = 0xc0d0a7aa; break; 1266 case ATA_PIO1: timing = 0xc0d0a7a3; break; 1267 case ATA_PIO2: timing = 0xc0d0a753; break; 1268 case ATA_PIO3: timing = 0xc0c8a742; break; 1269 case ATA_PIO4: timing = 0xc0c8a731; break; 1270 case ATA_WDMA2: timing = 0xa0c8a731; break; 1271 case ATA_UDMA2: timing = 0x90caa731; break; 1272 case ATA_UDMA4: timing = 0x90c9a731; break; 1273 default: timing = 0x0120a7a7; 1274 } 1275 break; 1276 case 0xd9: /* 40Mhz */ 1277 switch (mode) { 1278 case ATA_PIO0: timing = 0xc018d9d9; break; 1279 case ATA_PIO1: timing = 0xc010d9c7; break; 1280 case ATA_PIO2: timing = 0xc010d997; break; 1281 case ATA_PIO3: timing = 0xc010d974; break; 1282 case ATA_PIO4: timing = 0xc008d963; break; 1283 case ATA_WDMA2: timing = 0xa008d943; break; 1284 case ATA_UDMA2: timing = 0x900bd943; break; 1285 case ATA_UDMA4: timing = 0x900fd943; break; 1286 default: timing = 0x0120d9d9; 1287 } 1288 } 1289 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 1290 } 1291 } 1292