1 /*- 2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include "pci.h" 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/ata.h> 35 #include <sys/bio.h> 36 #include <sys/malloc.h> 37 #include <sys/bus.h> 38 #include <sys/disk.h> 39 #include <sys/devicestat.h> 40 #include <vm/vm.h> 41 #include <vm/pmap.h> 42 #include <pci/pcivar.h> 43 #include <machine/bus.h> 44 #include <sys/rman.h> 45 #include <dev/ata/ata-all.h> 46 47 /* prototypes */ 48 static void cyrix_timing(struct ata_softc *, int, int); 49 static void promise_timing(struct ata_softc *, int, int); 50 static void hpt_timing(struct ata_softc *, int, int); 51 52 /* misc defines */ 53 #ifdef __alpha__ 54 #undef vtophys 55 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 56 #endif 57 #define ATAPI_DEVICE(scp, device) \ 58 ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || \ 59 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 60 61 62 void * 63 ata_dmaalloc(struct ata_softc *scp, int device) 64 { 65 void *dmatab; 66 67 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) { 68 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 69 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 70 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 71 free(dmatab, M_DEVBUF); 72 dmatab = NULL; 73 } 74 } 75 return dmatab; 76 } 77 78 void 79 ata_dmainit(struct ata_softc *scp, int device, 80 int apiomode, int wdmamode, int udmamode) 81 { 82 device_t parent = device_get_parent(scp->dev); 83 int devno = (scp->channel << 1) + ATA_DEV(device); 84 int error; 85 86 /* set our most pessimistic default mode */ 87 scp->mode[ATA_DEV(device)] = ATA_PIO; 88 89 if (!scp->r_bmio) 90 return; 91 92 /* if simplex controller, only allow DMA on primary channel */ 93 if (scp->channel == 1) { 94 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 95 ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 96 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 97 if (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 98 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 99 return; 100 } 101 } 102 103 /* DMA engine address alignment is usually 1 word (2 bytes) */ 104 scp->alignment = 0x1; 105 106 #if 1 107 if (udmamode > 2 && !ATA_PARAM(scp, device)->hwres_cblid) { 108 ata_printf(scp, device, 109 "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 110 udmamode = 2; 111 } 112 #endif 113 switch (scp->chiptype) { 114 115 case 0x248a8086: /* Intel ICH3 mobile */ 116 case 0x248b8086: /* Intel ICH3 */ 117 case 0x244a8086: /* Intel ICH2 mobile */ 118 case 0x244b8086: /* Intel ICH2 */ 119 if (udmamode >= 5) { 120 int32_t mask48, new48; 121 int16_t word54; 122 123 word54 = pci_read_config(parent, 0x54, 2); 124 if (word54 & (0x10 << devno)) { 125 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 126 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 127 if (bootverbose) 128 ata_printf(scp, device, "%s setting UDMA5 on Intel chip\n", 129 (error) ? "failed" : "success"); 130 if (!error) { 131 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 132 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 133 pci_write_config(parent, 0x48, 134 (pci_read_config(parent, 0x48, 4) & 135 ~mask48) | new48, 4); 136 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 137 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 138 return; 139 } 140 } 141 } 142 /* make sure eventual ATA100 mode from the BIOS is disabled */ 143 pci_write_config(parent, 0x54, 144 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 145 /* FALLTHROUGH */ 146 147 case 0x24118086: /* Intel ICH */ 148 case 0x76018086: /* Intel ICH */ 149 if (udmamode >= 4) { 150 int32_t mask48, new48; 151 int16_t word54; 152 153 word54 = pci_read_config(parent, 0x54, 2); 154 if (word54 & (0x10 << devno)) { 155 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 156 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 157 if (bootverbose) 158 ata_printf(scp, device, "%s setting UDMA4 on Intel chip\n", 159 (error) ? "failed" : "success"); 160 if (!error) { 161 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 162 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 163 pci_write_config(parent, 0x48, 164 (pci_read_config(parent, 0x48, 4) & 165 ~mask48) | new48, 4); 166 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 167 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 168 return; 169 } 170 } 171 } 172 /* make sure eventual ATA66 mode from the BIOS is disabled */ 173 pci_write_config(parent, 0x54, 174 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 175 /* FALLTHROUGH */ 176 177 case 0x71118086: /* Intel PIIX4 */ 178 case 0x84CA8086: /* Intel PIIX4 */ 179 case 0x71998086: /* Intel PIIX4e */ 180 case 0x24218086: /* Intel ICH0 */ 181 if (udmamode >= 2) { 182 int32_t mask48, new48; 183 184 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 185 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 186 if (bootverbose) 187 ata_printf(scp, device, "%s setting UDMA2 on Intel chip\n", 188 (error) ? "failed" : "success"); 189 if (!error) { 190 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 191 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 192 pci_write_config(parent, 0x48, 193 (pci_read_config(parent, 0x48, 4) & 194 ~mask48) | new48, 4); 195 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 196 return; 197 } 198 } 199 /* make sure eventual ATA33 mode from the BIOS is disabled */ 200 pci_write_config(parent, 0x48, 201 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 202 /* FALLTHROUGH */ 203 204 case 0x70108086: /* Intel PIIX3 */ 205 if (wdmamode >= 2 && apiomode >= 4) { 206 int32_t mask40, new40, mask44, new44; 207 208 /* if SITRE not set doit for both channels */ 209 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 210 new40 = pci_read_config(parent, 0x40, 4); 211 new44 = pci_read_config(parent, 0x44, 4); 212 if (!(new40 & 0x00004000)) { 213 new44 &= ~0x0000000f; 214 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 215 } 216 if (!(new40 & 0x40000000)) { 217 new44 &= ~0x000000f0; 218 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 219 } 220 new40 |= 0x40004000; 221 pci_write_config(parent, 0x40, new40, 4); 222 pci_write_config(parent, 0x44, new44, 4); 223 } 224 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 225 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 226 if (bootverbose) 227 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n", 228 (error) ? "failed" : "success"); 229 if (!error) { 230 if (device == ATA_MASTER) { 231 mask40 = 0x0000330f; 232 new40 = 0x00002307; 233 mask44 = 0; 234 new44 = 0; 235 } 236 else { 237 mask40 = 0x000000f0; 238 new40 = 0x00000070; 239 mask44 = 0x0000000f; 240 new44 = 0x0000000b; 241 } 242 if (scp->channel) { 243 mask40 <<= 16; 244 new40 <<= 16; 245 mask44 <<= 4; 246 new44 <<= 4; 247 } 248 pci_write_config(parent, 0x40, 249 (pci_read_config(parent, 0x40, 4) & ~mask40)| 250 new40, 4); 251 pci_write_config(parent, 0x44, 252 (pci_read_config(parent, 0x44, 4) & ~mask44)| 253 new44, 4); 254 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 255 return; 256 } 257 } 258 /* we could set PIO mode timings, but we assume the BIOS did that */ 259 break; 260 261 case 0x12308086: /* Intel PIIX */ 262 if (wdmamode >= 2 && apiomode >= 4) { 263 int32_t word40; 264 265 word40 = pci_read_config(parent, 0x40, 4); 266 word40 >>= scp->channel * 16; 267 268 /* Check for timing config usable for DMA on controller */ 269 if (!((word40 & 0x3300) == 0x2300 && 270 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 271 break; 272 273 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 274 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 275 if (bootverbose) 276 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n", 277 (error) ? "failed" : "success"); 278 if (!error) { 279 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 280 return; 281 } 282 } 283 break; 284 285 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 286 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 287 if (pci_get_revid(parent) < 0xc2 && 288 scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 289 ata_printf(scp, device, 290 "Aladdin: two atapi devices on this channel, no DMA\n"); 291 break; 292 } 293 if (udmamode >= 5 && pci_get_revid(parent) >= 0xc4) { 294 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 295 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 296 if (bootverbose) 297 ata_printf(scp, device, "%s setting UDMA5 on Acer chip\n", 298 (error) ? "failed" : "success"); 299 if (!error) { 300 int32_t word54 = pci_read_config(parent, 0x54, 4); 301 302 pci_write_config(parent, 0x4b, 303 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 304 word54 &= ~(0x000f000f << (devno << 2)); 305 word54 |= (0x000f0005 << (devno << 2)); 306 pci_write_config(parent, 0x54, word54, 4); 307 pci_write_config(parent, 0x53, 308 pci_read_config(parent, 0x53, 1) | 0x03, 1); 309 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 310 return; 311 } 312 } 313 if (udmamode >= 4 && pci_get_revid(parent) >= 0xc2) { 314 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 315 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 316 if (bootverbose) 317 ata_printf(scp, device, "%s setting UDMA4 on Acer chip\n", 318 (error) ? "failed" : "success"); 319 if (!error) { 320 int32_t word54 = pci_read_config(parent, 0x54, 4); 321 322 pci_write_config(parent, 0x4b, 323 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 324 word54 &= ~(0x000f000f << (devno << 2)); 325 word54 |= (0x00080005 << (devno << 2)); 326 pci_write_config(parent, 0x54, word54, 4); 327 pci_write_config(parent, 0x53, 328 pci_read_config(parent, 0x53, 1) | 0x03, 1); 329 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 330 return; 331 } 332 } 333 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 334 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 335 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 336 if (bootverbose) 337 ata_printf(scp, device, "%s setting UDMA2 on Acer chip\n", 338 (error) ? "failed" : "success"); 339 if (!error) { 340 int32_t word54 = pci_read_config(parent, 0x54, 4); 341 342 word54 &= ~(0x000f000f << (devno << 2)); 343 word54 |= (0x000a0005 << (devno << 2)); 344 pci_write_config(parent, 0x54, word54, 4); 345 pci_write_config(parent, 0x53, 346 pci_read_config(parent, 0x53, 1) | 0x03, 1); 347 scp->flags |= ATA_ATAPI_DMA_RO; 348 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 349 return; 350 } 351 } 352 353 /* make sure eventual UDMA mode from the BIOS is disabled */ 354 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 355 ~(0x0008 << (devno << 2)), 2); 356 357 if (wdmamode >= 2 && apiomode >= 4) { 358 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 359 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 360 if (bootverbose) 361 ata_printf(scp, device, "%s setting WDMA2 on Acer chip\n", 362 (error) ? "failed" : "success"); 363 if (!error) { 364 pci_write_config(parent, 0x53, 365 pci_read_config(parent, 0x53, 1) | 0x03, 1); 366 scp->flags |= ATA_ATAPI_DMA_RO; 367 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 368 return; 369 } 370 } 371 pci_write_config(parent, 0x53, 372 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 373 /* we could set PIO mode timings, but we assume the BIOS did that */ 374 break; 375 376 case 0x74111022: /* AMD 766 */ 377 if (udmamode >= 5) { 378 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 379 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 380 if (bootverbose) 381 ata_printf(scp, device, "%s setting UDMA5 on AMD chip\n", 382 (error) ? "failed" : "success"); 383 if (!error) { 384 pci_write_config(parent, 0x53 - devno, 0xc6, 1); 385 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 386 return; 387 } 388 } 389 /* FALLTHROUGH */ 390 391 case 0x74091022: /* AMD 756 */ 392 if (udmamode >= 4) { 393 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 394 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 395 if (bootverbose) 396 ata_printf(scp, device, "%s setting UDMA4 on AMD chip\n", 397 (error) ? "failed" : "success"); 398 if (!error) { 399 pci_write_config(parent, 0x53 - devno, 0xc5, 1); 400 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 401 return; 402 } 403 } 404 goto via_82c586; 405 406 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 , 8231, 8233 */ 407 { 408 int via_modes[4][7] = { 409 { 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* ATA33 */ 410 { 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 }, /* ATA66 */ 411 { 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 }, /* ATA100 */ 412 { 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 }}; /* ATA133 */ 413 int *reg_val = NULL; 414 415 if (ata_find_dev(parent, 0x31471106, 0x40)) { /* 8233a */ 416 udmamode = imin(udmamode, 6); 417 reg_val = via_modes[3]; 418 } 419 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */ 420 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */ 421 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */ 422 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */ 423 udmamode = imin(udmamode, 5); 424 reg_val = via_modes[2]; 425 } 426 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */ 427 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 428 udmamode = imin(udmamode, 4); 429 reg_val = via_modes[1]; 430 } 431 else if (ata_find_dev(parent, 0x06861106, 0x0)) { /* 82C686 */ 432 udmamode = imin(udmamode, 2); 433 reg_val = via_modes[1]; 434 } 435 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 436 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 437 via_82c586: 438 udmamode = imin(udmamode, 2); 439 reg_val = via_modes[0]; 440 } 441 else 442 udmamode = 0; 443 444 if (udmamode >= 6) { 445 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 446 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 447 if (bootverbose) 448 ata_printf(scp, device, "%s setting UDMA6 on VIA chip\n", 449 (error) ? "failed" : "success"); 450 if (!error) { 451 pci_write_config(parent, 0x53 - devno, reg_val[6], 1); 452 scp->mode[ATA_DEV(device)] = ATA_UDMA6; 453 return; 454 } 455 } 456 if (udmamode >= 5) { 457 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 458 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 459 if (bootverbose) 460 ata_printf(scp, device, "%s setting UDMA5 on VIA chip\n", 461 (error) ? "failed" : "success"); 462 if (!error) { 463 pci_write_config(parent, 0x53 - devno, reg_val[5], 1); 464 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 465 return; 466 } 467 } 468 if (udmamode >= 4) { 469 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 470 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 471 if (bootverbose) 472 ata_printf(scp, device, "%s setting UDMA4 on VIA chip\n", 473 (error) ? "failed" : "success"); 474 if (!error) { 475 pci_write_config(parent, 0x53 - devno, reg_val[4], 1); 476 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 477 return; 478 } 479 } 480 if (udmamode >= 2) { 481 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 482 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 483 if (bootverbose) 484 ata_printf(scp, device, "%s setting UDMA2 on VIA chip\n", 485 (error) ? "failed" : "success"); 486 if (!error) { 487 pci_write_config(parent, 0x53 - devno, reg_val[2], 1); 488 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 489 return; 490 } 491 } 492 493 } 494 if (wdmamode >= 2 && apiomode >= 4) { 495 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 496 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 497 if (bootverbose) 498 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 499 (error) ? "failed" : "success", 500 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 501 if (!error) { 502 pci_write_config(parent, 0x53 - devno, 0x0b, 1); 503 pci_write_config(parent, 0x4b - devno, 0x31, 1); 504 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 505 return; 506 } 507 } 508 /* we could set PIO mode timings, but we assume the BIOS did that */ 509 break; 510 511 case 0x55131039: /* SiS 5591 */ 512 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */ 513 ata_find_dev(parent, 0x06331039, 0x00) || /* SiS 633 */ 514 ata_find_dev(parent, 0x06351039, 0x00) || /* SiS 635 */ 515 ata_find_dev(parent, 0x06401039, 0x00) || /* SiS 640 */ 516 ata_find_dev(parent, 0x06451039, 0x00) || /* SiS 645 */ 517 ata_find_dev(parent, 0x06501039, 0x00) || /* SiS 650 */ 518 ata_find_dev(parent, 0x07301039, 0x00) || /* SiS 730 */ 519 ata_find_dev(parent, 0x07331039, 0x00) || /* SiS 733 */ 520 ata_find_dev(parent, 0x07351039, 0x00) || /* SiS 735 */ 521 ata_find_dev(parent, 0x07401039, 0x00) || /* SiS 740 */ 522 ata_find_dev(parent, 0x07451039, 0x00) || /* SiS 745 */ 523 ata_find_dev(parent, 0x07501039, 0x00)) { /* SiS 750 */ 524 int8_t reg = 0x40 + (devno << 1); 525 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 526 527 if (udmamode >= 5) { 528 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 529 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 530 if (bootverbose) 531 ata_printf(scp, device, "%s setting UDMA5 on SiS chip\n", 532 (error) ? "failed" : "success"); 533 if (!error) { 534 pci_write_config(parent, reg, val | 0x8000, 2); 535 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 536 return; 537 } 538 } 539 if (udmamode >= 4) { 540 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 541 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 542 if (bootverbose) 543 ata_printf(scp, device, "%s setting UDMA4 on SiS chip\n", 544 (error) ? "failed" : "success"); 545 if (!error) { 546 pci_write_config(parent, reg, val | 0x9000, 2); 547 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 548 return; 549 } 550 } 551 if (udmamode >= 2) { 552 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 553 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 554 if (bootverbose) 555 ata_printf(scp, device, "%s setting UDMA2 on SiS chip\n", 556 (error) ? "failed" : "success"); 557 if (!error) { 558 pci_write_config(parent, reg, val | 0xb000, 2); 559 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 560 return; 561 } 562 } 563 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */ 564 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */ 565 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */ 566 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */ 567 int8_t reg = 0x40 + (devno << 1); 568 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 569 570 if (udmamode >= 4) { 571 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 572 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 573 if (bootverbose) 574 ata_printf(scp, device, "%s setting UDMA4 on SiS chip\n", 575 (error) ? "failed" : "success"); 576 if (!error) { 577 pci_write_config(parent, reg, val | 0x9000, 2); 578 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 579 return; 580 } 581 } 582 if (udmamode >= 2) { 583 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 584 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 585 if (bootverbose) 586 ata_printf(scp, device, "%s setting UDMA2 on SiS chip\n", 587 (error) ? "failed" : "success"); 588 if (!error) { 589 pci_write_config(parent, reg, val | 0xa000, 2); 590 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 591 return; 592 } 593 } 594 } else if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 595 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 596 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 597 if (bootverbose) 598 ata_printf(scp, device, "%s setting UDMA2 on SiS chip\n", 599 (error) ? "failed" : "success"); 600 if (!error) { 601 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 602 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 603 return; 604 } 605 } 606 if (wdmamode >=2 && apiomode >= 4) { 607 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 608 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 609 if (bootverbose) 610 ata_printf(scp, device, "%s setting WDMA2 on SiS chip\n", 611 (error) ? "failed" : "success"); 612 if (!error) { 613 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 614 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 615 return; 616 } 617 } 618 /* we could set PIO mode timings, but we assume the BIOS did that */ 619 break; 620 621 case 0x06491095: /* CMD 649 ATA100 controller */ 622 if (udmamode >= 5) { 623 u_int8_t umode; 624 625 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 626 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 627 if (bootverbose) 628 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 629 (error) ? "failed" : "success"); 630 if (!error) { 631 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 632 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 633 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 634 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 635 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 636 return; 637 } 638 } 639 /* FALLTHROUGH */ 640 641 case 0x06481095: /* CMD 648 ATA66 controller */ 642 if (udmamode >= 4) { 643 u_int8_t umode; 644 645 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 646 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 647 if (bootverbose) 648 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 649 (error) ? "failed" : "success"); 650 if (!error) { 651 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 652 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 653 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 654 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 655 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 656 return; 657 } 658 } 659 if (udmamode >= 2) { 660 u_int8_t umode; 661 662 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 663 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 664 if (bootverbose) 665 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 666 (error) ? "failed" : "success"); 667 if (!error) { 668 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 669 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 670 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 671 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 672 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 673 return; 674 } 675 } 676 /* make sure eventual UDMA mode from the BIOS is disabled */ 677 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 678 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 679 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 680 /* FALLTHROUGH */ 681 682 case 0x06461095: /* CMD 646 ATA controller */ 683 if (wdmamode >= 2 && apiomode >= 4) { 684 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 685 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 686 if (bootverbose) 687 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 688 error ? "failed" : "success"); 689 if (!error) { 690 int32_t offset = (devno < 3) ? (devno << 1) : 7; 691 692 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 693 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 694 return; 695 } 696 } 697 /* we could set PIO mode timings, but we assume the BIOS did that */ 698 break; 699 700 case 0xc6931080: /* Cypress 82c693 ATA controller */ 701 if (wdmamode >= 2 && apiomode >= 4) { 702 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 703 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 704 if (bootverbose) 705 ata_printf(scp, device, "%s setting WDMA2 on Cypress chip\n", 706 error ? "failed" : "success"); 707 if (!error) { 708 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 709 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 710 return; 711 } 712 } 713 /* we could set PIO mode timings, but we assume the BIOS did that */ 714 break; 715 716 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 717 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 718 if (udmamode >= 2) { 719 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 720 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 721 if (bootverbose) 722 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 723 (error) ? "failed" : "success"); 724 if (!error) { 725 cyrix_timing(scp, devno, ATA_UDMA2); 726 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 727 return; 728 } 729 } 730 if (wdmamode >= 2 && apiomode >= 4) { 731 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 732 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 733 if (bootverbose) 734 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 735 (error) ? "failed" : "success"); 736 if (!error) { 737 cyrix_timing(scp, devno, ATA_WDMA2); 738 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 739 return; 740 } 741 } 742 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 743 ATA_PIO0 + apiomode, ATA_C_F_SETXFER, 744 ATA_WAIT_READY); 745 if (bootverbose) 746 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 747 (error) ? "failed" : "success", 748 ata_mode2str(ATA_PIO0 + apiomode)); 749 cyrix_timing(scp, devno, ATA_PIO0 + apiomode); 750 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 751 return; 752 753 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 754 if (udmamode >= 2) { 755 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 756 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 757 if (bootverbose) 758 ata_printf(scp, device, 759 "%s setting UDMA2 on ServerWorks chip\n", 760 (error) ? "failed" : "success"); 761 if (!error) { 762 u_int16_t reg56; 763 764 pci_write_config(parent, 0x54, 765 pci_read_config(parent, 0x54, 1) | 766 (0x01 << devno), 1); 767 reg56 = pci_read_config(parent, 0x56, 2); 768 reg56 &= ~(0xf << (devno * 4)); 769 reg56 |= (0x2 << (devno * 4)); 770 pci_write_config(parent, 0x56, reg56, 2); 771 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 772 return; 773 } 774 } 775 if (wdmamode >= 2 && apiomode >= 4) { 776 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 777 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 778 if (bootverbose) 779 ata_printf(scp, device, 780 "%s setting WDMA2 on ServerWorks chip\n", 781 (error) ? "failed" : "success"); 782 if (!error) { 783 int offset = (scp->channel * 2) + (device == ATA_MASTER); 784 int word44 = pci_read_config(parent, 0x44, 4); 785 786 pci_write_config(parent, 0x54, 787 pci_read_config(parent, 0x54, 1) & 788 ~(0x01 << devno), 1); 789 word44 &= ~(0xff << (offset << 8)); 790 word44 |= (0x20 << (offset << 8)); 791 pci_write_config(parent, 0x44, 0x20, 4); 792 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 793 return; 794 } 795 } 796 /* we could set PIO mode timings, but we assume the BIOS did that */ 797 break; 798 799 case 0x4d69105a: /* Promise TX2 ATA133 controllers */ 800 ATA_OUTB(scp->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 801 if (udmamode >= 6 && !(ATA_INB(scp->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 802 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 803 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 804 if (bootverbose) 805 ata_printf(scp, device, "%s setting UDMA6 on Promise chip\n", 806 (error) ? "failed" : "success"); 807 if (!error) { 808 scp->mode[ATA_DEV(device)] = ATA_UDMA6; 809 return; 810 } 811 } 812 /* FALLTHROUGH */ 813 814 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 815 case 0x6268105a: /* Promise TX2 ATA100 controllers */ 816 ATA_OUTB(scp->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 817 if (udmamode >= 5 && !(ATA_INB(scp->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 818 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 819 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 820 if (bootverbose) 821 ata_printf(scp, device, "%s setting UDMA5 on Promise chip\n", 822 (error) ? "failed" : "success"); 823 if (!error) { 824 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 825 return; 826 } 827 } 828 ATA_OUTB(scp->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 829 if (udmamode >= 4 && !(ATA_INB(scp->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 830 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 831 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 832 if (bootverbose) 833 ata_printf(scp, device, "%s setting UDMA4 on Promise chip\n", 834 (error) ? "failed" : "success"); 835 if (!error) { 836 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 837 return; 838 } 839 } 840 if (udmamode >= 2) { 841 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 842 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 843 if (bootverbose) 844 ata_printf(scp, device, "%s setting %s on Promise chip\n", 845 (error) ? "failed" : "success", "UDMA2"); 846 if (!error) { 847 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 848 return; 849 } 850 } 851 if (wdmamode >= 2 && apiomode >= 4) { 852 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 853 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 854 if (bootverbose) 855 ata_printf(scp, device, "%s setting %s on Promise chip\n", 856 (error) ? "failed" : "success", "WDMA2"); 857 if (!error) { 858 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 859 return; 860 } 861 } 862 break; 863 864 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 865 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 866 if (!ATAPI_DEVICE(scp, device) && udmamode >= 5 && 867 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 868 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 869 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 870 if (bootverbose) 871 ata_printf(scp, device, "%s setting UDMA5 on Promise chip\n", 872 (error) ? "failed" : "success"); 873 if (!error) { 874 promise_timing(scp, devno, ATA_UDMA5); 875 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 876 return; 877 } 878 } 879 /* FALLTHROUGH */ 880 881 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 882 if (!ATAPI_DEVICE(scp, device) && udmamode >= 4 && 883 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 884 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 885 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 886 if (bootverbose) 887 ata_printf(scp, device, "%s setting UDMA4 on Promise chip\n", 888 (error) ? "failed" : "success"); 889 if (!error) { 890 promise_timing(scp, devno, ATA_UDMA4); 891 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 892 return; 893 } 894 } 895 /* FALLTHROUGH */ 896 897 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 898 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) { 899 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 900 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 901 if (bootverbose) 902 ata_printf(scp, device, "%s setting UDMA2 on Promise chip\n", 903 (error) ? "failed" : "success"); 904 if (!error) { 905 promise_timing(scp, devno, ATA_UDMA2); 906 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 907 return; 908 } 909 } 910 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) { 911 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 912 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 913 if (bootverbose) 914 ata_printf(scp, device, "%s setting WDMA2 on Promise chip\n", 915 (error) ? "failed" : "success"); 916 if (!error) { 917 promise_timing(scp, devno, ATA_WDMA2); 918 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 919 return; 920 } 921 } 922 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 923 ATA_PIO0 + apiomode, 924 ATA_C_F_SETXFER, ATA_WAIT_READY); 925 if (bootverbose) 926 ata_printf(scp, device, "%s setting PIO%d on Promise chip\n", 927 (error) ? "failed" : "success", 928 (apiomode >= 0) ? apiomode : 0); 929 promise_timing(scp, devno, ATA_PIO0 + apiomode); 930 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 931 return; 932 933 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */ 934 if (!ATAPI_DEVICE(scp, device) && 935 udmamode >= 6 && pci_get_revid(parent) >= 0x05 && 936 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 937 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 938 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 939 if (bootverbose) 940 ata_printf(scp, device, "%s setting UDMA6 on HighPoint chip\n", 941 (error) ? "failed" : "success"); 942 if (!error) { 943 hpt_timing(scp, devno, ATA_UDMA6); 944 scp->mode[ATA_DEV(device)] = ATA_UDMA6; 945 return; 946 } 947 } 948 if (!ATAPI_DEVICE(scp, device) && 949 udmamode >= 5 && pci_get_revid(parent) >= 0x03 && 950 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 951 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 952 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 953 if (bootverbose) 954 ata_printf(scp, device, "%s setting UDMA5 on HighPoint chip\n", 955 (error) ? "failed" : "success"); 956 if (!error) { 957 hpt_timing(scp, devno, ATA_UDMA5); 958 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 959 return; 960 } 961 } 962 if (!ATAPI_DEVICE(scp, device) && udmamode >= 4 && 963 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 964 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 965 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 966 if (bootverbose) 967 ata_printf(scp, device, "%s setting UDMA4 on HighPoint chip\n", 968 (error) ? "failed" : "success"); 969 if (!error) { 970 hpt_timing(scp, devno, ATA_UDMA4); 971 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 972 return; 973 } 974 } 975 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) { 976 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 977 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 978 if (bootverbose) 979 ata_printf(scp, device, "%s setting UDMA2 on HighPoint chip\n", 980 (error) ? "failed" : "success"); 981 if (!error) { 982 hpt_timing(scp, devno, ATA_UDMA2); 983 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 984 return; 985 } 986 } 987 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) { 988 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 989 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 990 if (bootverbose) 991 ata_printf(scp, device, "%s setting WDMA2 on HighPoint chip\n", 992 (error) ? "failed" : "success"); 993 if (!error) { 994 hpt_timing(scp, devno, ATA_WDMA2); 995 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 996 return; 997 } 998 } 999 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 1000 ATA_PIO0 + apiomode, 1001 ATA_C_F_SETXFER, ATA_WAIT_READY); 1002 if (bootverbose) 1003 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 1004 (error) ? "failed" : "success", 1005 (apiomode >= 0) ? apiomode : 0); 1006 hpt_timing(scp, devno, ATA_PIO0 + apiomode); 1007 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 1008 return; 1009 1010 default: /* unknown controller chip */ 1011 /* better not try generic DMA on ATAPI devices it almost never works */ 1012 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 1013 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 1014 break; 1015 1016 /* if controller says its setup for DMA take the easy way out */ 1017 /* the downside is we dont know what DMA mode we are in */ 1018 if ((udmamode >= 0 || wdmamode > 1) && 1019 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 1020 ((device==ATA_MASTER) ? 1021 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 1022 scp->mode[ATA_DEV(device)] = ATA_DMA; 1023 return; 1024 } 1025 1026 /* well, we have no support for this, but try anyways */ 1027 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) { 1028 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 1029 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1030 if (bootverbose) 1031 ata_printf(scp, device, "%s setting WDMA2 on generic chip\n", 1032 (error) ? "failed" : "success"); 1033 if (!error) { 1034 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 1035 return; 1036 } 1037 } 1038 } 1039 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode, 1040 ATA_C_F_SETXFER,ATA_WAIT_READY); 1041 if (bootverbose) 1042 ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 1043 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 1044 if (!error) 1045 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 1046 else { 1047 if (bootverbose) 1048 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 1049 scp->mode[ATA_DEV(device)] = ATA_PIO; 1050 } 1051 } 1052 1053 int 1054 ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 1055 caddr_t data, int32_t count) 1056 { 1057 u_int32_t dma_count, dma_base; 1058 int i = 0; 1059 1060 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 1061 ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 1062 return -1; 1063 } 1064 1065 if (!count) { 1066 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 1067 return -1; 1068 } 1069 1070 dma_base = vtophys(data); 1071 dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 1072 data += dma_count; 1073 count -= dma_count; 1074 1075 while (count) { 1076 dmatab[i].base = dma_base; 1077 dmatab[i].count = (dma_count & 0xffff); 1078 i++; 1079 if (i >= ATA_DMA_ENTRIES) { 1080 ata_printf(scp, device, "too many segments in DMA table\n"); 1081 return -1; 1082 } 1083 dma_base = vtophys(data); 1084 dma_count = imin(count, PAGE_SIZE); 1085 data += imin(count, PAGE_SIZE); 1086 count -= imin(count, PAGE_SIZE); 1087 } 1088 dmatab[i].base = dma_base; 1089 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 1090 return 0; 1091 } 1092 1093 void 1094 ata_dmastart(struct ata_softc *scp, int device, 1095 struct ata_dmaentry *dmatab, int dir) 1096 { 1097 scp->flags |= ATA_DMA_ACTIVE; 1098 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab)); 1099 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 1100 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 1101 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) | 1102 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 1103 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 1104 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 1105 } 1106 1107 int 1108 ata_dmadone(struct ata_softc *scp) 1109 { 1110 int error; 1111 1112 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 1113 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 1114 scp->flags &= ~ATA_DMA_ACTIVE; 1115 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT); 1116 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 1117 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 1118 return error & ATA_BMSTAT_MASK; 1119 } 1120 1121 int 1122 ata_dmastatus(struct ata_softc *scp) 1123 { 1124 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 1125 } 1126 1127 static void 1128 cyrix_timing(struct ata_softc *scp, int devno, int mode) 1129 { 1130 u_int32_t reg20 = 0x0000e132; 1131 u_int32_t reg24 = 0x00017771; 1132 1133 switch (mode) { 1134 case ATA_PIO0: reg20 = 0x0000e132; break; 1135 case ATA_PIO1: reg20 = 0x00018121; break; 1136 case ATA_PIO2: reg20 = 0x00024020; break; 1137 case ATA_PIO3: reg20 = 0x00032010; break; 1138 case ATA_PIO4: reg20 = 0x00040010; break; 1139 case ATA_WDMA2: reg24 = 0x00002020; break; 1140 case ATA_UDMA2: reg24 = 0x00911030; break; 1141 } 1142 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20); 1143 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24); 1144 } 1145 1146 static void 1147 promise_timing(struct ata_softc *scp, int devno, int mode) 1148 { 1149 u_int32_t timing = 0; 1150 struct promise_timing { 1151 u_int8_t pa:4; 1152 u_int8_t prefetch:1; 1153 u_int8_t iordy:1; 1154 u_int8_t errdy:1; 1155 u_int8_t syncin:1; 1156 u_int8_t pb:5; 1157 u_int8_t mb:3; 1158 u_int8_t mc:4; 1159 u_int8_t dmaw:1; 1160 u_int8_t dmar:1; 1161 u_int8_t iordyp:1; 1162 u_int8_t dmarqp:1; 1163 u_int8_t reserved:8; 1164 } *t = (struct promise_timing*)&timing; 1165 1166 t->iordy = 1; t->iordyp = 1; 1167 if (mode >= ATA_DMA) { 1168 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1169 } 1170 1171 switch (scp->chiptype) { 1172 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1173 switch (mode) { 1174 default: 1175 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1176 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1177 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1178 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1179 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1180 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1181 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1182 } 1183 break; 1184 1185 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1186 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1187 case 0x0d30105a: /* Promise OEM ATA 100 */ 1188 switch (mode) { 1189 default: 1190 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1191 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1192 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1193 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1194 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1195 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1196 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1197 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1198 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1199 } 1200 break; 1201 } 1202 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 1203 } 1204 1205 static void 1206 hpt_timing(struct ata_softc *scp, int devno, int mode) 1207 { 1208 device_t parent = device_get_parent(scp->dev); 1209 u_int32_t timing; 1210 if (pci_get_revid(parent) >= 0x05) { /* HPT372 */ 1211 switch (mode) { 1212 case ATA_PIO0: timing = 0x0d029d5e; break; 1213 case ATA_PIO1: timing = 0x0d029d26; break; 1214 case ATA_PIO2: timing = 0x0c829ca6; break; 1215 case ATA_PIO3: timing = 0x0c829c84; break; 1216 case ATA_PIO4: timing = 0x0c829c62; break; 1217 case ATA_WDMA2: timing = 0x2c829262; break; 1218 case ATA_UDMA2: timing = 0x1c91dc62; break; 1219 case ATA_UDMA4: timing = 0x1c8ddc62; break; 1220 case ATA_UDMA5: timing = 0x1c6ddc62; break; 1221 case ATA_UDMA6: timing = 0x1c81dc62; break; 1222 default: timing = 0x0d029d5e; 1223 } 1224 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1225 pci_write_config(parent, 0x5b, 0x20, 1); 1226 } 1227 else if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 1228 switch (mode) { 1229 case ATA_PIO0: timing = 0x06914e57; break; 1230 case ATA_PIO1: timing = 0x06914e43; break; 1231 case ATA_PIO2: timing = 0x06514e33; break; 1232 case ATA_PIO3: timing = 0x06514e22; break; 1233 case ATA_PIO4: timing = 0x06514e21; break; 1234 case ATA_WDMA2: timing = 0x26514e21; break; 1235 case ATA_UDMA2: timing = 0x16494e31; break; 1236 case ATA_UDMA4: timing = 0x16454e31; break; 1237 case ATA_UDMA5: timing = 0x16454e31; break; 1238 default: timing = 0x06514e57; 1239 } 1240 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1241 pci_write_config(parent, 0x5b, 0x22, 1); 1242 } 1243 else { /* HPT36[68] */ 1244 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1245 case 0x85: /* 25Mhz */ 1246 switch (mode) { 1247 case ATA_PIO0: timing = 0xc0d08585; break; 1248 case ATA_PIO1: timing = 0xc0d08572; break; 1249 case ATA_PIO2: timing = 0xc0ca8542; break; 1250 case ATA_PIO3: timing = 0xc0ca8532; break; 1251 case ATA_PIO4: timing = 0xc0ca8521; break; 1252 case ATA_WDMA2: timing = 0xa0ca8521; break; 1253 case ATA_UDMA2: timing = 0x90cf8521; break; 1254 case ATA_UDMA4: timing = 0x90c98521; break; 1255 default: timing = 0x01208585; 1256 } 1257 break; 1258 default: 1259 case 0xa7: /* 33MHz */ 1260 switch (mode) { 1261 case ATA_PIO0: timing = 0xc0d0a7aa; break; 1262 case ATA_PIO1: timing = 0xc0d0a7a3; break; 1263 case ATA_PIO2: timing = 0xc0d0a753; break; 1264 case ATA_PIO3: timing = 0xc0c8a742; break; 1265 case ATA_PIO4: timing = 0xc0c8a731; break; 1266 case ATA_WDMA2: timing = 0xa0c8a731; break; 1267 case ATA_UDMA2: timing = 0x90caa731; break; 1268 case ATA_UDMA4: timing = 0x90c9a731; break; 1269 default: timing = 0x0120a7a7; 1270 } 1271 break; 1272 case 0xd9: /* 40Mhz */ 1273 switch (mode) { 1274 case ATA_PIO0: timing = 0xc018d9d9; break; 1275 case ATA_PIO1: timing = 0xc010d9c7; break; 1276 case ATA_PIO2: timing = 0xc010d997; break; 1277 case ATA_PIO3: timing = 0xc010d974; break; 1278 case ATA_PIO4: timing = 0xc008d963; break; 1279 case ATA_WDMA2: timing = 0xa008d943; break; 1280 case ATA_UDMA2: timing = 0x900bd943; break; 1281 case ATA_UDMA4: timing = 0x900fd943; break; 1282 default: timing = 0x0120d9d9; 1283 } 1284 } 1285 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 1286 } 1287 } 1288