1 /*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include "pci.h" 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bio.h> 35 #include <sys/malloc.h> 36 #include <sys/bus.h> 37 #include <sys/disk.h> 38 #include <sys/devicestat.h> 39 #include <vm/vm.h> 40 #include <vm/pmap.h> 41 #if NPCI > 0 42 #include <pci/pcivar.h> 43 #endif 44 #include <dev/ata/ata-all.h> 45 #include <dev/ata/ata-disk.h> 46 47 #if NPCI > 0 48 49 /* prototypes */ 50 static void promise_timing(struct ata_softc *, int32_t, int32_t); 51 static void hpt366_timing(struct ata_softc *, int32_t, int32_t); 52 53 /* misc defines */ 54 #ifdef __alpha__ 55 #undef vtophys 56 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 57 #endif 58 59 void 60 ata_dmainit(struct ata_softc *scp, int32_t device, 61 int32_t apiomode, int32_t wdmamode, int32_t udmamode) 62 { 63 device_t parent = device_get_parent(scp->dev); 64 int32_t devno = (scp->unit << 1) + ATA_DEV(device); 65 int32_t error; 66 67 /* set our most pessimistic default mode */ 68 scp->mode[ATA_DEV(device)] = ATA_PIO; 69 70 if (!scp->bmaddr) 71 return; 72 73 /* if simplex controller, only allow DMA on primary channel */ 74 if (scp->unit == 1) { 75 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 76 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 77 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 78 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 79 return; 80 } 81 } 82 83 if (!scp->dmatab[ATA_DEV(device)]) { 84 void *dmatab; 85 86 if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) 87 return; 88 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 89 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 90 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 91 free(dmatab, M_DEVBUF); 92 return; 93 } 94 scp->dmatab[ATA_DEV(device)] = dmatab; 95 } 96 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) { 97 ata_printf(scp, device, 98 "DMA limitted to UDMA33, non-ATA66 compliant cable\n"); 99 udmamode = 2; 100 } 101 102 switch (scp->chiptype) { 103 104 case 0x24118086: /* Intel ICH */ 105 if (udmamode >= 4) { 106 int32_t mask48, new48; 107 int16_t word54; 108 109 word54 = pci_read_config(parent, 0x54, 2); 110 if (word54 & (0x10 << devno)) { 111 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 112 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 113 if (bootverbose) 114 ata_printf(scp, device, 115 "%s setting up UDMA4 mode on ICH chip\n", 116 (error) ? "failed" : "success"); 117 if (!error) { 118 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 119 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 120 pci_write_config(parent, 0x48, 121 (pci_read_config(parent, 0x48, 4) & 122 ~mask48) | new48, 4); 123 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 124 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 125 return; 126 } 127 } 128 } 129 /* FALLTHROUGH */ 130 131 case 0x71118086: /* Intel PIIX4 */ 132 case 0x71998086: /* Intel PIIX4e */ 133 case 0x24218086: /* Intel ICH0 */ 134 if (udmamode >= 2) { 135 int32_t mask48, new48; 136 137 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 138 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 139 if (bootverbose) 140 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 141 (error) ? "failed" : "success", 142 (scp->chiptype == 0x24118086) ? "ICH" : 143 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 144 if (!error) { 145 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 146 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 147 pci_write_config(parent, 0x48, 148 (pci_read_config(parent, 0x48, 4) & 149 ~mask48) | new48, 4); 150 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 151 return; 152 } 153 } 154 /* FALLTHROUGH */ 155 156 case 0x70108086: /* Intel PIIX3 */ 157 if (wdmamode >= 2 && apiomode >= 4) { 158 int32_t mask40, new40, mask44, new44; 159 160 /* if SITRE not set doit for both channels */ 161 if (!((pci_read_config(parent, 0x40, 4)>>(scp->unit<<8))&0x4000)){ 162 new40 = pci_read_config(parent, 0x40, 4); 163 new44 = pci_read_config(parent, 0x44, 4); 164 if (!(new40 & 0x00004000)) { 165 new44 &= ~0x0000000f; 166 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 167 } 168 if (!(new40 & 0x40000000)) { 169 new44 &= ~0x000000f0; 170 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 171 } 172 new40 |= 0x40004000; 173 pci_write_config(parent, 0x40, new40, 4); 174 pci_write_config(parent, 0x44, new44, 4); 175 } 176 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 177 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 178 if (bootverbose) 179 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 180 (error) ? "failed" : "success", 181 (scp->chiptype == 0x70108086) ? "PIIX3" : 182 (scp->chiptype == 0x24118086) ? "ICH" : 183 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 184 if (!error) { 185 if (device == ATA_MASTER) { 186 mask40 = 0x0000330f; 187 new40 = 0x00002307; 188 mask44 = 0; 189 new44 = 0; 190 } 191 else { 192 mask40 = 0x000000f0; 193 new40 = 0x00000070; 194 mask44 = 0x0000000f; 195 new44 = 0x0000000b; 196 } 197 if (scp->unit) { 198 mask40 <<= 16; 199 new40 <<= 16; 200 mask44 <<= 4; 201 new44 <<= 4; 202 } 203 pci_write_config(parent, 0x40, 204 (pci_read_config(parent, 0x40, 4) & ~mask40)| 205 new40, 4); 206 pci_write_config(parent, 0x44, 207 (pci_read_config(parent, 0x44, 4) & ~mask44)| 208 new44, 4); 209 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 210 return; 211 } 212 } 213 /* we could set PIO mode timings, but we assume the BIOS did that */ 214 break; 215 216 case 0x12308086: /* Intel PIIX */ 217 if (wdmamode >= 2 && apiomode >= 4) { 218 int32_t word40; 219 220 word40 = pci_read_config(parent, 0x40, 4); 221 word40 >>= scp->unit * 16; 222 223 /* Check for timing config usable for DMA on controller */ 224 if (!((word40 & 0x3300) == 0x2300 && 225 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 226 break; 227 228 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 229 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 230 if (bootverbose) 231 ata_printf(scp, device, 232 "%s setting up WDMA2 mode on PIIX chip\n", 233 (error) ? "failed" : "success"); 234 if (!error) { 235 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 236 return; 237 } 238 } 239 break; 240 241 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 242 /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 243 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 244 ata_printf(scp, device, 245 "Aladdin: two atapi devices on this channel, no DMA\n"); 246 break; 247 } 248 if (udmamode >= 2) { 249 int32_t word54 = pci_read_config(parent, 0x54, 4); 250 251 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 252 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 253 if (bootverbose) 254 ata_printf(scp, device, 255 "%s setting up UDMA2 mode on Aladdin chip\n", 256 (error) ? "failed" : "success"); 257 if (!error) { 258 word54 &= ~(0x000f000f << (devno << 2)); 259 word54 |= (0x000a0005 << (devno << 2)); 260 pci_write_config(parent, 0x54, word54, 4); 261 pci_write_config(parent, 0x53, 262 pci_read_config(parent, 0x53, 1) | 0x03, 1); 263 scp->flags |= ATA_ATAPI_DMA_RO; 264 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 265 return; 266 } 267 } 268 if (wdmamode >= 2 && apiomode >= 4) { 269 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 270 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 271 if (bootverbose) 272 ata_printf(scp, device, 273 "%s setting up WDMA2 mode on Aladdin chip\n", 274 (error) ? "failed" : "success"); 275 if (!error) { 276 pci_write_config(parent, 0x53, 277 pci_read_config(parent, 0x53, 1) | 0x03, 1); 278 scp->flags |= ATA_ATAPI_DMA_RO; 279 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 280 return; 281 } 282 } 283 pci_write_config(parent, 0x53, 284 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 285 /* we could set PIO mode timings, but we assume the BIOS did that */ 286 break; 287 288 case 0x74091022: /* AMD 756 */ 289 if (udmamode >= 4) { 290 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 291 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 292 if (bootverbose) 293 ata_printf(scp, device, 294 "%s setting up UDMA4 mode on AMD chip\n", 295 (error) ? "failed" : "success"); 296 if (!error) { 297 pci_write_config(parent, 0x53 - devno, 0xc3, 1); 298 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 299 return; 300 } 301 } 302 goto via_82c586; 303 304 case 0x06861106: /* VIA 82C686 */ 305 via_82c686: 306 if (udmamode >= 4) { 307 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 308 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 309 if (bootverbose) 310 ata_printf(scp, device, 311 "%s setting up UDMA4 mode on VIA chip\n", 312 (error) ? "failed" : "success"); 313 if (!error) { 314 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 315 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 316 return; 317 } 318 } 319 if (udmamode >= 2) { 320 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 321 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 322 if (bootverbose) 323 ata_printf(scp, device, 324 "%s setting up UDMA2 mode on VIA chip\n", 325 (error) ? "failed" : "success"); 326 if (!error) { 327 pci_write_config(parent, 0x53 - devno, 0xea, 1); 328 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 329 return; 330 } 331 } 332 goto via_generic; 333 334 case 0x05961106: /* VIA 82C596 */ 335 /* 82c596 revision >= 0x12 is like the 82c686 */ 336 if (ata_find_dev(parent, 0x05961106, 0x12)) 337 goto via_82c686; 338 /* FALLTHROUGH */ 339 340 case 0x05861106: /* VIA 82C586 */ 341 via_82c586: 342 /* UDMA2 mode only on 82C586 > rev1, 82C596, AMD 756 */ 343 if ((udmamode >= 2 && ata_find_dev(parent, 0x05861106, 0x02)) || 344 (udmamode >= 2 && scp->chiptype == 0x05961106) || 345 (udmamode >= 2 && scp->chiptype == 0x74091022)) { 346 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 347 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 348 if (bootverbose) 349 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 350 (error) ? "failed" : "success", 351 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 352 if (!error) { 353 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 354 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 355 return; 356 } 357 } 358 /* FALLTHROUGH */ 359 360 case 0x05711106: /* VIA 82C571 */ 361 via_generic: 362 if (wdmamode >= 2 && apiomode >= 4) { 363 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 364 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 365 if (bootverbose) 366 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 367 (error) ? "failed" : "success", 368 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 369 if (!error) { 370 pci_write_config(parent, 0x53 - devno, 0x82, 1); 371 pci_write_config(parent, 0x4b - devno, 0x31, 1); 372 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 373 return; 374 } 375 } 376 /* we could set PIO mode timings, but we assume the BIOS did that */ 377 break; 378 379 case 0x55131039: /* SiS 5591 */ 380 if (udmamode >= 2) { 381 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 382 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 383 if (bootverbose) 384 ata_printf(scp, device, 385 "%s setting up UDMA2 mode on SiS chip\n", 386 (error) ? "failed" : "success"); 387 if (!error) { 388 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 389 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 390 return; 391 } 392 } 393 if (wdmamode >=2 && apiomode >= 4) { 394 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 395 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 396 if (bootverbose) 397 ata_printf(scp, device, 398 "%s setting up WDMA2 mode on SiS chip\n", 399 (error) ? "failed" : "success"); 400 if (!error) { 401 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 402 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 403 return; 404 } 405 } 406 /* we could set PIO mode timings, but we assume the BIOS did that */ 407 break; 408 409 case 0x06461095: /* CMD 646 ATA controller */ 410 if (wdmamode >= 2 && apiomode >= 4) { 411 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 412 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 413 if (bootverbose) 414 ata_printf(scp, device, 415 "%s setting up WDMA2 mode on CMD646 chip\n", 416 error ? "failed" : "success"); 417 if (!error) { 418 int32_t offset = (devno < 3) ? (devno << 1) : 7; 419 420 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 421 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 422 return; 423 } 424 } 425 /* we could set PIO mode timings, but we assume the BIOS did that */ 426 break; 427 428 case 0xc6931080: /* Cypress 82c693 ATA controller */ 429 if (wdmamode >= 2 && apiomode >= 4) { 430 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 431 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 432 if (bootverbose) 433 ata_printf(scp, device, 434 "%s setting up WDMA2 mode on Cypress chip\n", 435 error ? "failed" : "success"); 436 if (!error) { 437 pci_write_config(scp->dev, scp->unit ? 0x4e : 0x4c, 0x2020, 2); 438 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 439 return; 440 } 441 } 442 /* we could set PIO mode timings, but we assume the BIOS did that */ 443 break; 444 445 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */ 446 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */ 447 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 448 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 449 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 450 break; 451 452 if (udmamode >=4 && scp->chiptype == 0x4d38105a && 453 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 454 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 455 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 456 if (bootverbose) 457 ata_printf(scp, device, 458 "%s setting up UDMA4 mode on Promise chip\n", 459 (error) ? "failed" : "success"); 460 if (!error) { 461 promise_timing(scp, devno, ATA_UDMA4); 462 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 463 return; 464 } 465 } 466 if (udmamode >= 2) { 467 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 468 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 469 if (bootverbose) 470 ata_printf(scp, device, 471 "%s setting up UDMA2 mode on Promise chip\n", 472 (error) ? "failed" : "success"); 473 if (!error) { 474 promise_timing(scp, devno, ATA_UDMA2); 475 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 476 return; 477 } 478 } 479 if (wdmamode >= 2 && apiomode >= 4) { 480 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 481 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 482 if (bootverbose) 483 ata_printf(scp, device, 484 "%s setting up WDMA2 mode on Promise chip\n", 485 (error) ? "failed" : "success"); 486 if (!error) { 487 promise_timing(scp, devno, ATA_WDMA2); 488 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 489 return; 490 } 491 } 492 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 493 ata_pio2mode(apiomode), 494 ATA_C_F_SETXFER, ATA_WAIT_READY); 495 if (bootverbose) 496 ata_printf(scp, device, 497 "%s setting up PIO%d mode on Promise chip\n", 498 (error) ? "failed" : "success", 499 (apiomode >= 0) ? apiomode : 0); 500 promise_timing(scp, devno, ata_pio2mode(apiomode)); 501 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 502 return; 503 504 case 0x00041103: /* HighPoint HPT366 controller */ 505 /* no ATAPI devices for now */ 506 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 507 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 508 break; 509 510 if (udmamode >=4 && !(pci_read_config(parent, 0x5a, 1) & 0x2)) { 511 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 512 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 513 if (bootverbose) 514 ata_printf(scp, device, 515 "%s setting up UDMA4 mode on HPT366 chip\n", 516 (error) ? "failed" : "success"); 517 if (!error) { 518 hpt366_timing(scp, devno, ATA_UDMA4); 519 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 520 return; 521 } 522 } 523 if (udmamode >= 2) { 524 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 525 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 526 if (bootverbose) 527 ata_printf(scp, device, 528 "%s setting up UDMA2 mode on HPT366 chip\n", 529 (error) ? "failed" : "success"); 530 if (!error) { 531 hpt366_timing(scp, devno, ATA_UDMA2); 532 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 533 return; 534 } 535 } 536 if (wdmamode >= 2 && apiomode >= 4) { 537 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 538 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 539 if (bootverbose) 540 ata_printf(scp, device, 541 "%s setting up WDMA2 mode on HPT366 chip\n", 542 (error) ? "failed" : "success"); 543 if (!error) { 544 hpt366_timing(scp, devno, ATA_WDMA2); 545 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 546 return; 547 } 548 } 549 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 550 ata_pio2mode(apiomode), 551 ATA_C_F_SETXFER, ATA_WAIT_READY); 552 if (bootverbose) 553 ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n", 554 (error) ? "failed" : "success", 555 (apiomode >= 0) ? apiomode : 0); 556 hpt366_timing(scp, devno, ata_pio2mode(apiomode)); 557 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 558 return; 559 560 default: /* unknown controller chip */ 561 /* better not try generic DMA on ATAPI devices it almost never works */ 562 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 563 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 564 break; 565 566 /* if controller says its setup for DMA take the easy way out */ 567 /* the downside is we dont know what DMA mode we are in */ 568 if ((udmamode >= 0 || wdmamode > 1) && 569 (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 570 ((device==ATA_MASTER) ? 571 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 572 scp->mode[ATA_DEV(device)] = ATA_DMA; 573 return; 574 } 575 576 /* well, we have no support for this, but try anyways */ 577 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) { 578 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 579 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 580 if (bootverbose) 581 ata_printf(scp, device, 582 "%s setting up WDMA2 mode on generic chip\n", 583 (error) ? "failed" : "success"); 584 if (!error) { 585 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 586 return; 587 } 588 } 589 } 590 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 591 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 592 if (bootverbose) 593 ata_printf(scp, device, "%s setting up PIO%d mode on generic chip\n", 594 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 595 if (!error) 596 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 597 else { 598 if (bootverbose) 599 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 600 scp->mode[ATA_DEV(device)] = ATA_PIO; 601 } 602 } 603 604 int32_t 605 ata_dmasetup(struct ata_softc *scp, int32_t device, 606 int8_t *data, int32_t count, int32_t flags) 607 { 608 struct ata_dmaentry *dmatab; 609 u_int32_t dma_count, dma_base; 610 int32_t i = 0; 611 612 if (((uintptr_t)data & 1) || (count & 1)) 613 return -1; 614 615 if (!count) { 616 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 617 return -1; 618 } 619 620 dmatab = scp->dmatab[ATA_DEV(device)]; 621 dma_base = vtophys(data); 622 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 623 data += dma_count; 624 count -= dma_count; 625 626 while (count) { 627 dmatab[i].base = dma_base; 628 dmatab[i].count = (dma_count & 0xffff); 629 i++; 630 if (i >= ATA_DMA_ENTRIES) { 631 ata_printf(scp, device, "too many segments in DMA table\n"); 632 return -1; 633 } 634 dma_base = vtophys(data); 635 dma_count = min(count, PAGE_SIZE); 636 data += min(count, PAGE_SIZE); 637 count -= min(count, PAGE_SIZE); 638 } 639 dmatab[i].base = dma_base; 640 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 641 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 642 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0); 643 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 644 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 645 return 0; 646 } 647 648 void 649 ata_dmastart(struct ata_softc *scp) 650 { 651 scp->flags |= ATA_DMA_ACTIVE; 652 outb(scp->bmaddr + ATA_BMCMD_PORT, 653 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 654 } 655 656 int32_t 657 ata_dmadone(struct ata_softc *scp) 658 { 659 outb(scp->bmaddr + ATA_BMCMD_PORT, 660 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 661 scp->flags &= ~ATA_DMA_ACTIVE; 662 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 663 } 664 665 int32_t 666 ata_dmastatus(struct ata_softc *scp) 667 { 668 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 669 } 670 671 static void 672 promise_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 673 { 674 u_int32_t timing = 0; 675 struct promise_timing { 676 u_int8_t pa:4; 677 u_int8_t prefetch:1; 678 u_int8_t iordy:1; 679 u_int8_t errdy:1; 680 u_int8_t syncin:1; 681 u_int8_t pb:5; 682 u_int8_t mb:3; 683 u_int8_t mc:4; 684 u_int8_t dmaw:1; 685 u_int8_t dmar:1; 686 u_int8_t iordyp:1; 687 u_int8_t dmarqp:1; 688 u_int8_t reserved:8; 689 } *t = (struct promise_timing*)&timing; 690 691 t->iordy = 1; t->iordyp = 1; 692 if (mode >= ATA_DMA) { 693 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 694 } 695 696 switch (scp->chiptype) { 697 case 0x4d33105a: /* Promise 33's */ 698 switch (mode) { 699 default: 700 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 701 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 702 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 703 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 704 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 705 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 706 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 707 } 708 break; 709 710 case 0x4d38105a: /* Promise 66's */ 711 switch (mode) { 712 default: 713 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 714 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 715 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 716 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 717 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 718 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 719 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 720 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 721 } 722 break; 723 } 724 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 725 } 726 727 static void 728 hpt366_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 729 { 730 device_t parent = device_get_parent(scp->dev); 731 u_int32_t timing; 732 733 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 734 case 0x85: /* 25Mhz */ 735 switch (mode) { 736 case ATA_PIO0: timing = 0xc0d08585; break; 737 case ATA_PIO1: timing = 0xc0d08572; break; 738 case ATA_PIO2: timing = 0xc0ca8542; break; 739 case ATA_PIO3: timing = 0xc0ca8532; break; 740 case ATA_PIO4: timing = 0xc0ca8521; break; 741 case ATA_WDMA2: timing = 0xa0ca8521; break; 742 case ATA_UDMA2: timing = 0x90cf8521; break; 743 case ATA_UDMA4: timing = 0x90c98521; break; 744 default: timing = 0x01208585; 745 } 746 break; 747 default: 748 case 0xa7: /* 33MHz */ 749 switch (mode) { 750 case ATA_PIO0: timing = 0xc0d0a7aa; break; 751 case ATA_PIO1: timing = 0xc0d0a7a3; break; 752 case ATA_PIO2: timing = 0xc0d0a753; break; 753 case ATA_PIO3: timing = 0xc0c8a742; break; 754 case ATA_PIO4: timing = 0xc0c8a731; break; 755 case ATA_WDMA2: timing = 0xa0c8a731; break; 756 case ATA_UDMA2: timing = 0x90caa731; break; 757 case ATA_UDMA4: timing = 0x90c9a731; break; 758 default: timing = 0x0120a7a7; 759 } 760 break; 761 case 0xd9: /* 40Mhz */ 762 switch (mode) { 763 case ATA_PIO0: timing = 0xc018d9d9; break; 764 case ATA_PIO1: timing = 0xc010d9c7; break; 765 case ATA_PIO2: timing = 0xc010d997; break; 766 case ATA_PIO3: timing = 0xc010d974; break; 767 case ATA_PIO4: timing = 0xc008d963; break; 768 case ATA_WDMA2: timing = 0xa008d943; break; 769 case ATA_UDMA2: timing = 0x900bd943; break; 770 case ATA_UDMA4: timing = 0x900fd943; break; 771 default: timing = 0x0120d9d9; 772 } 773 } 774 pci_write_config(parent, 0x40 + (devno << 2) , (timing & ~0x80000000), 4); 775 } 776 777 #else /* NPCI > 0 */ 778 779 void 780 ata_dmainit(struct ata_softc *scp, int32_t device, 781 int32_t piomode, int32_t wdmamode, int32_t udmamode) 782 { 783 } 784 785 int32_t 786 ata_dmasetup(struct ata_softc *scp, int32_t device, 787 int8_t *data, int32_t count, int32_t flags) 788 { 789 return -1; 790 } 791 792 void 793 ata_dmastart(struct ata_softc *scp) 794 { 795 } 796 797 int32_t 798 ata_dmadone(struct ata_softc *scp) 799 { 800 return -1; 801 } 802 803 int32_t 804 ata_dmastatus(struct ata_softc *scp) 805 { 806 return -1; 807 } 808 809 #endif /* NPCI > 0 */ 810