1 /*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include "pci.h" 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/buf.h> 35 #include <sys/malloc.h> 36 #include <sys/bus.h> 37 #include <sys/disk.h> 38 #include <sys/devicestat.h> 39 #include <vm/vm.h> 40 #include <vm/pmap.h> 41 #if NPCI > 0 42 #include <pci/pcivar.h> 43 #endif 44 #include <dev/ata/ata-all.h> 45 #include <dev/ata/ata-disk.h> 46 47 #if NPCI > 0 48 49 /* prototypes */ 50 static void promise_timing(struct ata_softc *, int32_t, int32_t); 51 static void hpt366_timing(struct ata_softc *, int32_t, int32_t); 52 53 /* misc defines */ 54 #ifdef __alpha__ 55 #undef vtophys 56 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 57 #endif 58 59 void 60 ata_dmainit(struct ata_softc *scp, int32_t device, 61 int32_t apiomode, int32_t wdmamode, int32_t udmamode) 62 { 63 device_t parent = device_get_parent(scp->dev); 64 int32_t devno = (scp->unit << 1) + ATA_DEV(device); 65 int32_t error; 66 67 /* set our most pessimistic default mode */ 68 scp->mode[ATA_DEV(device)] = ATA_PIO; 69 70 if (!scp->bmaddr) 71 return; 72 73 /* if simplex controller, only allow DMA on primary channel */ 74 if (scp->unit == 1) { 75 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 76 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 77 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 78 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 79 return; 80 } 81 } 82 83 if (!scp->dmatab[ATA_DEV(device)]) { 84 void *dmatab; 85 86 if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) 87 return; 88 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 89 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 90 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 91 free(dmatab, M_DEVBUF); 92 return; 93 } 94 scp->dmatab[ATA_DEV(device)] = dmatab; 95 } 96 97 switch (scp->chiptype) { 98 99 case 0x24118086: /* Intel ICH */ 100 if (udmamode >= 4) { 101 int32_t mask48, new48; 102 int16_t word54; 103 104 word54 = pci_read_config(parent, 0x54, 2); 105 if (word54 & (0x10 << devno)) { 106 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 107 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 108 if (bootverbose) 109 ata_printf(scp, device, 110 "%s setting up UDMA4 mode on ICH chip\n", 111 (error) ? "failed" : "success"); 112 if (!error) { 113 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 114 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 115 pci_write_config(parent, 0x48, 116 (pci_read_config(parent, 0x48, 4) & 117 ~mask48) | new48, 4); 118 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 119 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 120 return; 121 } 122 } 123 } 124 /* FALLTHROUGH */ 125 126 case 0x71118086: /* Intel PIIX4 */ 127 case 0x71998086: /* Intel PIIX4e */ 128 case 0x24218086: /* Intel ICH0 */ 129 if (udmamode >= 2) { 130 int32_t mask48, new48; 131 132 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 133 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 134 if (bootverbose) 135 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 136 (error) ? "failed" : "success", 137 (scp->chiptype == 0x24118086) ? "ICH" : 138 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 139 if (!error) { 140 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 141 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 142 pci_write_config(parent, 0x48, 143 (pci_read_config(parent, 0x48, 4) & 144 ~mask48) | new48, 4); 145 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 146 return; 147 } 148 } 149 /* FALLTHROUGH */ 150 151 case 0x70108086: /* Intel PIIX3 */ 152 if (wdmamode >= 2 && apiomode >= 4) { 153 int32_t mask40, new40, mask44, new44; 154 155 /* if SITRE not set doit for both channels */ 156 if (!((pci_read_config(parent, 0x40, 4)>>(scp->unit<<8))&0x4000)){ 157 new40 = pci_read_config(parent, 0x40, 4); 158 new44 = pci_read_config(parent, 0x44, 4); 159 if (!(new40 & 0x00004000)) { 160 new44 &= ~0x0000000f; 161 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 162 } 163 if (!(new40 & 0x40000000)) { 164 new44 &= ~0x000000f0; 165 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 166 } 167 new40 |= 0x40004000; 168 pci_write_config(parent, 0x40, new40, 4); 169 pci_write_config(parent, 0x44, new44, 4); 170 } 171 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 172 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 173 if (bootverbose) 174 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 175 (error) ? "failed" : "success", 176 (scp->chiptype == 0x70108086) ? "PIIX3" : 177 (scp->chiptype == 0x24118086) ? "ICH" : 178 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 179 if (!error) { 180 if (device == ATA_MASTER) { 181 mask40 = 0x0000330f; 182 new40 = 0x00002307; 183 mask44 = 0; 184 new44 = 0; 185 } 186 else { 187 mask40 = 0x000000f0; 188 new40 = 0x00000070; 189 mask44 = 0x0000000f; 190 new44 = 0x0000000b; 191 } 192 if (scp->unit) { 193 mask40 <<= 16; 194 new40 <<= 16; 195 mask44 <<= 4; 196 new44 <<= 4; 197 } 198 pci_write_config(parent, 0x40, 199 (pci_read_config(parent, 0x40, 4) & ~mask40)| 200 new40, 4); 201 pci_write_config(parent, 0x44, 202 (pci_read_config(parent, 0x44, 4) & ~mask44)| 203 new44, 4); 204 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 205 return; 206 } 207 } 208 /* we could set PIO mode timings, but we assume the BIOS did that */ 209 break; 210 211 case 0x12308086: /* Intel PIIX */ 212 if (wdmamode >= 2 && apiomode >= 4) { 213 int32_t word40; 214 215 word40 = pci_read_config(parent, 0x40, 4); 216 word40 >>= scp->unit * 16; 217 218 /* Check for timing config usable for DMA on controller */ 219 if (!((word40 & 0x3300) == 0x2300 && 220 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 221 break; 222 223 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 224 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 225 if (bootverbose) 226 ata_printf(scp, device, 227 "%s setting up WDMA2 mode on PIIX chip\n", 228 (error) ? "failed" : "success"); 229 if (!error) { 230 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 231 return; 232 } 233 } 234 break; 235 236 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 237 /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 238 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 239 ata_printf(scp, device, 240 "Aladdin: two atapi devices on this channel, no DMA\n"); 241 break; 242 } 243 if (udmamode >= 2) { 244 int32_t word54 = pci_read_config(parent, 0x54, 4); 245 246 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 247 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 248 if (bootverbose) 249 ata_printf(scp, device, 250 "%s setting up UDMA2 mode on Aladdin chip\n", 251 (error) ? "failed" : "success"); 252 if (!error) { 253 word54 |= 0x5555; 254 word54 |= (0x0a << (16 + (scp->unit << 3) + (device << 2))); 255 pci_write_config(parent, 0x54, word54, 4); 256 pci_write_config(parent, 0x53, 257 pci_read_config(parent, 0x53, 1) | 0x03, 1); 258 scp->flags |= ATA_ATAPI_DMA_RO; 259 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 260 return; 261 } 262 } 263 if (wdmamode >= 2 && apiomode >= 4) { 264 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 265 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 266 if (bootverbose) 267 ata_printf(scp, device, 268 "%s setting up WDMA2 mode on Aladdin chip\n", 269 (error) ? "failed" : "success"); 270 if (!error) { 271 pci_write_config(parent, 0x53, 272 pci_read_config(parent, 0x53, 1) | 0x03, 1); 273 scp->flags |= ATA_ATAPI_DMA_RO; 274 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 275 return; 276 } 277 } 278 pci_write_config(parent, 0x53, 279 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 280 /* we could set PIO mode timings, but we assume the BIOS did that */ 281 break; 282 283 case 0x74091022: /* AMD 756 */ 284 if (udmamode >= 4) { 285 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 286 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 287 if (bootverbose) 288 ata_printf(scp, device, 289 "%s setting up UDMA4 mode on AMD chip\n", 290 (error) ? "failed" : "success"); 291 if (!error) { 292 pci_write_config(parent, 0x53 - devno, 0xc3, 1); 293 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 294 return; 295 } 296 } 297 goto via_82c586; 298 299 case 0x06861106: /* VIA 82C686 */ 300 via_82c686: 301 if (udmamode >= 4) { 302 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 303 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 304 if (bootverbose) 305 ata_printf(scp, device, 306 "%s setting up UDMA4 mode on VIA chip\n", 307 (error) ? "failed" : "success"); 308 if (!error) { 309 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 310 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 311 return; 312 } 313 } 314 if (udmamode >= 2) { 315 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 316 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 317 if (bootverbose) 318 ata_printf(scp, device, 319 "%s setting up UDMA2 mode on VIA chip\n", 320 (error) ? "failed" : "success"); 321 if (!error) { 322 pci_write_config(parent, 0x53 - devno, 0xea, 1); 323 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 324 return; 325 } 326 } 327 goto via_generic; 328 329 case 0x05961106: /* VIA 82C596 */ 330 /* 82c596 revision >= 0x12 is like the 82c686 */ 331 if (ata_find_dev(parent, 0x05961106, 0x12)) 332 goto via_82c686; 333 /* FALLTHROUGH */ 334 335 case 0x05861106: /* VIA 82C586 */ 336 via_82c586: 337 /* UDMA2 mode only on 82C586 > rev1, 82C596, AMD 756 */ 338 if ((udmamode >= 2 && scp->chiptype == 0x05861106 && 339 pci_read_config(scp->dev, 0x08, 1) >= 0x01) || 340 (udmamode >= 2 && scp->chiptype == 0x05961106) || 341 (udmamode >= 2 && scp->chiptype == 0x74091022)) { 342 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 343 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 344 if (bootverbose) 345 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 346 (error) ? "failed" : "success", 347 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 348 if (!error) { 349 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 350 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 351 return; 352 } 353 } 354 /* FALLTHROUGH */ 355 356 case 0x05711106: /* VIA 82C571 */ 357 via_generic: 358 if (wdmamode >= 2 && apiomode >= 4) { 359 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 360 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 361 if (bootverbose) 362 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 363 (error) ? "failed" : "success", 364 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 365 if (!error) { 366 pci_write_config(parent, 0x53 - devno, 0x82, 1); 367 pci_write_config(parent, 0x4b - devno, 0x31, 1); 368 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 369 return; 370 } 371 } 372 /* we could set PIO mode timings, but we assume the BIOS did that */ 373 break; 374 375 case 0x55131039: /* SiS 5591 */ 376 if (udmamode >= 2) { 377 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 378 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 379 if (bootverbose) 380 ata_printf(scp, device, 381 "%s setting up UDMA2 mode on SiS chip\n", 382 (error) ? "failed" : "success"); 383 if (!error) { 384 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 385 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 386 return; 387 } 388 } 389 if (wdmamode >=2 && apiomode >= 4) { 390 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 391 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 392 if (bootverbose) 393 ata_printf(scp, device, 394 "%s setting up WDMA2 mode on SiS chip\n", 395 (error) ? "failed" : "success"); 396 if (!error) { 397 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 398 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 399 return; 400 } 401 } 402 /* we could set PIO mode timings, but we assume the BIOS did that */ 403 break; 404 405 case 0x06461095: /* CMD 646 ATA controller */ 406 if (wdmamode >= 2 && apiomode >= 4) { 407 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 408 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 409 if (bootverbose) 410 ata_printf(scp, device, 411 "%s setting up WDMA2 mode on CMD646 chip\n", 412 error ? "failed" : "success"); 413 if (!error) { 414 int32_t offset = (devno < 3) ? (devno << 1) : 7; 415 416 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 417 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 418 return; 419 } 420 } 421 /* we could set PIO mode timings, but we assume the BIOS did that */ 422 break; 423 424 case 0xc6931080: /* Cypress 82c693 ATA controller */ 425 if (wdmamode >= 2 && apiomode >= 4) { 426 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 427 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 428 if (bootverbose) 429 ata_printf(scp, device, 430 "%s setting up WDMA2 mode on Cypress chip\n", 431 error ? "failed" : "success"); 432 if (!error) { 433 pci_write_config(scp->dev, scp->unit ? 0x4e : 0x4c, 0x2020, 2); 434 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 435 return; 436 } 437 } 438 /* we could set PIO mode timings, but we assume the BIOS did that */ 439 break; 440 441 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */ 442 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */ 443 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 444 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 445 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 446 break; 447 448 if (udmamode >=4 && scp->chiptype == 0x4d38105a && 449 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 450 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 451 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 452 if (bootverbose) 453 ata_printf(scp, device, 454 "%s setting up UDMA4 mode on Promise chip\n", 455 (error) ? "failed" : "success"); 456 if (!error) { 457 promise_timing(scp, devno, ATA_UDMA4); 458 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 459 return; 460 } 461 } 462 if (udmamode >= 2) { 463 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 464 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 465 if (bootverbose) 466 ata_printf(scp, device, 467 "%s setting up UDMA2 mode on Promise chip\n", 468 (error) ? "failed" : "success"); 469 if (!error) { 470 promise_timing(scp, devno, ATA_UDMA2); 471 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 472 return; 473 } 474 } 475 if (wdmamode >= 2 && apiomode >= 4) { 476 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 477 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 478 if (bootverbose) 479 ata_printf(scp, device, 480 "%s setting up WDMA2 mode on Promise chip\n", 481 (error) ? "failed" : "success"); 482 if (!error) { 483 promise_timing(scp, devno, ATA_WDMA2); 484 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 485 return; 486 } 487 } 488 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 489 ata_pio2mode(apiomode), 490 ATA_C_F_SETXFER, ATA_WAIT_READY); 491 if (bootverbose) 492 ata_printf(scp, device, 493 "%s setting up PIO%d mode on Promise chip\n", 494 (error) ? "failed" : "success", 495 (apiomode >= 0) ? apiomode : 0); 496 promise_timing(scp, devno, ata_pio2mode(apiomode)); 497 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 498 return; 499 500 case 0x00041103: /* HighPoint HPT366 controller */ 501 /* no ATAPI devices for now */ 502 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 503 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 504 break; 505 506 if (udmamode >=4 && !(pci_read_config(parent, 0x5a, 1) & 0x2)) { 507 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 508 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 509 if (bootverbose) 510 ata_printf(scp, device, 511 "%s setting up UDMA4 mode on HPT366 chip\n", 512 (error) ? "failed" : "success"); 513 if (!error) { 514 hpt366_timing(scp, devno, ATA_UDMA4); 515 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 516 return; 517 } 518 } 519 if (udmamode >= 2) { 520 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 521 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 522 if (bootverbose) 523 ata_printf(scp, device, 524 "%s setting up UDMA2 mode on HPT366 chip\n", 525 (error) ? "failed" : "success"); 526 if (!error) { 527 hpt366_timing(scp, devno, ATA_UDMA2); 528 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 529 return; 530 } 531 } 532 if (wdmamode >= 2 && apiomode >= 4) { 533 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 534 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 535 if (bootverbose) 536 ata_printf(scp, device, 537 "%s setting up WDMA2 mode on HPT366 chip\n", 538 (error) ? "failed" : "success"); 539 if (!error) { 540 hpt366_timing(scp, devno, ATA_WDMA2); 541 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 542 return; 543 } 544 } 545 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 546 ata_pio2mode(apiomode), 547 ATA_C_F_SETXFER, ATA_WAIT_READY); 548 if (bootverbose) 549 ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n", 550 (error) ? "failed" : "success", 551 (apiomode >= 0) ? apiomode : 0); 552 hpt366_timing(scp, devno, ata_pio2mode(apiomode)); 553 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 554 return; 555 556 default: /* unknown controller chip */ 557 /* better not try generic DMA on ATAPI devices it almost never works */ 558 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 559 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 560 break; 561 562 /* if controller says its setup for DMA take the easy way out */ 563 /* the downside is we dont know what DMA mode we are in */ 564 if ((udmamode >= 0 || wdmamode > 1) && 565 (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 566 ((device==ATA_MASTER) ? 567 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 568 scp->mode[ATA_DEV(device)] = ATA_DMA; 569 return; 570 } 571 572 /* well, we have no support for this, but try anyways */ 573 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) { 574 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 575 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 576 if (bootverbose) 577 ata_printf(scp, device, 578 "%s setting up WDMA2 mode on generic chip\n", 579 (error) ? "failed" : "success"); 580 if (!error) { 581 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 582 return; 583 } 584 } 585 } 586 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 587 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 588 if (bootverbose) 589 ata_printf(scp, device, "%s setting up PIO%d mode on generic chip\n", 590 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 591 if (!error) 592 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 593 else { 594 if (bootverbose) 595 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 596 scp->mode[ATA_DEV(device)] = ATA_PIO; 597 } 598 } 599 600 int32_t 601 ata_dmasetup(struct ata_softc *scp, int32_t device, 602 int8_t *data, int32_t count, int32_t flags) 603 { 604 struct ata_dmaentry *dmatab; 605 u_int32_t dma_count, dma_base; 606 int32_t i = 0; 607 608 if (((uintptr_t)data & 1) || (count & 1)) 609 return -1; 610 611 if (!count) { 612 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 613 return -1; 614 } 615 616 dmatab = scp->dmatab[ATA_DEV(device)]; 617 dma_base = vtophys(data); 618 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 619 data += dma_count; 620 count -= dma_count; 621 622 while (count) { 623 dmatab[i].base = dma_base; 624 dmatab[i].count = (dma_count & 0xffff); 625 i++; 626 if (i >= ATA_DMA_ENTRIES) { 627 ata_printf(scp, device, "too many segments in DMA table\n"); 628 return -1; 629 } 630 dma_base = vtophys(data); 631 dma_count = min(count, PAGE_SIZE); 632 data += min(count, PAGE_SIZE); 633 count -= min(count, PAGE_SIZE); 634 } 635 dmatab[i].base = dma_base; 636 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 637 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 638 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0); 639 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 640 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 641 return 0; 642 } 643 644 void 645 ata_dmastart(struct ata_softc *scp) 646 { 647 scp->flags |= ATA_DMA_ACTIVE; 648 outb(scp->bmaddr + ATA_BMCMD_PORT, 649 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 650 } 651 652 int32_t 653 ata_dmadone(struct ata_softc *scp) 654 { 655 outb(scp->bmaddr + ATA_BMCMD_PORT, 656 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 657 scp->flags &= ~ATA_DMA_ACTIVE; 658 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 659 } 660 661 int32_t 662 ata_dmastatus(struct ata_softc *scp) 663 { 664 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 665 } 666 667 static void 668 promise_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 669 { 670 u_int32_t timing = 0; 671 struct promise_timing { 672 u_int8_t pa:4; 673 u_int8_t prefetch:1; 674 u_int8_t iordy:1; 675 u_int8_t errdy:1; 676 u_int8_t syncin:1; 677 u_int8_t pb:5; 678 u_int8_t mb:3; 679 u_int8_t mc:4; 680 u_int8_t dmaw:1; 681 u_int8_t dmar:1; 682 u_int8_t iordyp:1; 683 u_int8_t dmarqp:1; 684 u_int8_t reserved:8; 685 } *t = (struct promise_timing*)&timing; 686 687 t->iordy = 1; t->iordyp = 1; 688 if (mode >= ATA_DMA) { 689 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 690 } 691 692 switch (scp->chiptype) { 693 case 0x4d33105a: /* Promise 33's */ 694 switch (mode) { 695 default: 696 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 697 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 698 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 699 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 700 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 701 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 702 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 703 } 704 break; 705 706 case 0x4d38105a: /* Promise 66's */ 707 switch (mode) { 708 default: 709 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 710 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 711 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 712 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 713 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 714 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 715 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 716 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 717 } 718 break; 719 } 720 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 721 } 722 723 static void 724 hpt366_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 725 { 726 device_t parent = device_get_parent(scp->dev); 727 u_int32_t timing; 728 729 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 730 case 0x85: /* 25Mhz */ 731 switch (mode) { 732 case ATA_PIO0: timing = 0xc0d08585; break; 733 case ATA_PIO1: timing = 0xc0d08572; break; 734 case ATA_PIO2: timing = 0xc0ca8542; break; 735 case ATA_PIO3: timing = 0xc0ca8532; break; 736 case ATA_PIO4: timing = 0xc0ca8521; break; 737 case ATA_WDMA2: timing = 0xa0ca8521; break; 738 case ATA_UDMA2: timing = 0x90cf8521; break; 739 case ATA_UDMA4: timing = 0x90c98521; break; 740 default: timing = 0x01208585; 741 } 742 break; 743 default: 744 case 0xa7: /* 33MHz */ 745 switch (mode) { 746 case ATA_PIO0: timing = 0xc0d0a7aa; break; 747 case ATA_PIO1: timing = 0xc0d0a7a3; break; 748 case ATA_PIO2: timing = 0xc0d0a753; break; 749 case ATA_PIO3: timing = 0xc0c8a742; break; 750 case ATA_PIO4: timing = 0xc0c8a731; break; 751 case ATA_WDMA2: timing = 0xa0c8a731; break; 752 case ATA_UDMA2: timing = 0x90caa731; break; 753 case ATA_UDMA4: timing = 0x90c9a731; break; 754 default: timing = 0x0120a7a7; 755 } 756 break; 757 case 0xd9: /* 40Mhz */ 758 switch (mode) { 759 case ATA_PIO0: timing = 0xc018d9d9; break; 760 case ATA_PIO1: timing = 0xc010d9c7; break; 761 case ATA_PIO2: timing = 0xc010d997; break; 762 case ATA_PIO3: timing = 0xc010d974; break; 763 case ATA_PIO4: timing = 0xc008d963; break; 764 case ATA_WDMA2: timing = 0xa008d943; break; 765 case ATA_UDMA2: timing = 0x900bd943; break; 766 case ATA_UDMA4: timing = 0x900fd943; break; 767 default: timing = 0x0120d9d9; 768 } 769 } 770 pci_write_config(parent, 0x40 + (devno << 2) , (timing & ~0x80000000), 4); 771 } 772 773 #else /* NPCI > 0 */ 774 775 void 776 ata_dmainit(struct ata_softc *scp, int32_t device, 777 int32_t piomode, int32_t wdmamode, int32_t udmamode) 778 { 779 } 780 781 int32_t 782 ata_dmasetup(struct ata_softc *scp, int32_t device, 783 int8_t *data, int32_t count, int32_t flags) 784 { 785 return -1; 786 } 787 788 void 789 ata_dmastart(struct ata_softc *scp) 790 { 791 } 792 793 int32_t 794 ata_dmadone(struct ata_softc *scp) 795 { 796 return -1; 797 } 798 799 int32_t 800 ata_dmastatus(struct ata_softc *scp) 801 { 802 return -1; 803 } 804 805 #endif /* NPCI > 0 */ 806