1 /*- 2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include "pci.h" 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/ata.h> 35 #include <sys/bio.h> 36 #include <sys/malloc.h> 37 #include <sys/bus.h> 38 #include <sys/disk.h> 39 #include <sys/devicestat.h> 40 #include <vm/vm.h> 41 #include <vm/pmap.h> 42 #include <pci/pcivar.h> 43 #include <machine/bus.h> 44 #include <sys/rman.h> 45 #include <dev/ata/ata-all.h> 46 47 /* prototypes */ 48 static void cyrix_timing(struct ata_softc *, int, int); 49 static void promise_timing(struct ata_softc *, int, int); 50 static void hpt_timing(struct ata_softc *, int, int); 51 52 /* misc defines */ 53 #ifdef __alpha__ 54 #undef vtophys 55 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 56 #endif 57 58 void * 59 ata_dmaalloc(struct ata_softc *scp, int device) 60 { 61 void *dmatab; 62 63 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) { 64 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 65 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 66 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 67 free(dmatab, M_DEVBUF); 68 dmatab = NULL; 69 } 70 } 71 return dmatab; 72 } 73 74 void 75 ata_dmainit(struct ata_softc *scp, int device, 76 int apiomode, int wdmamode, int udmamode) 77 { 78 device_t parent = device_get_parent(scp->dev); 79 int devno = (scp->channel << 1) + ATA_DEV(device); 80 int error; 81 82 /* set our most pessimistic default mode */ 83 scp->mode[ATA_DEV(device)] = ATA_PIO; 84 85 if (!scp->r_bmio) 86 return; 87 88 /* if simplex controller, only allow DMA on primary channel */ 89 if (scp->channel == 1) { 90 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 91 ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 92 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 93 if (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 94 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 95 return; 96 } 97 } 98 99 /* DMA engine address alignment is usually 1 word (2 bytes) */ 100 scp->alignment = 0x1; 101 102 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) { 103 ata_printf(scp, device, 104 "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 105 udmamode = 2; 106 } 107 108 switch (scp->chiptype) { 109 110 case 0x244a8086: /* Intel ICH2 mobile */ 111 case 0x244b8086: /* Intel ICH2 */ 112 if (udmamode >= 5) { 113 int32_t mask48, new48; 114 int16_t word54; 115 116 word54 = pci_read_config(parent, 0x54, 2); 117 if (word54 & (0x10 << devno)) { 118 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 119 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 120 if (bootverbose) 121 ata_printf(scp, device, 122 "%s setting UDMA5 on Intel chip\n", 123 (error) ? "failed" : "success"); 124 if (!error) { 125 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 126 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 127 pci_write_config(parent, 0x48, 128 (pci_read_config(parent, 0x48, 4) & 129 ~mask48) | new48, 4); 130 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 131 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 132 return; 133 } 134 } 135 } 136 /* make sure eventual ATA100 mode from the BIOS is disabled */ 137 pci_write_config(parent, 0x54, 138 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 139 /* FALLTHROUGH */ 140 141 case 0x24118086: /* Intel ICH */ 142 if (udmamode >= 4) { 143 int32_t mask48, new48; 144 int16_t word54; 145 146 word54 = pci_read_config(parent, 0x54, 2); 147 if (word54 & (0x10 << devno)) { 148 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 149 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 150 if (bootverbose) 151 ata_printf(scp, device, 152 "%s setting UDMA4 on Intel chip\n", 153 (error) ? "failed" : "success"); 154 if (!error) { 155 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 156 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 157 pci_write_config(parent, 0x48, 158 (pci_read_config(parent, 0x48, 4) & 159 ~mask48) | new48, 4); 160 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 161 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 162 return; 163 } 164 } 165 } 166 /* make sure eventual ATA66 mode from the BIOS is disabled */ 167 pci_write_config(parent, 0x54, 168 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 169 /* FALLTHROUGH */ 170 171 case 0x71118086: /* Intel PIIX4 */ 172 case 0x71998086: /* Intel PIIX4e */ 173 case 0x24218086: /* Intel ICH0 */ 174 if (udmamode >= 2) { 175 int32_t mask48, new48; 176 177 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 178 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 179 if (bootverbose) 180 ata_printf(scp, device, "%s setting UDMA2 on Intel chip\n", 181 (error) ? "failed" : "success"); 182 if (!error) { 183 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 184 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 185 pci_write_config(parent, 0x48, 186 (pci_read_config(parent, 0x48, 4) & 187 ~mask48) | new48, 4); 188 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 189 return; 190 } 191 } 192 /* make sure eventual ATA33 mode from the BIOS is disabled */ 193 pci_write_config(parent, 0x48, 194 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 195 /* FALLTHROUGH */ 196 197 case 0x70108086: /* Intel PIIX3 */ 198 if (wdmamode >= 2 && apiomode >= 4) { 199 int32_t mask40, new40, mask44, new44; 200 201 /* if SITRE not set doit for both channels */ 202 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 203 new40 = pci_read_config(parent, 0x40, 4); 204 new44 = pci_read_config(parent, 0x44, 4); 205 if (!(new40 & 0x00004000)) { 206 new44 &= ~0x0000000f; 207 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 208 } 209 if (!(new40 & 0x40000000)) { 210 new44 &= ~0x000000f0; 211 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 212 } 213 new40 |= 0x40004000; 214 pci_write_config(parent, 0x40, new40, 4); 215 pci_write_config(parent, 0x44, new44, 4); 216 } 217 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 218 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 219 if (bootverbose) 220 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n", 221 (error) ? "failed" : "success"); 222 if (!error) { 223 if (device == ATA_MASTER) { 224 mask40 = 0x0000330f; 225 new40 = 0x00002307; 226 mask44 = 0; 227 new44 = 0; 228 } 229 else { 230 mask40 = 0x000000f0; 231 new40 = 0x00000070; 232 mask44 = 0x0000000f; 233 new44 = 0x0000000b; 234 } 235 if (scp->channel) { 236 mask40 <<= 16; 237 new40 <<= 16; 238 mask44 <<= 4; 239 new44 <<= 4; 240 } 241 pci_write_config(parent, 0x40, 242 (pci_read_config(parent, 0x40, 4) & ~mask40)| 243 new40, 4); 244 pci_write_config(parent, 0x44, 245 (pci_read_config(parent, 0x44, 4) & ~mask44)| 246 new44, 4); 247 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 248 return; 249 } 250 } 251 /* we could set PIO mode timings, but we assume the BIOS did that */ 252 break; 253 254 case 0x12308086: /* Intel PIIX */ 255 if (wdmamode >= 2 && apiomode >= 4) { 256 int32_t word40; 257 258 word40 = pci_read_config(parent, 0x40, 4); 259 word40 >>= scp->channel * 16; 260 261 /* Check for timing config usable for DMA on controller */ 262 if (!((word40 & 0x3300) == 0x2300 && 263 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 264 break; 265 266 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 267 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 268 if (bootverbose) 269 ata_printf(scp, device, 270 "%s setting WDMA2 on Intel chip\n", 271 (error) ? "failed" : "success"); 272 if (!error) { 273 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 274 return; 275 } 276 } 277 break; 278 279 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 280 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 281 if (pci_get_revid(parent) < 0xC2 && 282 scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 283 ata_printf(scp, device, 284 "Aladdin: two atapi devices on this channel, no DMA\n"); 285 break; 286 } 287 if (udmamode >= 5 && pci_get_revid(parent) >= 0xC4) { 288 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 289 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 290 if (bootverbose) 291 ata_printf(scp, device, 292 "%s setting UDMA5 on Acer chip\n", 293 (error) ? "failed" : "success"); 294 if (!error) { 295 int32_t word54 = pci_read_config(parent, 0x54, 4); 296 297 pci_write_config(parent, 0x4b, 298 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 299 word54 &= ~(0x000f000f << (devno << 2)); 300 word54 |= (0x000f0005 << (devno << 2)); 301 pci_write_config(parent, 0x54, word54, 4); 302 pci_write_config(parent, 0x53, 303 pci_read_config(parent, 0x53, 1) | 0x03, 1); 304 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 305 return; 306 } 307 } 308 if (udmamode >= 4 && pci_get_revid(parent) >= 0xC2) { 309 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 310 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 311 if (bootverbose) 312 ata_printf(scp, device, 313 "%s setting UDMA4 on Acer chip\n", 314 (error) ? "failed" : "success"); 315 if (!error) { 316 int32_t word54 = pci_read_config(parent, 0x54, 4); 317 318 pci_write_config(parent, 0x4b, 319 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 320 word54 &= ~(0x000f000f << (devno << 2)); 321 word54 |= (0x00080005 << (devno << 2)); 322 pci_write_config(parent, 0x54, word54, 4); 323 pci_write_config(parent, 0x53, 324 pci_read_config(parent, 0x53, 1) | 0x03, 1); 325 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 326 return; 327 } 328 } 329 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 330 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 331 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 332 if (bootverbose) 333 ata_printf(scp, device, 334 "%s setting UDMA2 on Acer chip\n", 335 (error) ? "failed" : "success"); 336 if (!error) { 337 int32_t word54 = pci_read_config(parent, 0x54, 4); 338 339 word54 &= ~(0x000f000f << (devno << 2)); 340 word54 |= (0x000a0005 << (devno << 2)); 341 pci_write_config(parent, 0x54, word54, 4); 342 pci_write_config(parent, 0x53, 343 pci_read_config(parent, 0x53, 1) | 0x03, 1); 344 scp->flags |= ATA_ATAPI_DMA_RO; 345 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 346 return; 347 } 348 } 349 350 /* make sure eventual UDMA mode from the BIOS is disabled */ 351 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 352 ~(0x0008 << (devno << 2)), 2); 353 354 if (wdmamode >= 2 && apiomode >= 4) { 355 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 356 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 357 if (bootverbose) 358 ata_printf(scp, device, 359 "%s setting WDMA2 on Acer chip\n", 360 (error) ? "failed" : "success"); 361 if (!error) { 362 pci_write_config(parent, 0x53, 363 pci_read_config(parent, 0x53, 1) | 0x03, 1); 364 scp->flags |= ATA_ATAPI_DMA_RO; 365 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 366 return; 367 } 368 } 369 pci_write_config(parent, 0x53, 370 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 371 /* we could set PIO mode timings, but we assume the BIOS did that */ 372 break; 373 374 case 0x74111022: /* AMD 766 */ 375 if (udmamode >= 5) { 376 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 377 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 378 if (bootverbose) 379 ata_printf(scp, device, 380 "%s setting UDMA5 on AMD chip\n", 381 (error) ? "failed" : "success"); 382 if (!error) { 383 pci_write_config(parent, 0x53 - devno, 0xc6, 1); 384 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 385 return; 386 } 387 } 388 /* FALLTHROUGH */ 389 390 case 0x74091022: /* AMD 756 */ 391 if (udmamode >= 4) { 392 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 393 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 394 if (bootverbose) 395 ata_printf(scp, device, 396 "%s setting UDMA4 on AMD chip\n", 397 (error) ? "failed" : "success"); 398 if (!error) { 399 pci_write_config(parent, 0x53 - devno, 0xc5, 1); 400 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 401 return; 402 } 403 } 404 goto via_82c586; 405 406 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 407 if (ata_find_dev(parent, 0x06861106, 0x40)) { /* 82C686b */ 408 if (udmamode >= 5) { 409 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 410 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 411 if (bootverbose) 412 ata_printf(scp, device, 413 "%s setting UDMA5 on VIA chip\n", 414 (error) ? "failed" : "success"); 415 if (!error) { 416 pci_write_config(parent, 0x53 - devno, 0xf0, 1); 417 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 418 return; 419 } 420 } 421 if (udmamode >= 4) { 422 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 423 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 424 if (bootverbose) 425 ata_printf(scp, device, 426 "%s setting UDMA4 on VIA chip\n", 427 (error) ? "failed" : "success"); 428 if (!error) { 429 pci_write_config(parent, 0x53 - devno, 0xf1, 1); 430 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 431 return; 432 } 433 } 434 if (udmamode >= 2) { 435 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 436 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 437 if (bootverbose) 438 ata_printf(scp, device, 439 "%s setting UDMA2 on VIA chip\n", 440 (error) ? "failed" : "success"); 441 if (!error) { 442 pci_write_config(parent, 0x53 - devno, 0xf4, 1); 443 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 444 return; 445 } 446 } 447 } 448 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 449 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 450 if (udmamode >= 4) { 451 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 452 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 453 if (bootverbose) 454 ata_printf(scp, device, 455 "%s setting UDMA4 on VIA chip\n", 456 (error) ? "failed" : "success"); 457 if (!error) { 458 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 459 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 460 return; 461 } 462 } 463 if (udmamode >= 2) { 464 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 465 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 466 if (bootverbose) 467 ata_printf(scp, device, 468 "%s setting UDMA2 on VIA chip\n", 469 (error) ? "failed" : "success"); 470 if (!error) { 471 pci_write_config(parent, 0x53 - devno, 0xea, 1); 472 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 473 return; 474 } 475 } 476 } 477 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 478 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 479 via_82c586: 480 if (udmamode >= 2) { 481 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 482 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 483 if (bootverbose) 484 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 485 (error) ? "failed" : "success", 486 ((scp->chiptype == 0x74091022) || 487 (scp->chiptype == 0x74111022)) ? "AMD" : "VIA"); 488 if (!error) { 489 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 490 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 491 return; 492 } 493 } 494 } 495 if (wdmamode >= 2 && apiomode >= 4) { 496 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 497 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 498 if (bootverbose) 499 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 500 (error) ? "failed" : "success", 501 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 502 if (!error) { 503 pci_write_config(parent, 0x53 - devno, 0x0b, 1); 504 pci_write_config(parent, 0x4b - devno, 0x31, 1); 505 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 506 return; 507 } 508 } 509 /* we could set PIO mode timings, but we assume the BIOS did that */ 510 break; 511 512 case 0x55131039: /* SiS 5591 */ 513 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 514 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 515 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 516 if (bootverbose) 517 ata_printf(scp, device, 518 "%s setting UDMA2 on SiS chip\n", 519 (error) ? "failed" : "success"); 520 if (!error) { 521 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 522 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 523 return; 524 } 525 } 526 if (wdmamode >=2 && apiomode >= 4) { 527 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 528 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 529 if (bootverbose) 530 ata_printf(scp, device, 531 "%s setting WDMA2 on SiS chip\n", 532 (error) ? "failed" : "success"); 533 if (!error) { 534 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 535 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 536 return; 537 } 538 } 539 /* we could set PIO mode timings, but we assume the BIOS did that */ 540 break; 541 542 case 0x06491095: /* CMD 649 ATA100 controller */ 543 if (udmamode >= 5) { 544 u_int8_t umode; 545 546 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 547 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 548 if (bootverbose) 549 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 550 (error) ? "failed" : "success"); 551 if (!error) { 552 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 553 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 554 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 555 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 556 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 557 return; 558 } 559 } 560 /* FALLTHROUGH */ 561 562 case 0x06481095: /* CMD 648 ATA66 controller */ 563 if (udmamode >= 4) { 564 u_int8_t umode; 565 566 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 567 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 568 if (bootverbose) 569 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 570 (error) ? "failed" : "success"); 571 if (!error) { 572 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 573 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 574 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 575 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 576 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 577 return; 578 } 579 } 580 if (udmamode >= 2) { 581 u_int8_t umode; 582 583 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 584 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 585 if (bootverbose) 586 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 587 (error) ? "failed" : "success"); 588 if (!error) { 589 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 590 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 591 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 592 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 593 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 594 return; 595 } 596 } 597 /* make sure eventual UDMA mode from the BIOS is disabled */ 598 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 599 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 600 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 601 /* FALLTHROUGH */ 602 603 case 0x06461095: /* CMD 646 ATA controller */ 604 if (wdmamode >= 2 && apiomode >= 4) { 605 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 606 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 607 if (bootverbose) 608 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 609 error ? "failed" : "success"); 610 if (!error) { 611 int32_t offset = (devno < 3) ? (devno << 1) : 7; 612 613 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 614 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 615 return; 616 } 617 } 618 /* we could set PIO mode timings, but we assume the BIOS did that */ 619 break; 620 621 case 0xc6931080: /* Cypress 82c693 ATA controller */ 622 if (wdmamode >= 2 && apiomode >= 4) { 623 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 624 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 625 if (bootverbose) 626 ata_printf(scp, device, 627 "%s setting WDMA2 on Cypress chip\n", 628 error ? "failed" : "success"); 629 if (!error) { 630 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 631 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 632 return; 633 } 634 } 635 /* we could set PIO mode timings, but we assume the BIOS did that */ 636 break; 637 638 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 639 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 640 if (udmamode >= 2) { 641 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 642 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 643 if (bootverbose) 644 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 645 (error) ? "failed" : "success"); 646 if (!error) { 647 cyrix_timing(scp, devno, ATA_UDMA2); 648 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 649 return; 650 } 651 } 652 if (wdmamode >= 2 && apiomode >= 4) { 653 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 654 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 655 if (bootverbose) 656 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 657 (error) ? "failed" : "success"); 658 if (!error) { 659 cyrix_timing(scp, devno, ATA_WDMA2); 660 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 661 return; 662 } 663 } 664 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 665 ata_pio2mode(apiomode), ATA_C_F_SETXFER, 666 ATA_WAIT_READY); 667 if (bootverbose) 668 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 669 (error) ? "failed" : "success", 670 ata_mode2str(ata_pio2mode(apiomode))); 671 cyrix_timing(scp, devno, ata_pio2mode(apiomode)); 672 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 673 return; 674 675 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 676 if (udmamode >= 2) { 677 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 678 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 679 if (bootverbose) 680 ata_printf(scp, device, 681 "%s setting UDMA2 on ServerWorks chip\n", 682 (error) ? "failed" : "success"); 683 if (!error) { 684 u_int16_t reg56; 685 686 pci_write_config(parent, 0x54, 687 pci_read_config(parent, 0x54, 1) | 688 (0x01 << devno), 1); 689 reg56 = pci_read_config(parent, 0x56, 2); 690 reg56 &= ~(0xf << (devno * 4)); 691 reg56 |= (0x2 << (devno * 4)); 692 pci_write_config(parent, 0x56, reg56, 2); 693 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 694 return; 695 } 696 } 697 if (wdmamode >= 2 && apiomode >= 4) { 698 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 699 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 700 if (bootverbose) 701 ata_printf(scp, device, 702 "%s setting WDMA2 on ServerWorks chip\n", 703 (error) ? "failed" : "success"); 704 if (!error) { 705 int offset = (scp->channel * 2) + (device == ATA_MASTER); 706 int word44 = pci_read_config(parent, 0x44, 4); 707 708 pci_write_config(parent, 0x54, 709 pci_read_config(parent, 0x54, 1) & 710 ~(0x01 << devno), 1); 711 word44 &= ~(0xff << (offset << 8)); 712 word44 |= (0x20 << (offset << 8)); 713 pci_write_config(parent, 0x44, 0x20, 4); 714 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 715 return; 716 } 717 } 718 /* we could set PIO mode timings, but we assume the BIOS did that */ 719 break; 720 721 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 722 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 723 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 724 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 725 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 726 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 727 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 728 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 729 break; 730 731 if (udmamode >= 5 && (scp->chiptype == 0x4d30105a || 732 scp->chiptype == 0x0d30105a || scp->chiptype == 0x4d68105a) && 733 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 734 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 735 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 736 if (bootverbose) 737 ata_printf(scp, device, 738 "%s setting UDMA5 on Promise chip\n", 739 (error) ? "failed" : "success"); 740 if (!error) { 741 promise_timing(scp, devno, ATA_UDMA5); 742 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 743 return; 744 } 745 } 746 if (udmamode >= 4 && 747 (scp->chiptype == 0x4d38105a || scp->chiptype == 0x4d30105a || 748 scp->chiptype == 0x0d30105a || scp->chiptype == 0x4d68105a) && 749 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 750 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 751 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 752 if (bootverbose) 753 ata_printf(scp, device, 754 "%s setting UDMA4 on Promise chip\n", 755 (error) ? "failed" : "success"); 756 if (!error) { 757 promise_timing(scp, devno, ATA_UDMA4); 758 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 759 return; 760 } 761 } 762 if (udmamode >= 2) { 763 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 764 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 765 if (bootverbose) 766 ata_printf(scp, device, 767 "%s setting UDMA2 on Promise chip\n", 768 (error) ? "failed" : "success"); 769 if (!error) { 770 promise_timing(scp, devno, ATA_UDMA2); 771 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 772 return; 773 } 774 } 775 if (wdmamode >= 2 && apiomode >= 4) { 776 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 777 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 778 if (bootverbose) 779 ata_printf(scp, device, 780 "%s setting WDMA2 on Promise chip\n", 781 (error) ? "failed" : "success"); 782 if (!error) { 783 promise_timing(scp, devno, ATA_WDMA2); 784 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 785 return; 786 } 787 } 788 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 789 ata_pio2mode(apiomode), 790 ATA_C_F_SETXFER, ATA_WAIT_READY); 791 if (bootverbose) 792 ata_printf(scp, device, 793 "%s setting PIO%d on Promise chip\n", 794 (error) ? "failed" : "success", 795 (apiomode >= 0) ? apiomode : 0); 796 promise_timing(scp, devno, ata_pio2mode(apiomode)); 797 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 798 return; 799 800 case 0x00041103: /* HighPoint HPT366/368/370 controllers */ 801 /* no ATAPI devices for now */ 802 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 803 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 804 break; 805 806 if (udmamode >=5 && pci_get_revid(parent) >= 0x03 && 807 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 808 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 809 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 810 if (bootverbose) 811 ata_printf(scp, device, 812 "%s setting UDMA5 on HighPoint chip\n", 813 (error) ? "failed" : "success"); 814 if (!error) { 815 hpt_timing(scp, devno, ATA_UDMA5); 816 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 817 return; 818 } 819 } 820 if (udmamode >=4 && 821 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 822 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 823 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 824 if (bootverbose) 825 ata_printf(scp, device, 826 "%s setting UDMA4 on HighPoint chip\n", 827 (error) ? "failed" : "success"); 828 if (!error) { 829 hpt_timing(scp, devno, ATA_UDMA4); 830 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 831 return; 832 } 833 } 834 if (udmamode >= 2) { 835 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 836 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 837 if (bootverbose) 838 ata_printf(scp, device, 839 "%s setting UDMA2 on HighPoint chip\n", 840 (error) ? "failed" : "success"); 841 if (!error) { 842 hpt_timing(scp, devno, ATA_UDMA2); 843 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 844 return; 845 } 846 } 847 if (wdmamode >= 2 && apiomode >= 4) { 848 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 849 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 850 if (bootverbose) 851 ata_printf(scp, device, 852 "%s setting WDMA2 on HighPoint chip\n", 853 (error) ? "failed" : "success"); 854 if (!error) { 855 hpt_timing(scp, devno, ATA_WDMA2); 856 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 857 return; 858 } 859 } 860 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 861 ata_pio2mode(apiomode), 862 ATA_C_F_SETXFER, ATA_WAIT_READY); 863 if (bootverbose) 864 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 865 (error) ? "failed" : "success", 866 (apiomode >= 0) ? apiomode : 0); 867 hpt_timing(scp, devno, ata_pio2mode(apiomode)); 868 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 869 return; 870 871 default: /* unknown controller chip */ 872 /* better not try generic DMA on ATAPI devices it almost never works */ 873 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 874 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 875 break; 876 877 /* if controller says its setup for DMA take the easy way out */ 878 /* the downside is we dont know what DMA mode we are in */ 879 if ((udmamode >= 0 || wdmamode > 1) && 880 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 881 ((device==ATA_MASTER) ? 882 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 883 scp->mode[ATA_DEV(device)] = ATA_DMA; 884 return; 885 } 886 887 /* well, we have no support for this, but try anyways */ 888 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) { 889 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 890 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 891 if (bootverbose) 892 ata_printf(scp, device, 893 "%s setting WDMA2 on generic chip\n", 894 (error) ? "failed" : "success"); 895 if (!error) { 896 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 897 return; 898 } 899 } 900 } 901 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 902 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 903 if (bootverbose) 904 ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 905 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 906 if (!error) 907 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 908 else { 909 if (bootverbose) 910 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 911 scp->mode[ATA_DEV(device)] = ATA_PIO; 912 } 913 } 914 915 int 916 ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 917 caddr_t data, int32_t count) 918 { 919 u_int32_t dma_count, dma_base; 920 int i = 0; 921 922 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 923 ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 924 return -1; 925 } 926 927 if (!count) { 928 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 929 return -1; 930 } 931 932 dma_base = vtophys(data); 933 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 934 data += dma_count; 935 count -= dma_count; 936 937 while (count) { 938 dmatab[i].base = dma_base; 939 dmatab[i].count = (dma_count & 0xffff); 940 i++; 941 if (i >= ATA_DMA_ENTRIES) { 942 ata_printf(scp, device, "too many segments in DMA table\n"); 943 return -1; 944 } 945 dma_base = vtophys(data); 946 dma_count = min(count, PAGE_SIZE); 947 data += min(count, PAGE_SIZE); 948 count -= min(count, PAGE_SIZE); 949 } 950 dmatab[i].base = dma_base; 951 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 952 return 0; 953 } 954 955 void 956 ata_dmastart(struct ata_softc *scp, int device, 957 struct ata_dmaentry *dmatab, int dir) 958 { 959 scp->flags |= ATA_DMA_ACTIVE; 960 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab)); 961 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 962 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 963 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) | 964 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 965 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 966 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 967 } 968 969 int 970 ata_dmadone(struct ata_softc *scp) 971 { 972 int error; 973 974 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 975 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 976 scp->flags &= ~ATA_DMA_ACTIVE; 977 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT); 978 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 979 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 980 return error & ATA_BMSTAT_MASK; 981 } 982 983 int 984 ata_dmastatus(struct ata_softc *scp) 985 { 986 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 987 } 988 989 static void 990 cyrix_timing(struct ata_softc *scp, int devno, int mode) 991 { 992 u_int32_t reg20 = 0x0000e132; 993 u_int32_t reg24 = 0x00017771; 994 995 switch (mode) { 996 case ATA_PIO0: reg20 = 0x0000e132; break; 997 case ATA_PIO1: reg20 = 0x00018121; break; 998 case ATA_PIO2: reg20 = 0x00024020; break; 999 case ATA_PIO3: reg20 = 0x00032010; break; 1000 case ATA_PIO4: reg20 = 0x00040010; break; 1001 case ATA_WDMA2: reg24 = 0x00002020; break; 1002 case ATA_UDMA2: reg24 = 0x00911030; break; 1003 } 1004 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20); 1005 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24); 1006 } 1007 1008 static void 1009 promise_timing(struct ata_softc *scp, int devno, int mode) 1010 { 1011 u_int32_t timing = 0; 1012 struct promise_timing { 1013 u_int8_t pa:4; 1014 u_int8_t prefetch:1; 1015 u_int8_t iordy:1; 1016 u_int8_t errdy:1; 1017 u_int8_t syncin:1; 1018 u_int8_t pb:5; 1019 u_int8_t mb:3; 1020 u_int8_t mc:4; 1021 u_int8_t dmaw:1; 1022 u_int8_t dmar:1; 1023 u_int8_t iordyp:1; 1024 u_int8_t dmarqp:1; 1025 u_int8_t reserved:8; 1026 } *t = (struct promise_timing*)&timing; 1027 1028 t->iordy = 1; t->iordyp = 1; 1029 if (mode >= ATA_DMA) { 1030 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1031 } 1032 1033 switch (scp->chiptype) { 1034 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1035 switch (mode) { 1036 default: 1037 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1038 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1039 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1040 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1041 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1042 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1043 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1044 } 1045 break; 1046 1047 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1048 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1049 case 0x0d30105a: /* Promise OEM ATA 100 */ 1050 case 0x4d68105a: /* Promise TX2 ATA 100 */ 1051 switch (mode) { 1052 default: 1053 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1054 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1055 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1056 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1057 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1058 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1059 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1060 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1061 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1062 } 1063 break; 1064 } 1065 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 1066 } 1067 1068 static void 1069 hpt_timing(struct ata_softc *scp, int devno, int mode) 1070 { 1071 device_t parent = device_get_parent(scp->dev); 1072 u_int32_t timing; 1073 1074 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 1075 switch (mode) { 1076 case ATA_PIO0: timing = 0x06914e57; break; 1077 case ATA_PIO1: timing = 0x06914e43; break; 1078 case ATA_PIO2: timing = 0x06514e33; break; 1079 case ATA_PIO3: timing = 0x06514e22; break; 1080 case ATA_PIO4: timing = 0x06514e21; break; 1081 case ATA_WDMA2: timing = 0x26514e21; break; 1082 case ATA_UDMA2: timing = 0x16494e31; break; 1083 case ATA_UDMA4: timing = 0x16454e31; break; 1084 case ATA_UDMA5: timing = 0x16454e31; break; 1085 default: timing = 0x06514e57; 1086 } 1087 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1088 pci_write_config(parent, 0x5b, 0x22, 1); 1089 } 1090 else { /* HPT36[68] */ 1091 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1092 case 0x85: /* 25Mhz */ 1093 switch (mode) { 1094 case ATA_PIO0: timing = 0xc0d08585; break; 1095 case ATA_PIO1: timing = 0xc0d08572; break; 1096 case ATA_PIO2: timing = 0xc0ca8542; break; 1097 case ATA_PIO3: timing = 0xc0ca8532; break; 1098 case ATA_PIO4: timing = 0xc0ca8521; break; 1099 case ATA_WDMA2: timing = 0xa0ca8521; break; 1100 case ATA_UDMA2: timing = 0x90cf8521; break; 1101 case ATA_UDMA4: timing = 0x90c98521; break; 1102 default: timing = 0x01208585; 1103 } 1104 break; 1105 default: 1106 case 0xa7: /* 33MHz */ 1107 switch (mode) { 1108 case ATA_PIO0: timing = 0xc0d0a7aa; break; 1109 case ATA_PIO1: timing = 0xc0d0a7a3; break; 1110 case ATA_PIO2: timing = 0xc0d0a753; break; 1111 case ATA_PIO3: timing = 0xc0c8a742; break; 1112 case ATA_PIO4: timing = 0xc0c8a731; break; 1113 case ATA_WDMA2: timing = 0xa0c8a731; break; 1114 case ATA_UDMA2: timing = 0x90caa731; break; 1115 case ATA_UDMA4: timing = 0x90c9a731; break; 1116 default: timing = 0x0120a7a7; 1117 } 1118 break; 1119 case 0xd9: /* 40Mhz */ 1120 switch (mode) { 1121 case ATA_PIO0: timing = 0xc018d9d9; break; 1122 case ATA_PIO1: timing = 0xc010d9c7; break; 1123 case ATA_PIO2: timing = 0xc010d997; break; 1124 case ATA_PIO3: timing = 0xc010d974; break; 1125 case ATA_PIO4: timing = 0xc008d963; break; 1126 case ATA_WDMA2: timing = 0xa008d943; break; 1127 case ATA_UDMA2: timing = 0x900bd943; break; 1128 case ATA_UDMA4: timing = 0x900fd943; break; 1129 default: timing = 0x0120d9d9; 1130 } 1131 } 1132 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 1133 } 1134 } 1135