1 /*- 2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include "pci.h" 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/ata.h> 35 #include <sys/bio.h> 36 #include <sys/malloc.h> 37 #include <sys/bus.h> 38 #include <sys/disk.h> 39 #include <sys/devicestat.h> 40 #include <vm/vm.h> 41 #include <vm/pmap.h> 42 #include <pci/pcivar.h> 43 #include <machine/bus.h> 44 #include <sys/rman.h> 45 #include <dev/ata/ata-all.h> 46 47 /* prototypes */ 48 static void cyrix_timing(struct ata_softc *, int, int); 49 static void promise_timing(struct ata_softc *, int, int); 50 static void hpt_timing(struct ata_softc *, int, int); 51 52 /* misc defines */ 53 #ifdef __alpha__ 54 #undef vtophys 55 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 56 #endif 57 #define ATAPI_DEVICE(scp, device) \ 58 ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || \ 59 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 60 61 62 void * 63 ata_dmaalloc(struct ata_softc *scp, int device) 64 { 65 void *dmatab; 66 67 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) { 68 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 69 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 70 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 71 free(dmatab, M_DEVBUF); 72 dmatab = NULL; 73 } 74 } 75 return dmatab; 76 } 77 78 void 79 ata_dmainit(struct ata_softc *scp, int device, 80 int apiomode, int wdmamode, int udmamode) 81 { 82 device_t parent = device_get_parent(scp->dev); 83 int devno = (scp->channel << 1) + ATA_DEV(device); 84 int error; 85 86 /* set our most pessimistic default mode */ 87 scp->mode[ATA_DEV(device)] = ATA_PIO; 88 89 if (!scp->r_bmio) 90 return; 91 92 /* if simplex controller, only allow DMA on primary channel */ 93 if (scp->channel == 1) { 94 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 95 ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 96 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 97 if (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 98 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 99 return; 100 } 101 } 102 103 /* DMA engine address alignment is usually 1 word (2 bytes) */ 104 scp->alignment = 0x1; 105 106 #if 1 107 if (udmamode > 2 && !ATA_PARAM(scp, device)->hwres_cblid) { 108 ata_printf(scp, device, 109 "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 110 udmamode = 2; 111 } 112 #endif 113 switch (scp->chiptype) { 114 115 case 0x248a8086: /* Intel ICH3 mobile */ 116 case 0x248b8086: /* Intel ICH3 */ 117 case 0x244a8086: /* Intel ICH2 mobile */ 118 case 0x244b8086: /* Intel ICH2 */ 119 if (udmamode >= 5) { 120 int32_t mask48, new48; 121 int16_t word54; 122 123 word54 = pci_read_config(parent, 0x54, 2); 124 if (word54 & (0x10 << devno)) { 125 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 126 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 127 if (bootverbose) 128 ata_printf(scp, device, "%s setting UDMA5 on Intel chip\n", 129 (error) ? "failed" : "success"); 130 if (!error) { 131 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 132 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 133 pci_write_config(parent, 0x48, 134 (pci_read_config(parent, 0x48, 4) & 135 ~mask48) | new48, 4); 136 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 137 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 138 return; 139 } 140 } 141 } 142 /* make sure eventual ATA100 mode from the BIOS is disabled */ 143 pci_write_config(parent, 0x54, 144 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 145 /* FALLTHROUGH */ 146 147 case 0x24118086: /* Intel ICH */ 148 case 0x76018086: /* Intel ICH */ 149 if (udmamode >= 4) { 150 int32_t mask48, new48; 151 int16_t word54; 152 153 word54 = pci_read_config(parent, 0x54, 2); 154 if (word54 & (0x10 << devno)) { 155 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 156 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 157 if (bootverbose) 158 ata_printf(scp, device, "%s setting UDMA4 on Intel chip\n", 159 (error) ? "failed" : "success"); 160 if (!error) { 161 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 162 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 163 pci_write_config(parent, 0x48, 164 (pci_read_config(parent, 0x48, 4) & 165 ~mask48) | new48, 4); 166 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 167 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 168 return; 169 } 170 } 171 } 172 /* make sure eventual ATA66 mode from the BIOS is disabled */ 173 pci_write_config(parent, 0x54, 174 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 175 /* FALLTHROUGH */ 176 177 case 0x71118086: /* Intel PIIX4 */ 178 case 0x84CA8086: /* Intel PIIX4 */ 179 case 0x71998086: /* Intel PIIX4e */ 180 case 0x24218086: /* Intel ICH0 */ 181 if (udmamode >= 2) { 182 int32_t mask48, new48; 183 184 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 185 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 186 if (bootverbose) 187 ata_printf(scp, device, "%s setting UDMA2 on Intel chip\n", 188 (error) ? "failed" : "success"); 189 if (!error) { 190 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 191 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 192 pci_write_config(parent, 0x48, 193 (pci_read_config(parent, 0x48, 4) & 194 ~mask48) | new48, 4); 195 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 196 return; 197 } 198 } 199 /* make sure eventual ATA33 mode from the BIOS is disabled */ 200 pci_write_config(parent, 0x48, 201 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 202 /* FALLTHROUGH */ 203 204 case 0x70108086: /* Intel PIIX3 */ 205 if (wdmamode >= 2 && apiomode >= 4) { 206 int32_t mask40, new40, mask44, new44; 207 208 /* if SITRE not set doit for both channels */ 209 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 210 new40 = pci_read_config(parent, 0x40, 4); 211 new44 = pci_read_config(parent, 0x44, 4); 212 if (!(new40 & 0x00004000)) { 213 new44 &= ~0x0000000f; 214 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 215 } 216 if (!(new40 & 0x40000000)) { 217 new44 &= ~0x000000f0; 218 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 219 } 220 new40 |= 0x40004000; 221 pci_write_config(parent, 0x40, new40, 4); 222 pci_write_config(parent, 0x44, new44, 4); 223 } 224 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 225 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 226 if (bootverbose) 227 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n", 228 (error) ? "failed" : "success"); 229 if (!error) { 230 if (device == ATA_MASTER) { 231 mask40 = 0x0000330f; 232 new40 = 0x00002307; 233 mask44 = 0; 234 new44 = 0; 235 } 236 else { 237 mask40 = 0x000000f0; 238 new40 = 0x00000070; 239 mask44 = 0x0000000f; 240 new44 = 0x0000000b; 241 } 242 if (scp->channel) { 243 mask40 <<= 16; 244 new40 <<= 16; 245 mask44 <<= 4; 246 new44 <<= 4; 247 } 248 pci_write_config(parent, 0x40, 249 (pci_read_config(parent, 0x40, 4) & ~mask40)| 250 new40, 4); 251 pci_write_config(parent, 0x44, 252 (pci_read_config(parent, 0x44, 4) & ~mask44)| 253 new44, 4); 254 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 255 return; 256 } 257 } 258 /* we could set PIO mode timings, but we assume the BIOS did that */ 259 break; 260 261 case 0x12308086: /* Intel PIIX */ 262 if (wdmamode >= 2 && apiomode >= 4) { 263 int32_t word40; 264 265 word40 = pci_read_config(parent, 0x40, 4); 266 word40 >>= scp->channel * 16; 267 268 /* Check for timing config usable for DMA on controller */ 269 if (!((word40 & 0x3300) == 0x2300 && 270 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 271 break; 272 273 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 274 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 275 if (bootverbose) 276 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n", 277 (error) ? "failed" : "success"); 278 if (!error) { 279 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 280 return; 281 } 282 } 283 break; 284 285 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 286 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 287 if (pci_get_revid(parent) < 0xc2 && 288 scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 289 ata_printf(scp, device, 290 "Aladdin: two atapi devices on this channel, no DMA\n"); 291 break; 292 } 293 if (udmamode >= 5 && pci_get_revid(parent) >= 0xc4) { 294 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 295 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 296 if (bootverbose) 297 ata_printf(scp, device, "%s setting UDMA5 on Acer chip\n", 298 (error) ? "failed" : "success"); 299 if (!error) { 300 int32_t word54 = pci_read_config(parent, 0x54, 4); 301 302 pci_write_config(parent, 0x4b, 303 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 304 word54 &= ~(0x000f000f << (devno << 2)); 305 word54 |= (0x000f0005 << (devno << 2)); 306 pci_write_config(parent, 0x54, word54, 4); 307 pci_write_config(parent, 0x53, 308 pci_read_config(parent, 0x53, 1) | 0x03, 1); 309 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 310 return; 311 } 312 } 313 if (udmamode >= 4 && pci_get_revid(parent) >= 0xc2) { 314 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 315 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 316 if (bootverbose) 317 ata_printf(scp, device, "%s setting UDMA4 on Acer chip\n", 318 (error) ? "failed" : "success"); 319 if (!error) { 320 int32_t word54 = pci_read_config(parent, 0x54, 4); 321 322 pci_write_config(parent, 0x4b, 323 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 324 word54 &= ~(0x000f000f << (devno << 2)); 325 word54 |= (0x00080005 << (devno << 2)); 326 pci_write_config(parent, 0x54, word54, 4); 327 pci_write_config(parent, 0x53, 328 pci_read_config(parent, 0x53, 1) | 0x03, 1); 329 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 330 return; 331 } 332 } 333 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 334 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 335 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 336 if (bootverbose) 337 ata_printf(scp, device, "%s setting UDMA2 on Acer chip\n", 338 (error) ? "failed" : "success"); 339 if (!error) { 340 int32_t word54 = pci_read_config(parent, 0x54, 4); 341 342 word54 &= ~(0x000f000f << (devno << 2)); 343 word54 |= (0x000a0005 << (devno << 2)); 344 pci_write_config(parent, 0x54, word54, 4); 345 pci_write_config(parent, 0x53, 346 pci_read_config(parent, 0x53, 1) | 0x03, 1); 347 scp->flags |= ATA_ATAPI_DMA_RO; 348 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 349 return; 350 } 351 } 352 353 /* make sure eventual UDMA mode from the BIOS is disabled */ 354 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 355 ~(0x0008 << (devno << 2)), 2); 356 357 if (wdmamode >= 2 && apiomode >= 4) { 358 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 359 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 360 if (bootverbose) 361 ata_printf(scp, device, "%s setting WDMA2 on Acer chip\n", 362 (error) ? "failed" : "success"); 363 if (!error) { 364 pci_write_config(parent, 0x53, 365 pci_read_config(parent, 0x53, 1) | 0x03, 1); 366 scp->flags |= ATA_ATAPI_DMA_RO; 367 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 368 return; 369 } 370 } 371 pci_write_config(parent, 0x53, 372 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 373 /* we could set PIO mode timings, but we assume the BIOS did that */ 374 break; 375 376 case 0x74111022: /* AMD 766 */ 377 if (udmamode >= 5) { 378 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 379 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 380 if (bootverbose) 381 ata_printf(scp, device, "%s setting UDMA5 on AMD chip\n", 382 (error) ? "failed" : "success"); 383 if (!error) { 384 pci_write_config(parent, 0x53 - devno, 0xc6, 1); 385 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 386 return; 387 } 388 } 389 /* FALLTHROUGH */ 390 391 case 0x74091022: /* AMD 756 */ 392 if (udmamode >= 4) { 393 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 394 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 395 if (bootverbose) 396 ata_printf(scp, device, "%s setting UDMA4 on AMD chip\n", 397 (error) ? "failed" : "success"); 398 if (!error) { 399 pci_write_config(parent, 0x53 - devno, 0xc5, 1); 400 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 401 return; 402 } 403 } 404 goto via_82c586; 405 406 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 407 if (ata_find_dev(parent, 0x06861106, 0x40) || 408 ata_find_dev(parent, 0x82311106, 0) || 409 ata_find_dev(parent, 0x30741106, 0)) { /* 82C686b */ 410 if (udmamode >= 5) { 411 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 412 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 413 if (bootverbose) 414 ata_printf(scp, device, "%s setting UDMA5 on VIA chip\n", 415 (error) ? "failed" : "success"); 416 if (!error) { 417 pci_write_config(parent, 0x53 - devno, 0xf0, 1); 418 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 419 return; 420 } 421 } 422 if (udmamode >= 4) { 423 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 424 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 425 if (bootverbose) 426 ata_printf(scp, device, "%s setting UDMA4 on VIA chip\n", 427 (error) ? "failed" : "success"); 428 if (!error) { 429 pci_write_config(parent, 0x53 - devno, 0xf1, 1); 430 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 431 return; 432 } 433 } 434 if (udmamode >= 2) { 435 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 436 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 437 if (bootverbose) 438 ata_printf(scp, device, "%s setting UDMA2 on VIA chip\n", 439 (error) ? "failed" : "success"); 440 if (!error) { 441 pci_write_config(parent, 0x53 - devno, 0xf4, 1); 442 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 443 return; 444 } 445 } 446 } 447 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 448 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 449 if (udmamode >= 4) { 450 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 451 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 452 if (bootverbose) 453 ata_printf(scp, device, "%s setting UDMA4 on VIA chip\n", 454 (error) ? "failed" : "success"); 455 if (!error) { 456 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 457 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 458 return; 459 } 460 } 461 if (udmamode >= 2) { 462 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 463 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 464 if (bootverbose) 465 ata_printf(scp, device, "%s setting UDMA2 on VIA chip\n", 466 (error) ? "failed" : "success"); 467 if (!error) { 468 pci_write_config(parent, 0x53 - devno, 0xea, 1); 469 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 470 return; 471 } 472 } 473 } 474 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 475 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 476 via_82c586: 477 if (udmamode >= 2) { 478 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 479 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 480 if (bootverbose) 481 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 482 (error) ? "failed" : "success", 483 ((scp->chiptype == 0x74091022) || 484 (scp->chiptype == 0x74111022)) ? "AMD" : "VIA"); 485 if (!error) { 486 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 487 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 488 return; 489 } 490 } 491 } 492 if (wdmamode >= 2 && apiomode >= 4) { 493 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 494 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 495 if (bootverbose) 496 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 497 (error) ? "failed" : "success", 498 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 499 if (!error) { 500 pci_write_config(parent, 0x53 - devno, 0x0b, 1); 501 pci_write_config(parent, 0x4b - devno, 0x31, 1); 502 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 503 return; 504 } 505 } 506 /* we could set PIO mode timings, but we assume the BIOS did that */ 507 break; 508 509 case 0x55131039: /* SiS 5591 */ 510 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */ 511 ata_find_dev(parent, 0x06331039, 0x00) || /* SiS 633 */ 512 ata_find_dev(parent, 0x06351039, 0x00) || /* SiS 635 */ 513 ata_find_dev(parent, 0x06401039, 0x00) || /* SiS 640 */ 514 ata_find_dev(parent, 0x06451039, 0x00) || /* SiS 645 */ 515 ata_find_dev(parent, 0x06501039, 0x00) || /* SiS 650 */ 516 ata_find_dev(parent, 0x07301039, 0x00) || /* SiS 730 */ 517 ata_find_dev(parent, 0x07331039, 0x00) || /* SiS 733 */ 518 ata_find_dev(parent, 0x07351039, 0x00) || /* SiS 735 */ 519 ata_find_dev(parent, 0x07401039, 0x00) || /* SiS 740 */ 520 ata_find_dev(parent, 0x07451039, 0x00) || /* SiS 745 */ 521 ata_find_dev(parent, 0x07501039, 0x00)) { /* SiS 750 */ 522 int8_t reg = 0x40 + (devno << 1); 523 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 524 525 if (udmamode >= 5) { 526 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 527 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 528 if (bootverbose) 529 ata_printf(scp, device, "%s setting UDMA5 on SiS chip\n", 530 (error) ? "failed" : "success"); 531 if (!error) { 532 pci_write_config(parent, reg, val | 0x8000, 2); 533 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 534 return; 535 } 536 } 537 if (udmamode >= 4) { 538 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 539 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 540 if (bootverbose) 541 ata_printf(scp, device, "%s setting UDMA4 on SiS chip\n", 542 (error) ? "failed" : "success"); 543 if (!error) { 544 pci_write_config(parent, reg, val | 0x9000, 2); 545 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 546 return; 547 } 548 } 549 if (udmamode >= 2) { 550 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 551 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 552 if (bootverbose) 553 ata_printf(scp, device, "%s setting UDMA2 on SiS chip\n", 554 (error) ? "failed" : "success"); 555 if (!error) { 556 pci_write_config(parent, reg, val | 0xb000, 2); 557 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 558 return; 559 } 560 } 561 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */ 562 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */ 563 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */ 564 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */ 565 int8_t reg = 0x40 + (devno << 1); 566 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 567 568 if (udmamode >= 4) { 569 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 570 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 571 if (bootverbose) 572 ata_printf(scp, device, "%s setting UDMA4 on SiS chip\n", 573 (error) ? "failed" : "success"); 574 if (!error) { 575 pci_write_config(parent, reg, val | 0x9000, 2); 576 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 577 return; 578 } 579 } 580 if (udmamode >= 2) { 581 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 582 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 583 if (bootverbose) 584 ata_printf(scp, device, "%s setting UDMA2 on SiS chip\n", 585 (error) ? "failed" : "success"); 586 if (!error) { 587 pci_write_config(parent, reg, val | 0xa000, 2); 588 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 589 return; 590 } 591 } 592 } else if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 593 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 594 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 595 if (bootverbose) 596 ata_printf(scp, device, "%s setting UDMA2 on SiS chip\n", 597 (error) ? "failed" : "success"); 598 if (!error) { 599 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 600 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 601 return; 602 } 603 } 604 if (wdmamode >=2 && apiomode >= 4) { 605 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 606 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 607 if (bootverbose) 608 ata_printf(scp, device, "%s setting WDMA2 on SiS chip\n", 609 (error) ? "failed" : "success"); 610 if (!error) { 611 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 612 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 613 return; 614 } 615 } 616 /* we could set PIO mode timings, but we assume the BIOS did that */ 617 break; 618 619 case 0x06491095: /* CMD 649 ATA100 controller */ 620 if (udmamode >= 5) { 621 u_int8_t umode; 622 623 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 624 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 625 if (bootverbose) 626 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 627 (error) ? "failed" : "success"); 628 if (!error) { 629 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 630 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 631 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 632 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 633 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 634 return; 635 } 636 } 637 /* FALLTHROUGH */ 638 639 case 0x06481095: /* CMD 648 ATA66 controller */ 640 if (udmamode >= 4) { 641 u_int8_t umode; 642 643 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 644 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 645 if (bootverbose) 646 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 647 (error) ? "failed" : "success"); 648 if (!error) { 649 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 650 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 651 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 652 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 653 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 654 return; 655 } 656 } 657 if (udmamode >= 2) { 658 u_int8_t umode; 659 660 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 661 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 662 if (bootverbose) 663 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 664 (error) ? "failed" : "success"); 665 if (!error) { 666 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 667 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 668 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 669 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 670 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 671 return; 672 } 673 } 674 /* make sure eventual UDMA mode from the BIOS is disabled */ 675 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 676 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 677 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 678 /* FALLTHROUGH */ 679 680 case 0x06461095: /* CMD 646 ATA controller */ 681 if (wdmamode >= 2 && apiomode >= 4) { 682 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 683 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 684 if (bootverbose) 685 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 686 error ? "failed" : "success"); 687 if (!error) { 688 int32_t offset = (devno < 3) ? (devno << 1) : 7; 689 690 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 691 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 692 return; 693 } 694 } 695 /* we could set PIO mode timings, but we assume the BIOS did that */ 696 break; 697 698 case 0xc6931080: /* Cypress 82c693 ATA controller */ 699 if (wdmamode >= 2 && apiomode >= 4) { 700 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 701 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 702 if (bootverbose) 703 ata_printf(scp, device, "%s setting WDMA2 on Cypress chip\n", 704 error ? "failed" : "success"); 705 if (!error) { 706 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 707 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 708 return; 709 } 710 } 711 /* we could set PIO mode timings, but we assume the BIOS did that */ 712 break; 713 714 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 715 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 716 if (udmamode >= 2) { 717 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 718 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 719 if (bootverbose) 720 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 721 (error) ? "failed" : "success"); 722 if (!error) { 723 cyrix_timing(scp, devno, ATA_UDMA2); 724 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 725 return; 726 } 727 } 728 if (wdmamode >= 2 && apiomode >= 4) { 729 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 730 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 731 if (bootverbose) 732 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 733 (error) ? "failed" : "success"); 734 if (!error) { 735 cyrix_timing(scp, devno, ATA_WDMA2); 736 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 737 return; 738 } 739 } 740 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 741 ATA_PIO0 + apiomode, ATA_C_F_SETXFER, 742 ATA_WAIT_READY); 743 if (bootverbose) 744 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 745 (error) ? "failed" : "success", 746 ata_mode2str(ATA_PIO0 + apiomode)); 747 cyrix_timing(scp, devno, ATA_PIO0 + apiomode); 748 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 749 return; 750 751 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 752 if (udmamode >= 2) { 753 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 754 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 755 if (bootverbose) 756 ata_printf(scp, device, 757 "%s setting UDMA2 on ServerWorks chip\n", 758 (error) ? "failed" : "success"); 759 if (!error) { 760 u_int16_t reg56; 761 762 pci_write_config(parent, 0x54, 763 pci_read_config(parent, 0x54, 1) | 764 (0x01 << devno), 1); 765 reg56 = pci_read_config(parent, 0x56, 2); 766 reg56 &= ~(0xf << (devno * 4)); 767 reg56 |= (0x2 << (devno * 4)); 768 pci_write_config(parent, 0x56, reg56, 2); 769 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 770 return; 771 } 772 } 773 if (wdmamode >= 2 && apiomode >= 4) { 774 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 775 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 776 if (bootverbose) 777 ata_printf(scp, device, 778 "%s setting WDMA2 on ServerWorks chip\n", 779 (error) ? "failed" : "success"); 780 if (!error) { 781 int offset = (scp->channel * 2) + (device == ATA_MASTER); 782 int word44 = pci_read_config(parent, 0x44, 4); 783 784 pci_write_config(parent, 0x54, 785 pci_read_config(parent, 0x54, 1) & 786 ~(0x01 << devno), 1); 787 word44 &= ~(0xff << (offset << 8)); 788 word44 |= (0x20 << (offset << 8)); 789 pci_write_config(parent, 0x44, 0x20, 4); 790 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 791 return; 792 } 793 } 794 /* we could set PIO mode timings, but we assume the BIOS did that */ 795 break; 796 797 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 798 case 0x6268105a: /* Promise TX2 ATA100 controllers */ 799 case 0x4d69105a: /* Promise TX2 ATA133 controllers */ 800 ATA_OUTB(scp->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 801 if (udmamode >= 4 && !(ATA_INB(scp->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 802 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 803 ATA_UDMA + udmamode, ATA_C_F_SETXFER, 804 ATA_WAIT_READY); 805 if (bootverbose) 806 ata_printf(scp, device, "%s setting %s on Promise chip\n", 807 (error) ? "failed" : "success", 808 ata_mode2str(ATA_UDMA + udmamode)); 809 if (!error) { 810 scp->mode[ATA_DEV(device)] = ATA_UDMA + udmamode; 811 return; 812 } 813 } 814 if (udmamode >= 2) { 815 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 816 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 817 if (bootverbose) 818 ata_printf(scp, device, "%s setting %s on Promise chip\n", 819 (error) ? "failed" : "success", "UDMA2"); 820 if (!error) { 821 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 822 return; 823 } 824 } 825 if (wdmamode >= 2 && apiomode >= 4) { 826 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 827 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 828 if (bootverbose) 829 ata_printf(scp, device, "%s setting %s on Promise chip\n", 830 (error) ? "failed" : "success", "WDMA2"); 831 if (!error) { 832 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 833 return; 834 } 835 } 836 break; 837 838 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 839 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 840 if (!ATAPI_DEVICE(scp, device) && udmamode >= 5 && 841 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 842 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 843 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 844 if (bootverbose) 845 ata_printf(scp, device, "%s setting UDMA5 on Promise chip\n", 846 (error) ? "failed" : "success"); 847 if (!error) { 848 promise_timing(scp, devno, ATA_UDMA5); 849 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 850 return; 851 } 852 } 853 /* FALLTHROUGH */ 854 855 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 856 if (!ATAPI_DEVICE(scp, device) && udmamode >= 4 && 857 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 858 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 859 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 860 if (bootverbose) 861 ata_printf(scp, device, "%s setting UDMA4 on Promise chip\n", 862 (error) ? "failed" : "success"); 863 if (!error) { 864 promise_timing(scp, devno, ATA_UDMA4); 865 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 866 return; 867 } 868 } 869 /* FALLTHROUGH */ 870 871 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 872 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) { 873 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 874 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 875 if (bootverbose) 876 ata_printf(scp, device, "%s setting UDMA2 on Promise chip\n", 877 (error) ? "failed" : "success"); 878 if (!error) { 879 promise_timing(scp, devno, ATA_UDMA2); 880 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 881 return; 882 } 883 } 884 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) { 885 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 886 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 887 if (bootverbose) 888 ata_printf(scp, device, "%s setting WDMA2 on Promise chip\n", 889 (error) ? "failed" : "success"); 890 if (!error) { 891 promise_timing(scp, devno, ATA_WDMA2); 892 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 893 return; 894 } 895 } 896 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 897 ATA_PIO0 + apiomode, 898 ATA_C_F_SETXFER, ATA_WAIT_READY); 899 if (bootverbose) 900 ata_printf(scp, device, "%s setting PIO%d on Promise chip\n", 901 (error) ? "failed" : "success", 902 (apiomode >= 0) ? apiomode : 0); 903 promise_timing(scp, devno, ATA_PIO0 + apiomode); 904 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 905 return; 906 907 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */ 908 if (!ATAPI_DEVICE(scp, device) && 909 udmamode >= 6 && pci_get_revid(parent) >= 0x05 && 910 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 911 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 912 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 913 if (bootverbose) 914 ata_printf(scp, device, "%s setting UDMA6 on HighPoint chip\n", 915 (error) ? "failed" : "success"); 916 if (!error) { 917 hpt_timing(scp, devno, ATA_UDMA6); 918 scp->mode[ATA_DEV(device)] = ATA_UDMA6; 919 return; 920 } 921 } 922 if (!ATAPI_DEVICE(scp, device) && 923 udmamode >= 5 && pci_get_revid(parent) >= 0x03 && 924 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 925 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 926 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 927 if (bootverbose) 928 ata_printf(scp, device, "%s setting UDMA5 on HighPoint chip\n", 929 (error) ? "failed" : "success"); 930 if (!error) { 931 hpt_timing(scp, devno, ATA_UDMA5); 932 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 933 return; 934 } 935 } 936 if (!ATAPI_DEVICE(scp, device) && udmamode >=4 && 937 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 938 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 939 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 940 if (bootverbose) 941 ata_printf(scp, device, "%s setting UDMA4 on HighPoint chip\n", 942 (error) ? "failed" : "success"); 943 if (!error) { 944 hpt_timing(scp, devno, ATA_UDMA4); 945 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 946 return; 947 } 948 } 949 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) { 950 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 951 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 952 if (bootverbose) 953 ata_printf(scp, device, "%s setting UDMA2 on HighPoint chip\n", 954 (error) ? "failed" : "success"); 955 if (!error) { 956 hpt_timing(scp, devno, ATA_UDMA2); 957 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 958 return; 959 } 960 } 961 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) { 962 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 963 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 964 if (bootverbose) 965 ata_printf(scp, device, "%s setting WDMA2 on HighPoint chip\n", 966 (error) ? "failed" : "success"); 967 if (!error) { 968 hpt_timing(scp, devno, ATA_WDMA2); 969 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 970 return; 971 } 972 } 973 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 974 ATA_PIO0 + apiomode, 975 ATA_C_F_SETXFER, ATA_WAIT_READY); 976 if (bootverbose) 977 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 978 (error) ? "failed" : "success", 979 (apiomode >= 0) ? apiomode : 0); 980 hpt_timing(scp, devno, ATA_PIO0 + apiomode); 981 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 982 return; 983 984 default: /* unknown controller chip */ 985 /* better not try generic DMA on ATAPI devices it almost never works */ 986 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 987 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 988 break; 989 990 /* if controller says its setup for DMA take the easy way out */ 991 /* the downside is we dont know what DMA mode we are in */ 992 if ((udmamode >= 0 || wdmamode > 1) && 993 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 994 ((device==ATA_MASTER) ? 995 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 996 scp->mode[ATA_DEV(device)] = ATA_DMA; 997 return; 998 } 999 1000 /* well, we have no support for this, but try anyways */ 1001 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) { 1002 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 1003 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1004 if (bootverbose) 1005 ata_printf(scp, device, "%s setting WDMA2 on generic chip\n", 1006 (error) ? "failed" : "success"); 1007 if (!error) { 1008 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 1009 return; 1010 } 1011 } 1012 } 1013 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode, 1014 ATA_C_F_SETXFER,ATA_WAIT_READY); 1015 if (bootverbose) 1016 ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 1017 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 1018 if (!error) 1019 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 1020 else { 1021 if (bootverbose) 1022 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 1023 scp->mode[ATA_DEV(device)] = ATA_PIO; 1024 } 1025 } 1026 1027 int 1028 ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 1029 caddr_t data, int32_t count) 1030 { 1031 u_int32_t dma_count, dma_base; 1032 int i = 0; 1033 1034 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 1035 ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 1036 return -1; 1037 } 1038 1039 if (!count) { 1040 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 1041 return -1; 1042 } 1043 1044 dma_base = vtophys(data); 1045 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 1046 data += dma_count; 1047 count -= dma_count; 1048 1049 while (count) { 1050 dmatab[i].base = dma_base; 1051 dmatab[i].count = (dma_count & 0xffff); 1052 i++; 1053 if (i >= ATA_DMA_ENTRIES) { 1054 ata_printf(scp, device, "too many segments in DMA table\n"); 1055 return -1; 1056 } 1057 dma_base = vtophys(data); 1058 dma_count = min(count, PAGE_SIZE); 1059 data += min(count, PAGE_SIZE); 1060 count -= min(count, PAGE_SIZE); 1061 } 1062 dmatab[i].base = dma_base; 1063 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 1064 return 0; 1065 } 1066 1067 void 1068 ata_dmastart(struct ata_softc *scp, int device, 1069 struct ata_dmaentry *dmatab, int dir) 1070 { 1071 scp->flags |= ATA_DMA_ACTIVE; 1072 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab)); 1073 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 1074 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 1075 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) | 1076 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 1077 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 1078 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 1079 } 1080 1081 int 1082 ata_dmadone(struct ata_softc *scp) 1083 { 1084 int error; 1085 1086 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 1087 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 1088 scp->flags &= ~ATA_DMA_ACTIVE; 1089 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT); 1090 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 1091 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 1092 return error & ATA_BMSTAT_MASK; 1093 } 1094 1095 int 1096 ata_dmastatus(struct ata_softc *scp) 1097 { 1098 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 1099 } 1100 1101 static void 1102 cyrix_timing(struct ata_softc *scp, int devno, int mode) 1103 { 1104 u_int32_t reg20 = 0x0000e132; 1105 u_int32_t reg24 = 0x00017771; 1106 1107 switch (mode) { 1108 case ATA_PIO0: reg20 = 0x0000e132; break; 1109 case ATA_PIO1: reg20 = 0x00018121; break; 1110 case ATA_PIO2: reg20 = 0x00024020; break; 1111 case ATA_PIO3: reg20 = 0x00032010; break; 1112 case ATA_PIO4: reg20 = 0x00040010; break; 1113 case ATA_WDMA2: reg24 = 0x00002020; break; 1114 case ATA_UDMA2: reg24 = 0x00911030; break; 1115 } 1116 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20); 1117 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24); 1118 } 1119 1120 static void 1121 promise_timing(struct ata_softc *scp, int devno, int mode) 1122 { 1123 u_int32_t timing = 0; 1124 struct promise_timing { 1125 u_int8_t pa:4; 1126 u_int8_t prefetch:1; 1127 u_int8_t iordy:1; 1128 u_int8_t errdy:1; 1129 u_int8_t syncin:1; 1130 u_int8_t pb:5; 1131 u_int8_t mb:3; 1132 u_int8_t mc:4; 1133 u_int8_t dmaw:1; 1134 u_int8_t dmar:1; 1135 u_int8_t iordyp:1; 1136 u_int8_t dmarqp:1; 1137 u_int8_t reserved:8; 1138 } *t = (struct promise_timing*)&timing; 1139 1140 t->iordy = 1; t->iordyp = 1; 1141 if (mode >= ATA_DMA) { 1142 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1143 } 1144 1145 switch (scp->chiptype) { 1146 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1147 switch (mode) { 1148 default: 1149 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1150 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1151 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1152 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1153 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1154 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1155 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1156 } 1157 break; 1158 1159 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1160 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1161 case 0x0d30105a: /* Promise OEM ATA 100 */ 1162 switch (mode) { 1163 default: 1164 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1165 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1166 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1167 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1168 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1169 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1170 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1171 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1172 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1173 } 1174 break; 1175 } 1176 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 1177 } 1178 1179 static void 1180 hpt_timing(struct ata_softc *scp, int devno, int mode) 1181 { 1182 device_t parent = device_get_parent(scp->dev); 1183 u_int32_t timing; 1184 if (pci_get_revid(parent) >= 0x05) { /* HPT372 */ 1185 switch (mode) { 1186 case ATA_PIO0: timing = 0x0d029d5e; break; 1187 case ATA_PIO1: timing = 0x0d029d26; break; 1188 case ATA_PIO2: timing = 0x0c829ca6; break; 1189 case ATA_PIO3: timing = 0x0c829c84; break; 1190 case ATA_PIO4: timing = 0x0c829c62; break; 1191 case ATA_WDMA2: timing = 0x2c829262; break; 1192 case ATA_UDMA2: timing = 0x1c91dc62; break; 1193 case ATA_UDMA4: timing = 0x1c8ddc62; break; 1194 case ATA_UDMA5: timing = 0x1c6ddc62; break; 1195 case ATA_UDMA6: timing = 0x1c81dc62; break; 1196 default: timing = 0x0d029d5e; 1197 } 1198 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1199 pci_write_config(parent, 0x5b, 0x20, 1); 1200 } 1201 else if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 1202 switch (mode) { 1203 case ATA_PIO0: timing = 0x06914e57; break; 1204 case ATA_PIO1: timing = 0x06914e43; break; 1205 case ATA_PIO2: timing = 0x06514e33; break; 1206 case ATA_PIO3: timing = 0x06514e22; break; 1207 case ATA_PIO4: timing = 0x06514e21; break; 1208 case ATA_WDMA2: timing = 0x26514e21; break; 1209 case ATA_UDMA2: timing = 0x16494e31; break; 1210 case ATA_UDMA4: timing = 0x16454e31; break; 1211 case ATA_UDMA5: timing = 0x16454e31; break; 1212 default: timing = 0x06514e57; 1213 } 1214 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1215 pci_write_config(parent, 0x5b, 0x22, 1); 1216 } 1217 else { /* HPT36[68] */ 1218 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1219 case 0x85: /* 25Mhz */ 1220 switch (mode) { 1221 case ATA_PIO0: timing = 0xc0d08585; break; 1222 case ATA_PIO1: timing = 0xc0d08572; break; 1223 case ATA_PIO2: timing = 0xc0ca8542; break; 1224 case ATA_PIO3: timing = 0xc0ca8532; break; 1225 case ATA_PIO4: timing = 0xc0ca8521; break; 1226 case ATA_WDMA2: timing = 0xa0ca8521; break; 1227 case ATA_UDMA2: timing = 0x90cf8521; break; 1228 case ATA_UDMA4: timing = 0x90c98521; break; 1229 default: timing = 0x01208585; 1230 } 1231 break; 1232 default: 1233 case 0xa7: /* 33MHz */ 1234 switch (mode) { 1235 case ATA_PIO0: timing = 0xc0d0a7aa; break; 1236 case ATA_PIO1: timing = 0xc0d0a7a3; break; 1237 case ATA_PIO2: timing = 0xc0d0a753; break; 1238 case ATA_PIO3: timing = 0xc0c8a742; break; 1239 case ATA_PIO4: timing = 0xc0c8a731; break; 1240 case ATA_WDMA2: timing = 0xa0c8a731; break; 1241 case ATA_UDMA2: timing = 0x90caa731; break; 1242 case ATA_UDMA4: timing = 0x90c9a731; break; 1243 default: timing = 0x0120a7a7; 1244 } 1245 break; 1246 case 0xd9: /* 40Mhz */ 1247 switch (mode) { 1248 case ATA_PIO0: timing = 0xc018d9d9; break; 1249 case ATA_PIO1: timing = 0xc010d9c7; break; 1250 case ATA_PIO2: timing = 0xc010d997; break; 1251 case ATA_PIO3: timing = 0xc010d974; break; 1252 case ATA_PIO4: timing = 0xc008d963; break; 1253 case ATA_WDMA2: timing = 0xa008d943; break; 1254 case ATA_UDMA2: timing = 0x900bd943; break; 1255 case ATA_UDMA4: timing = 0x900fd943; break; 1256 default: timing = 0x0120d9d9; 1257 } 1258 } 1259 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 1260 } 1261 } 1262