1 /*- 2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* ATA register defines */ 32 #define ATA_DATA 0x00 /* data register */ 33 #define ATA_ERROR 0x01 /* (R) error register */ 34 #define ATA_E_NM 0x02 /* no media */ 35 #define ATA_E_ABORT 0x04 /* command aborted */ 36 #define ATA_E_MCR 0x08 /* media change request */ 37 #define ATA_E_IDNF 0x10 /* ID not found */ 38 #define ATA_E_MC 0x20 /* media changed */ 39 #define ATA_E_UNC 0x40 /* uncorrectable data */ 40 #define ATA_E_ICRC 0x80 /* UDMA crc error */ 41 42 #define ATA_FEATURE 0x01 /* (W) feature register */ 43 #define ATA_F_DMA 0x01 /* enable DMA */ 44 #define ATA_F_OVL 0x02 /* enable overlap */ 45 46 #define ATA_COUNT 0x02 /* (W) sector count */ 47 #define ATA_IREASON 0x02 /* (R) interrupt reason */ 48 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 49 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 50 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 51 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 52 53 #define ATA_SECTOR 0x03 /* sector # */ 54 #define ATA_CYL_LSB 0x04 /* cylinder# LSB */ 55 #define ATA_CYL_MSB 0x05 /* cylinder# MSB */ 56 #define ATA_DRIVE 0x06 /* Sector/Drive/Head register */ 57 #define ATA_D_LBA 0x40 /* use LBA adressing */ 58 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 59 60 #define ATA_CMD 0x07 /* command register */ 61 #define ATA_C_NOP 0x00 /* NOP command */ 62 #define ATA_C_F_FLUSHQUEUE 0x00 /* flush queued cmd's */ 63 #define ATA_C_F_AUTOPOLL 0x01 /* start autopoll function */ 64 #define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */ 65 #define ATA_C_READ 0x20 /* read command */ 66 #define ATA_C_WRITE 0x30 /* write command */ 67 #define ATA_C_PACKET_CMD 0xa0 /* packet command */ 68 #define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/ 69 #define ATA_C_SERVICE 0xa2 /* service command */ 70 #define ATA_C_READ_MUL 0xc4 /* read multi command */ 71 #define ATA_C_WRITE_MUL 0xc5 /* write multi command */ 72 #define ATA_C_SET_MULTI 0xc6 /* set multi size command */ 73 #define ATA_C_READ_DMA_QUEUED 0xc7 /* read w/DMA QUEUED command */ 74 #define ATA_C_READ_DMA 0xc8 /* read w/DMA command */ 75 #define ATA_C_WRITE_DMA 0xca /* write w/DMA command */ 76 #define ATA_C_WRITE_DMA_QUEUED 0xcc /* write w/DMA QUEUED command */ 77 #define ATA_C_FLUSHCACHE 0xe7 /* flush cache to disk */ 78 #define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */ 79 #define ATA_C_SETFEATURES 0xef /* features command */ 80 #define ATA_C_F_SETXFER 0x03 /* set transfer mode */ 81 #define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */ 82 #define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */ 83 #define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */ 84 #define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */ 85 #define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */ 86 #define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */ 87 #define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */ 88 #define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */ 89 90 #define ATA_STATUS 0x07 /* status register */ 91 #define ATA_S_ERROR 0x01 /* error */ 92 #define ATA_S_INDEX 0x02 /* index */ 93 #define ATA_S_CORR 0x04 /* data corrected */ 94 #define ATA_S_DRQ 0x08 /* data request */ 95 #define ATA_S_DSC 0x10 /* drive seek completed */ 96 #define ATA_S_SERVICE 0x10 /* drive needs service */ 97 #define ATA_S_DWF 0x20 /* drive write fault */ 98 #define ATA_S_DMA 0x20 /* DMA ready */ 99 #define ATA_S_READY 0x40 /* drive ready */ 100 #define ATA_S_BUSY 0x80 /* busy */ 101 102 #define ATA_ALTSTAT 0x00 /* alternate status register */ 103 #define ATA_ALTOFFSET 0x206 /* alternate registers offset */ 104 #define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */ 105 #define ATA_A_IDS 0x02 /* disable interrupts */ 106 #define ATA_A_RESET 0x04 /* RESET controller */ 107 #define ATA_A_4BIT 0x08 /* 4 head bits */ 108 109 /* misc defines */ 110 #define ATA_PRIMARY 0x1f0 111 #define ATA_SECONDARY 0x170 112 #define ATA_MASTER 0x00 113 #define ATA_SLAVE 0x10 114 #define ATA_IOSIZE 0x08 115 #define ATA_ALTIOSIZE 0x01 116 #define ATA_BMIOSIZE 0x08 117 #define ATA_OP_FINISHED 0x00 118 #define ATA_OP_CONTINUES 0x01 119 #define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1) 120 #define ATA_PARAM(scp, device) (scp->dev_param[ATA_DEV(device)]) 121 122 /* busmaster DMA related defines */ 123 #define ATA_DMA_ENTRIES 256 124 #define ATA_DMA_EOT 0x80000000 125 126 #define ATA_BMCMD_PORT 0x00 127 #define ATA_BMCMD_START_STOP 0x01 128 #define ATA_BMCMD_WRITE_READ 0x08 129 130 #define ATA_BMSTAT_PORT 0x02 131 #define ATA_BMSTAT_ACTIVE 0x01 132 #define ATA_BMSTAT_ERROR 0x02 133 #define ATA_BMSTAT_INTERRUPT 0x04 134 #define ATA_BMSTAT_MASK 0x07 135 #define ATA_BMSTAT_DMA_MASTER 0x20 136 #define ATA_BMSTAT_DMA_SLAVE 0x40 137 #define ATA_BMSTAT_DMA_SIMPLEX 0x80 138 139 #define ATA_BMDTP_PORT 0x04 140 141 /* structure for holding DMA address data */ 142 struct ata_dmaentry { 143 u_int32_t base; 144 u_int32_t count; 145 }; 146 147 /* ATA/ATAPI device parameter information */ 148 struct ata_params { 149 u_int8_t cmdsize :2; /* packet command size */ 150 #define ATAPI_PSIZE_12 0 /* 12 bytes */ 151 #define ATAPI_PSIZE_16 1 /* 16 bytes */ 152 153 u_int8_t :3; 154 u_int8_t drqtype :2; /* DRQ type */ 155 #define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */ 156 #define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */ 157 #define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */ 158 159 u_int8_t removable :1; /* device is removable */ 160 u_int8_t device_type :5; /* device type */ 161 #define ATAPI_TYPE_DIRECT 0 /* disk/floppy */ 162 #define ATAPI_TYPE_TAPE 1 /* streaming tape */ 163 #define ATAPI_TYPE_CDROM 5 /* CD-ROM device */ 164 #define ATAPI_TYPE_OPTICAL 7 /* optical disk */ 165 166 u_int8_t :1; 167 u_int8_t proto :2; /* command protocol */ 168 #define ATAPI_PROTO_ATAPI 2 169 170 u_int16_t cylinders; /* number of cylinders */ 171 u_int16_t reserved2; 172 u_int16_t heads; /* # heads */ 173 u_int16_t unfbytespertrk; /* # unformatted bytes/track */ 174 u_int16_t unfbytes; /* # unformatted bytes/sector */ 175 u_int16_t sectors; /* # sectors/track */ 176 u_int16_t vendorunique0[3]; 177 u_int8_t serial[20]; /* serial number */ 178 u_int16_t buffertype; /* buffer type */ 179 #define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */ 180 #define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */ 181 #define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */ 182 183 u_int16_t buffersize; /* buf size, 512-byte units */ 184 u_int16_t necc; /* ecc bytes appended */ 185 u_int8_t revision[8]; /* firmware revision */ 186 u_int8_t model[40]; /* model name */ 187 u_int8_t nsecperint; /* sectors per interrupt */ 188 u_int8_t vendorunique1; 189 u_int16_t usedmovsd; /* double word read/write? */ 190 191 u_int8_t vendorcap; /* vendor capabilities */ 192 u_int8_t dmaflag :1; /* DMA supported - always 1 */ 193 u_int8_t lbaflag :1; /* LBA supported - always 1 */ 194 u_int8_t iordydis :1; /* IORDY may be disabled */ 195 u_int8_t iordyflag :1; /* IORDY supported */ 196 u_int8_t softreset :1; /* needs softreset when busy */ 197 u_int8_t stdby_ovlap :1; /* standby/overlap supported */ 198 u_int8_t queueing :1; /* supports queuing overlap */ 199 u_int8_t idmaflag :1; /* interleaved DMA supported */ 200 u_int16_t capvalidate; /* validation for above */ 201 202 u_int8_t vendorunique3; 203 u_int8_t opiomode; /* PIO modes 0-2 */ 204 u_int8_t vendorunique4; 205 u_int8_t odmamode; /* old DMA modes, not ATA-3 */ 206 207 u_int16_t atavalid; /* fields valid */ 208 #define ATA_FLAG_54_58 1 /* words 54-58 valid */ 209 #define ATA_FLAG_64_70 2 /* words 64-70 valid */ 210 #define ATA_FLAG_88 4 /* word 88 valid */ 211 212 u_int16_t currcyls; 213 u_int16_t currheads; 214 u_int16_t currsectors; 215 u_int16_t currsize0; 216 u_int16_t currsize1; 217 u_int8_t currmultsect; 218 u_int8_t multsectvalid; 219 u_int32_t lbasize; 220 221 u_int16_t sdmamodes; /* singleword DMA modes */ 222 u_int16_t wdmamodes; /* multiword DMA modes */ 223 u_int16_t apiomodes; /* advanced PIO modes */ 224 225 u_int16_t mwdmamin; /* min. M/W DMA time/word ns */ 226 u_int16_t mwdmarec; /* rec. M/W DMA time ns */ 227 u_int16_t pioblind; /* min. PIO cycle w/o flow */ 228 u_int16_t pioiordy; /* min. PIO cycle IORDY flow */ 229 230 u_int16_t reserved69; 231 u_int16_t reserved70; 232 u_int16_t rlsovlap; /* rel time (us) for overlap */ 233 u_int16_t rlsservice; /* rel time (us) for service */ 234 u_int16_t reserved73; 235 u_int16_t reserved74; 236 u_int16_t queuelen:5; 237 u_int16_t :11; 238 u_int16_t reserved76; 239 u_int16_t reserved77; 240 u_int16_t reserved78; 241 u_int16_t reserved79; 242 u_int16_t versmajor; 243 u_int16_t versminor; 244 u_int16_t featsupp1; /* 82 */ 245 u_int16_t supmicrocode:1; 246 u_int16_t supqueued:1; 247 u_int16_t supcfa:1; 248 u_int16_t supapm:1; 249 u_int16_t suprmsn:1; 250 u_int16_t :11; 251 u_int16_t featsupp3; /* 84 */ 252 u_int16_t featenab1; /* 85 */ 253 u_int16_t enabmicrocode:1; 254 u_int16_t enabqueued:1; 255 u_int16_t enabcfa:1; 256 u_int16_t enabapm:1; 257 u_int16_t enabrmsn:1; 258 u_int16_t :11; 259 u_int16_t featenab3; /* 87 */ 260 u_int16_t udmamodes; /* UltraDMA modes */ 261 u_int16_t erasetime; 262 u_int16_t enherasetime; 263 u_int16_t apmlevel; 264 u_int16_t masterpasswdrev; 265 u_int16_t masterhwres :8; 266 u_int16_t slavehwres :5; 267 u_int16_t cblid :1; 268 u_int16_t reserved93_1415 :2; 269 u_int16_t reserved94[32]; 270 u_int16_t rmvstat; 271 u_int16_t securstat; 272 u_int16_t reserved129[30]; 273 u_int16_t cfapwrmode; 274 u_int16_t reserved161[84]; 275 u_int16_t integrity; 276 }; 277 278 /* structure describing an ATA device */ 279 struct ata_softc { 280 struct device *dev; /* device handle */ 281 int channel; /* channel on this controller */ 282 struct resource *r_io; /* io addr resource handle */ 283 struct resource *r_altio; /* altio addr resource handle */ 284 struct resource *r_bmio; /* bmio addr resource handle */ 285 struct resource *r_irq; /* interrupt of this channel */ 286 void *ih; /* interrupt handle */ 287 u_int32_t chiptype; /* pciid of controller chip */ 288 u_int32_t alignment; /* dma engine min alignment */ 289 struct ata_params *dev_param[2]; /* ptr to devices params */ 290 void *dev_softc[2]; /* ptr to devices softc's */ 291 int mode[2]; /* transfer mode for devices */ 292 #define ATA_PIO 0x00 293 #define ATA_PIO0 0x08 294 #define ATA_PIO1 0x09 295 #define ATA_PIO2 0x0a 296 #define ATA_PIO3 0x0b 297 #define ATA_PIO4 0x0c 298 #define ATA_DMA 0x10 299 #define ATA_WDMA2 0x22 300 #define ATA_UDMA2 0x42 301 #define ATA_UDMA4 0x44 302 #define ATA_UDMA5 0x45 303 304 int flags; /* controller flags */ 305 #define ATA_DMA_ACTIVE 0x01 306 #define ATA_ATAPI_DMA_RO 0x02 307 #define ATA_USE_16BIT 0x04 308 #define ATA_NO_SLAVE 0x08 309 #define ATA_ATTACHED 0x10 310 #define ATA_QUEUED 0x20 311 312 int devices; /* what is present */ 313 #define ATA_ATA_MASTER 0x01 314 #define ATA_ATA_SLAVE 0x02 315 #define ATA_ATAPI_MASTER 0x04 316 #define ATA_ATAPI_SLAVE 0x08 317 318 u_int8_t status; /* last controller status */ 319 u_int8_t error; /* last controller error */ 320 int active; /* active processing request */ 321 #define ATA_IDLE 0x0 322 #define ATA_IMMEDIATE 0x1 323 #define ATA_WAIT_INTR 0x2 324 #define ATA_WAIT_READY 0x3 325 #define ATA_ACTIVE 0x4 326 #define ATA_ACTIVE_ATA 0x5 327 #define ATA_ACTIVE_ATAPI 0x6 328 #define ATA_REINITING 0x7 329 330 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */ 331 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */ 332 void *running; /* currently running request */ 333 }; 334 335 /* externs */ 336 extern devclass_t ata_devclass; 337 338 /* public prototypes */ 339 void ata_start(struct ata_softc *); 340 void ata_reset(struct ata_softc *, int *); 341 int ata_reinit(struct ata_softc *); 342 int ata_wait(struct ata_softc *, int, u_int8_t); 343 int ata_command(struct ata_softc *, int, u_int8_t, u_int16_t, u_int8_t, u_int8_t, u_int8_t, u_int8_t, int); 344 int ata_printf(struct ata_softc *, int, const char *, ...) __printflike(3, 4); 345 int ata_get_lun(u_int32_t *); 346 int ata_test_lun(u_int32_t *, int); 347 void ata_free_lun(u_int32_t *, int); 348 char *ata_mode2str(int); 349 int ata_pio2mode(int); 350 int ata_pmode(struct ata_params *); 351 int ata_wmode(struct ata_params *); 352 int ata_umode(struct ata_params *); 353 #if NPCI > 0 354 int ata_find_dev(device_t, u_int32_t, u_int32_t); 355 #endif 356 357 void *ata_dmaalloc(struct ata_softc *, int); 358 void ata_dmainit(struct ata_softc *, int, int, int, int); 359 int ata_dmasetup(struct ata_softc *, int, struct ata_dmaentry *, caddr_t, int); 360 void ata_dmastart(struct ata_softc *, int, struct ata_dmaentry *, int); 361 int ata_dmastatus(struct ata_softc *); 362 int ata_dmadone(struct ata_softc *); 363 364 #define ATA_INB(res, offset) \ 365 bus_space_read_1(rman_get_bustag((res)), \ 366 rman_get_bushandle((res)), (offset)) 367 #define ATA_INW(res, offset) \ 368 bus_space_read_2(rman_get_bustag((res)), \ 369 rman_get_bushandle((res)), (offset)) 370 #define ATA_INL(res, offset) \ 371 bus_space_read_4(rman_get_bustag((res)), \ 372 rman_get_bushandle((res)), (offset)) 373 #define ATA_INSW(res, offset, addr, count) \ 374 bus_space_read_multi_2(rman_get_bustag((res)), \ 375 rman_get_bushandle((res)), \ 376 (offset), (addr), (count)) 377 #define ATA_INSL(res, offset, addr, count) \ 378 bus_space_read_multi_4(rman_get_bustag((res)), \ 379 rman_get_bushandle((res)), \ 380 (offset), (addr), (count)) 381 #define ATA_OUTB(res, offset, value) \ 382 bus_space_write_1(rman_get_bustag((res)), \ 383 rman_get_bushandle((res)), (offset), (value)) 384 #define ATA_OUTW(res, offset, value) \ 385 bus_space_write_2(rman_get_bustag((res)), \ 386 rman_get_bushandle((res)), (offset), (value)) 387 #define ATA_OUTL(res, offset, value) \ 388 bus_space_write_4(rman_get_bustag((res)), \ 389 rman_get_bushandle((res)), (offset), (value)) 390 #define ATA_OUTSW(res, offset, addr, count) \ 391 bus_space_write_multi_2(rman_get_bustag((res)), \ 392 rman_get_bushandle((res)), \ 393 (offset), (addr), (count)) 394 #define ATA_OUTSL(res, offset, addr, count) \ 395 bus_space_write_multi_4(rman_get_bustag((res)), \ 396 rman_get_bushandle((res)), \ 397 (offset), (addr), (count)) 398