1 /*- 2 * Copyright (c) 1998 - 2005 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* ATA register defines */ 32 #define ATA_DATA 0 /* (RW) data */ 33 34 #define ATA_FEATURE 1 /* (W) feature */ 35 #define ATA_F_DMA 0x01 /* enable DMA */ 36 #define ATA_F_OVL 0x02 /* enable overlap */ 37 38 #define ATA_COUNT 2 /* (W) sector count */ 39 40 #define ATA_SECTOR 3 /* (RW) sector # */ 41 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 42 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 43 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 44 #define ATA_D_LBA 0x40 /* use LBA addressing */ 45 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 46 47 #define ATA_COMMAND 7 /* (W) command */ 48 49 #define ATA_ERROR 8 /* (R) error */ 50 #define ATA_E_ILI 0x01 /* illegal length */ 51 #define ATA_E_NM 0x02 /* no media */ 52 #define ATA_E_ABORT 0x04 /* command aborted */ 53 #define ATA_E_MCR 0x08 /* media change request */ 54 #define ATA_E_IDNF 0x10 /* ID not found */ 55 #define ATA_E_MC 0x20 /* media changed */ 56 #define ATA_E_UNC 0x40 /* uncorrectable data */ 57 #define ATA_E_ICRC 0x80 /* UDMA crc error */ 58 #define ATA_E_MASK 0x0f /* error mask */ 59 #define ATA_SK_MASK 0xf0 /* sense key mask */ 60 #define ATA_SK_NO_SENSE 0x00 /* no specific sense key info */ 61 #define ATA_SK_RECOVERED_ERROR 0x10 /* command OK, data recovered */ 62 #define ATA_SK_NOT_READY 0x20 /* no access to drive */ 63 #define ATA_SK_MEDIUM_ERROR 0x30 /* non-recovered data error */ 64 #define ATA_SK_HARDWARE_ERROR 0x40 /* non-recoverable HW failure */ 65 #define ATA_SK_ILLEGAL_REQUEST 0x50 /* invalid command param(s) */ 66 #define ATA_SK_UNIT_ATTENTION 0x60 /* media changed */ 67 #define ATA_SK_DATA_PROTECT 0x70 /* write protect */ 68 #define ATA_SK_BLANK_CHECK 0x80 /* blank check */ 69 #define ATA_SK_VENDOR_SPECIFIC 0x90 /* vendor specific skey */ 70 #define ATA_SK_COPY_ABORTED 0xa0 /* copy aborted */ 71 #define ATA_SK_ABORTED_COMMAND 0xb0 /* command aborted, try again */ 72 #define ATA_SK_EQUAL 0xc0 /* equal */ 73 #define ATA_SK_VOLUME_OVERFLOW 0xd0 /* volume overflow */ 74 #define ATA_SK_MISCOMPARE 0xe0 /* data dont match the medium */ 75 #define ATA_SK_RESERVED 0xf0 76 77 #define ATA_IREASON 9 /* (R) interrupt reason */ 78 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 79 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 80 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 81 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 82 83 #define ATA_STATUS 10 /* (R) status */ 84 #define ATA_ALTSTAT 11 /* (R) alternate status */ 85 #define ATA_S_ERROR 0x01 /* error */ 86 #define ATA_S_INDEX 0x02 /* index */ 87 #define ATA_S_CORR 0x04 /* data corrected */ 88 #define ATA_S_DRQ 0x08 /* data request */ 89 #define ATA_S_DSC 0x10 /* drive seek completed */ 90 #define ATA_S_SERVICE 0x10 /* drive needs service */ 91 #define ATA_S_DWF 0x20 /* drive write fault */ 92 #define ATA_S_DMA 0x20 /* DMA ready */ 93 #define ATA_S_READY 0x40 /* drive ready */ 94 #define ATA_S_BUSY 0x80 /* busy */ 95 96 #define ATA_CONTROL 12 /* (W) control */ 97 98 #define ATA_CTLOFFSET 0x206 /* control register offset */ 99 #define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */ 100 #define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */ 101 #define ATA_A_IDS 0x02 /* disable interrupts */ 102 #define ATA_A_RESET 0x04 /* RESET controller */ 103 #define ATA_A_4BIT 0x08 /* 4 head bits */ 104 #define ATA_A_HOB 0x80 /* High Order Byte enable */ 105 106 /* SATA register defines */ 107 #define ATA_SSTATUS 13 108 #define ATA_SS_DET_MASK 0x0000000f 109 #define ATA_SS_DET_NO_DEVICE 0x00000000 110 #define ATA_SS_DET_DEV_PRESENT 0x00000001 111 #define ATA_SS_DET_PHY_ONLINE 0x00000003 112 #define ATA_SS_DET_PHY_OFFLINE 0x00000004 113 114 #define ATA_SS_SPD_MASK 0x000000f0 115 #define ATA_SS_SPD_NO_SPEED 0x00000000 116 #define ATA_SS_SPD_GEN1 0x00000010 117 #define ATA_SS_SPD_GEN2 0x00000020 118 119 #define ATA_SS_IPM_MASK 0x00000f00 120 #define ATA_SS_IPM_NO_DEVICE 0x00000000 121 #define ATA_SS_IPM_ACTIVE 0x00000100 122 #define ATA_SS_IPM_PARTIAL 0x00000200 123 #define ATA_SS_IPM_SLUMBER 0x00000600 124 125 #define ATA_SS_CONWELL_MASK \ 126 (ATA_SS_DET_MASK|ATA_SS_SPD_MASK|ATA_SS_IPM_MASK) 127 #define ATA_SS_CONWELL_GEN1 \ 128 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN1|ATA_SS_IPM_ACTIVE) 129 #define ATA_SS_CONWELL_GEN2 \ 130 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN2|ATA_SS_IPM_ACTIVE) 131 132 #define ATA_SERROR 14 133 #define ATA_SE_DATA_CORRECTED 0x00000001 134 #define ATA_SE_COMM_CORRECTED 0x00000002 135 #define ATA_SE_DATA_ERR 0x00000100 136 #define ATA_SE_COMM_ERR 0x00000200 137 #define ATA_SE_PROT_ERR 0x00000400 138 #define ATA_SE_HOST_ERR 0x00000800 139 #define ATA_SE_PHY_CHANGED 0x00010000 140 #define ATA_SE_PHY_IERROR 0x00020000 141 #define ATA_SE_COMM_WAKE 0x00040000 142 #define ATA_SE_DECODE_ERR 0x00080000 143 #define ATA_SE_PARITY_ERR 0x00100000 144 #define ATA_SE_CRC_ERR 0x00200000 145 #define ATA_SE_HANDSHAKE_ERR 0x00400000 146 #define ATA_SE_LINKSEQ_ERR 0x00800000 147 #define ATA_SE_TRANSPORT_ERR 0x01000000 148 #define ATA_SE_UNKNOWN_FIS 0x02000000 149 150 #define ATA_SCONTROL 15 151 #define ATA_SC_DET_MASK 0x0000000f 152 #define ATA_SC_DET_IDLE 0x00000000 153 #define ATA_SC_DET_RESET 0x00000001 154 #define ATA_SC_DET_DISABLE 0x00000004 155 156 #define ATA_SC_SPD_MASK 0x000000f0 157 #define ATA_SC_SPD_NO_SPEED 0x00000000 158 #define ATA_SC_SPD_SPEED_GEN1 0x00000010 159 #define ATA_SC_SPD_SPEED_GEN2 0x00000020 160 161 #define ATA_SC_IPM_MASK 0x00000f00 162 #define ATA_SC_IPM_NONE 0x00000000 163 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100 164 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200 165 166 /* DMA register defines */ 167 #define ATA_DMA_ENTRIES 256 168 #define ATA_DMA_EOT 0x80000000 169 170 #define ATA_BMCMD_PORT 16 171 #define ATA_BMCMD_START_STOP 0x01 172 #define ATA_BMCMD_WRITE_READ 0x08 173 174 #define ATA_BMDEVSPEC_0 17 175 #define ATA_BMSTAT_PORT 18 176 #define ATA_BMSTAT_ACTIVE 0x01 177 #define ATA_BMSTAT_ERROR 0x02 178 #define ATA_BMSTAT_INTERRUPT 0x04 179 #define ATA_BMSTAT_MASK 0x07 180 #define ATA_BMSTAT_DMA_MASTER 0x20 181 #define ATA_BMSTAT_DMA_SLAVE 0x40 182 #define ATA_BMSTAT_DMA_SIMPLEX 0x80 183 184 #define ATA_BMDEVSPEC_1 19 185 #define ATA_BMDTP_PORT 20 186 187 #define ATA_IDX_ADDR 21 188 #define ATA_IDX_DATA 22 189 #define ATA_MAX_RES 23 190 191 /* misc defines */ 192 #define ATA_PRIMARY 0x1f0 193 #define ATA_SECONDARY 0x170 194 #define ATA_PC98_BANK 0x432 195 #define ATA_IOSIZE 0x08 196 #define ATA_PC98_IOSIZE 0x10 197 #define ATA_CTLIOSIZE 0x01 198 #define ATA_BMIOSIZE 0x08 199 #define ATA_PC98_BANKIOSIZE 0x01 200 #define ATA_IOADDR_RID 0 201 #define ATA_CTLADDR_RID 1 202 #define ATA_BMADDR_RID 0x20 203 #define ATA_PC98_CTLADDR_RID 8 204 #define ATA_PC98_BANKADDR_RID 9 205 #define ATA_IRQ_RID 0 206 #define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1) 207 #define ATAPI_MAGIC_LSB 0x14 208 #define ATAPI_MAGIC_MSB 0xeb 209 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 210 #define ATAPI_P_WRITE (ATA_S_DRQ) 211 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 212 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 213 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 214 #define ATAPI_P_ABORT 0 215 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 216 #define ATA_OP_CONTINUES 0 217 #define ATA_OP_FINISHED 1 218 #define ATA_MAX_28BIT_LBA 268435455 219 220 /* ATAPI request sense structure */ 221 struct atapi_sense { 222 u_int8_t error_code :7; /* current or deferred errors */ 223 u_int8_t valid :1; /* follows ATAPI spec */ 224 u_int8_t segment; /* Segment number */ 225 u_int8_t sense_key :4; /* sense key */ 226 u_int8_t reserved2_4 :1; /* reserved */ 227 u_int8_t ili :1; /* incorrect length indicator */ 228 u_int8_t eom :1; /* end of medium */ 229 u_int8_t filemark :1; /* filemark */ 230 u_int32_t cmd_info __packed; /* cmd information */ 231 u_int8_t sense_length; /* additional sense len (n-7) */ 232 u_int32_t cmd_specific_info __packed; /* additional cmd spec info */ 233 u_int8_t asc; /* additional sense code */ 234 u_int8_t ascq; /* additional sense code qual */ 235 u_int8_t replaceable_unit_code; /* replaceable unit code */ 236 u_int8_t sk_specific :7; /* sense key specific */ 237 u_int8_t sksv :1; /* sense key specific info OK */ 238 u_int8_t sk_specific1; /* sense key specific */ 239 u_int8_t sk_specific2; /* sense key specific */ 240 }; 241 242 /* structure used for composite atomic operations */ 243 struct ata_composite { 244 struct mtx lock; /* control lock */ 245 u_int32_t rd_needed; /* needed read subdisks */ 246 u_int32_t rd_done; /* done read subdisks */ 247 u_int32_t wr_needed; /* needed write subdisks */ 248 u_int32_t wr_depend; /* write depends on subdisks */ 249 u_int32_t wr_done; /* done write subdisks */ 250 struct ata_request *request[32]; /* size must match maps above */ 251 caddr_t data_1; 252 caddr_t data_2; 253 }; 254 255 /* structure used to queue an ATA/ATAPI request */ 256 struct ata_request { 257 device_t dev; /* device handle */ 258 union { 259 struct { 260 u_int8_t command; /* command reg */ 261 u_int16_t feature; /* feature reg */ 262 u_int16_t count; /* count reg */ 263 u_int64_t lba; /* lba reg */ 264 } ata; 265 struct { 266 u_int8_t ccb[16]; /* ATAPI command block */ 267 struct atapi_sense sense_data; /* ATAPI request sense data */ 268 u_int8_t sense_key; /* ATAPI request sense key */ 269 u_int8_t sense_cmd; /* ATAPI saved command */ 270 } atapi; 271 } u; 272 u_int32_t bytecount; /* bytes to transfer */ 273 u_int32_t transfersize; /* bytes pr transfer */ 274 caddr_t data; /* pointer to data buf */ 275 int flags; 276 #define ATA_R_CONTROL 0x00000001 277 #define ATA_R_READ 0x00000002 278 #define ATA_R_WRITE 0x00000004 279 #define ATA_R_DMA 0x00000008 280 281 #define ATA_R_ATAPI 0x00000010 282 #define ATA_R_QUIET 0x00000020 283 #define ATA_R_INTR_SEEN 0x00000040 284 #define ATA_R_TIMEOUT 0x00000080 285 286 #define ATA_R_ORDERED 0x00000100 287 #define ATA_R_AT_HEAD 0x00000200 288 #define ATA_R_REQUEUE 0x00000400 289 #define ATA_R_THREAD 0x00000800 290 #define ATA_R_DIRECT 0x00001000 291 292 #define ATA_R_DEBUG 0x10000000 293 294 u_int8_t status; /* ATA status */ 295 u_int8_t error; /* ATA error */ 296 u_int8_t dmastat; /* DMA status */ 297 u_int32_t donecount; /* bytes transferred */ 298 int result; /* result error code */ 299 void (*callback)(struct ata_request *request); 300 struct sema done; /* request done sema */ 301 int retries; /* retry count */ 302 int timeout; /* timeout for this cmd */ 303 struct callout callout; /* callout management */ 304 struct task task; /* task management */ 305 struct bio *bio; /* bio for this request */ 306 int this; /* this request ID */ 307 struct ata_composite *composite; /* for composite atomic ops */ 308 void *driver; /* driver specific */ 309 TAILQ_ENTRY(ata_request) chain; /* list management */ 310 }; 311 312 /* define this for debugging request processing */ 313 #if 0 314 #define ATA_DEBUG_RQ(request, string) \ 315 { \ 316 if (request->flags & ATA_R_DEBUG) \ 317 device_printf(request->dev, "req=%p %s " string "\n", \ 318 request, ata_cmd2str(request)); \ 319 } 320 #else 321 #define ATA_DEBUG_RQ(request, string) 322 #endif 323 324 325 /* structure describing an ATA/ATAPI device */ 326 struct ata_device { 327 device_t dev; /* device handle */ 328 int unit; /* physical unit */ 329 #define ATA_MASTER 0x00 330 #define ATA_SLAVE 0x10 331 332 struct ata_params param; /* ata param structure */ 333 int mode; /* current transfermode */ 334 u_int32_t max_iosize; /* max IO size */ 335 int cmd; /* last cmd executed */ 336 int flags; 337 #define ATA_D_USE_CHS 0x0001 338 #define ATA_D_MEDIA_CHANGED 0x0002 339 #define ATA_D_ENC_PRESENT 0x0004 340 }; 341 342 /* structure for holding DMA Physical Region Descriptors (PRD) entries */ 343 struct ata_dma_prdentry { 344 u_int32_t addr; 345 u_int32_t count; 346 }; 347 348 /* structure used by the setprd function */ 349 struct ata_dmasetprd_args { 350 void *dmatab; 351 int error; 352 }; 353 354 struct ata_channel {}; 355 /* structure holding DMA related information */ 356 struct ata_dma { 357 bus_dma_tag_t dmatag; /* parent DMA tag */ 358 bus_dma_tag_t sg_tag; /* SG list DMA tag */ 359 bus_dmamap_t sg_map; /* SG list DMA map */ 360 void *sg; /* DMA transfer table */ 361 bus_addr_t sg_bus; /* bus address of dmatab */ 362 bus_dma_tag_t data_tag; /* data DMA tag */ 363 bus_dmamap_t data_map; /* data DMA map */ 364 bus_dma_tag_t work_tag; /* workspace DMA tag */ 365 bus_dmamap_t work_map; /* workspace DMA map */ 366 u_int8_t *work; /* workspace */ 367 bus_addr_t work_bus; /* bus address of dmatab */ 368 369 u_int32_t alignment; /* DMA engine alignment */ 370 u_int32_t boundary; /* DMA engine boundary */ 371 u_int32_t max_iosize; /* DMA engine max IO size */ 372 u_int32_t cur_iosize; /* DMA engine current IO size */ 373 int flags; 374 #define ATA_DMA_READ 0x01 /* transaction is a read */ 375 #define ATA_DMA_LOADED 0x02 /* DMA tables etc loaded */ 376 #define ATA_DMA_ACTIVE 0x04 /* DMA transfer in progress */ 377 378 void (*alloc)(struct ata_channel *ch); 379 void (*free)(struct ata_channel *ch); 380 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 381 int (*load)(struct ata_device *atadev, caddr_t data, int32_t count,int dir); 382 int (*unload)(struct ata_channel *ch); 383 int (*start)(struct ata_channel *ch); 384 int (*stop)(struct ata_channel *ch); 385 }; 386 387 /* structure holding lowlevel functions */ 388 struct ata_lowlevel { 389 int (*begin_transaction)(struct ata_request *request); 390 int (*end_transaction)(struct ata_request *request); 391 void (*reset)(struct ata_channel *ch); 392 int (*command)(struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature); 393 }; 394 395 /* structure holding resources for an ATA channel */ 396 struct ata_resource { 397 struct resource *res; 398 int offset; 399 }; 400 401 /* structure describing an ATA channel */ 402 struct ata_channel { 403 device_t dev; /* device handle */ 404 int unit; /* physical channel */ 405 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ 406 struct resource *r_irq; /* interrupt of this channel */ 407 void *ih; /* interrupt handle */ 408 struct ata_lowlevel hw; /* lowlevel HW functions */ 409 struct ata_dma *dma; /* DMA data / functions */ 410 int flags; /* channel flags */ 411 #define ATA_NO_SLAVE 0x01 412 #define ATA_USE_16BIT 0x02 413 #define ATA_ATAPI_DMA_RO 0x04 414 #define ATA_48BIT_ACTIVE 0x08 415 416 int devices; /* what is present */ 417 #define ATA_ATA_MASTER 0x01 418 #define ATA_ATA_SLAVE 0x02 419 #define ATA_ATAPI_MASTER 0x04 420 #define ATA_ATAPI_SLAVE 0x08 421 422 struct mtx state_mtx; /* state lock */ 423 int state; /* ATA channel state */ 424 #define ATA_IDLE 0x0000 425 #define ATA_ACTIVE 0x0001 426 #define ATA_STALL_QUEUE 0x0002 427 #define ATA_TIMEOUT 0x0004 428 429 struct mtx queue_mtx; /* queue lock */ 430 TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */ 431 struct ata_request *freezepoint; /* composite freezepoint */ 432 struct ata_request *running; /* currently running request */ 433 }; 434 435 /* disk bay/enclosure related */ 436 #define ATA_LED_OFF 0x00 437 #define ATA_LED_RED 0x01 438 #define ATA_LED_GREEN 0x02 439 #define ATA_LED_ORANGE 0x03 440 #define ATA_LED_MASK 0x03 441 442 /* externs */ 443 extern int (*ata_ioctl_func)(struct ata_cmd *iocmd); 444 extern devclass_t ata_devclass; 445 extern int ata_wc; 446 447 /* public prototypes */ 448 /* ata-all.c: */ 449 int ata_probe(device_t dev); 450 int ata_attach(device_t dev); 451 int ata_detach(device_t dev); 452 int ata_reinit(device_t dev); 453 int ata_suspend(device_t dev); 454 int ata_resume(device_t dev); 455 void ata_default_registers(struct ata_channel *ch); 456 void ata_udelay(int interval); 457 char *ata_mode2str(int mode); 458 int ata_pmode(struct ata_params *ap); 459 int ata_wmode(struct ata_params *ap); 460 int ata_umode(struct ata_params *ap); 461 int ata_limit_mode(struct ata_device *atadev, int mode, int maxmode); 462 463 /* ata-queue.c: */ 464 int ata_controlcmd(struct ata_device *atadev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count); 465 int ata_atapicmd(struct ata_device *atadev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout); 466 void ata_queue_request(struct ata_request *request); 467 void ata_start(device_t dev); 468 void ata_finish(struct ata_request *request); 469 void ata_catch_inflight(struct ata_channel *ch); 470 void ata_fail_requests(struct ata_channel *ch, device_t dev); 471 char *ata_cmd2str(struct ata_request *request); 472 473 /* ata-lowlevel.c: */ 474 void ata_generic_hw(struct ata_channel *ch); 475 int ata_generic_command(struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature); 476 int ata_getparam(device_t parent, struct ata_device *atadev, u_int8_t command); 477 478 /* macros for alloc/free of struct ata_request */ 479 extern uma_zone_t ata_request_zone; 480 #define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT | M_ZERO) 481 #define ata_free_request(request) uma_zfree(ata_request_zone, request) 482 483 /* macros for alloc/free of struct ata_composite */ 484 extern uma_zone_t ata_composite_zone; 485 #define ata_alloc_composite() uma_zalloc(ata_composite_zone, M_NOWAIT | M_ZERO) 486 #define ata_free_composite(composite) uma_zfree(ata_composite_zone, composite) 487 488 MALLOC_DECLARE(M_ATA); 489 490 /* misc newbus defines */ 491 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 492 493 /* macros to hide busspace uglyness */ 494 #define ATA_INB(res, offset) \ 495 bus_space_read_1(rman_get_bustag((res)), \ 496 rman_get_bushandle((res)), (offset)) 497 498 #define ATA_INW(res, offset) \ 499 bus_space_read_2(rman_get_bustag((res)), \ 500 rman_get_bushandle((res)), (offset)) 501 #define ATA_INL(res, offset) \ 502 bus_space_read_4(rman_get_bustag((res)), \ 503 rman_get_bushandle((res)), (offset)) 504 #define ATA_INSW(res, offset, addr, count) \ 505 bus_space_read_multi_2(rman_get_bustag((res)), \ 506 rman_get_bushandle((res)), \ 507 (offset), (addr), (count)) 508 #define ATA_INSW_STRM(res, offset, addr, count) \ 509 bus_space_read_multi_stream_2(rman_get_bustag((res)), \ 510 rman_get_bushandle((res)), \ 511 (offset), (addr), (count)) 512 #define ATA_INSL(res, offset, addr, count) \ 513 bus_space_read_multi_4(rman_get_bustag((res)), \ 514 rman_get_bushandle((res)), \ 515 (offset), (addr), (count)) 516 #define ATA_INSL_STRM(res, offset, addr, count) \ 517 bus_space_read_multi_stream_4(rman_get_bustag((res)), \ 518 rman_get_bushandle((res)), \ 519 (offset), (addr), (count)) 520 #define ATA_OUTB(res, offset, value) \ 521 bus_space_write_1(rman_get_bustag((res)), \ 522 rman_get_bushandle((res)), (offset), (value)) 523 #define ATA_OUTW(res, offset, value) \ 524 bus_space_write_2(rman_get_bustag((res)), \ 525 rman_get_bushandle((res)), (offset), (value)) 526 #define ATA_OUTL(res, offset, value) \ 527 bus_space_write_4(rman_get_bustag((res)), \ 528 rman_get_bushandle((res)), (offset), (value)) 529 #define ATA_OUTSW(res, offset, addr, count) \ 530 bus_space_write_multi_2(rman_get_bustag((res)), \ 531 rman_get_bushandle((res)), \ 532 (offset), (addr), (count)) 533 #define ATA_OUTSW_STRM(res, offset, addr, count) \ 534 bus_space_write_multi_stream_2(rman_get_bustag((res)), \ 535 rman_get_bushandle((res)), \ 536 (offset), (addr), (count)) 537 #define ATA_OUTSL(res, offset, addr, count) \ 538 bus_space_write_multi_4(rman_get_bustag((res)), \ 539 rman_get_bushandle((res)), \ 540 (offset), (addr), (count)) 541 #define ATA_OUTSL_STRM(res, offset, addr, count) \ 542 bus_space_write_multi_stream_4(rman_get_bustag((res)), \ 543 rman_get_bushandle((res)), \ 544 (offset), (addr), (count)) 545 546 #define ATA_IDX_INB(ch, idx) \ 547 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) 548 549 #define ATA_IDX_INW(ch, idx) \ 550 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) 551 552 #define ATA_IDX_INL(ch, idx) \ 553 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) 554 555 #define ATA_IDX_INSW(ch, idx, addr, count) \ 556 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 557 558 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 559 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 560 561 #define ATA_IDX_INSL(ch, idx, addr, count) \ 562 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 563 564 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 565 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 566 567 #define ATA_IDX_OUTB(ch, idx, value) \ 568 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) 569 570 #define ATA_IDX_OUTW(ch, idx, value) \ 571 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) 572 573 #define ATA_IDX_OUTL(ch, idx, value) \ 574 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) 575 576 #define ATA_IDX_OUTSW(ch, idx, addr, count) \ 577 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 578 579 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 580 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 581 582 #define ATA_IDX_OUTSL(ch, idx, addr, count) \ 583 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 584 585 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 586 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 587