1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include "opt_ata.h" 30 31 #if 0 32 #define ATA_LEGACY_SUPPORT /* Enable obsolete features that break 33 * some modern devices */ 34 #endif 35 36 /* ATA register defines */ 37 #define ATA_DATA 0 /* (RW) data */ 38 39 #define ATA_FEATURE 1 /* (W) feature */ 40 #define ATA_F_DMA 0x01 /* enable DMA */ 41 #define ATA_F_OVL 0x02 /* enable overlap */ 42 43 #define ATA_COUNT 2 /* (W) sector count */ 44 45 #define ATA_SECTOR 3 /* (RW) sector # */ 46 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 47 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 48 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 49 #define ATA_D_LBA 0x40 /* use LBA addressing */ 50 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 51 52 #define ATA_COMMAND 7 /* (W) command */ 53 54 #define ATA_ERROR 8 /* (R) error */ 55 #define ATA_E_ILI 0x01 /* illegal length */ 56 #define ATA_E_NM 0x02 /* no media */ 57 #define ATA_E_ABORT 0x04 /* command aborted */ 58 #define ATA_E_MCR 0x08 /* media change request */ 59 #define ATA_E_IDNF 0x10 /* ID not found */ 60 #define ATA_E_MC 0x20 /* media changed */ 61 #define ATA_E_UNC 0x40 /* uncorrectable data */ 62 #define ATA_E_ICRC 0x80 /* UDMA crc error */ 63 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 64 65 #define ATA_IREASON 9 /* (R) interrupt reason */ 66 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 67 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 68 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 69 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 70 71 #define ATA_STATUS 10 /* (R) status */ 72 #define ATA_ALTSTAT 11 /* (R) alternate status */ 73 #define ATA_S_ERROR 0x01 /* error */ 74 #define ATA_S_INDEX 0x02 /* index */ 75 #define ATA_S_CORR 0x04 /* data corrected */ 76 #define ATA_S_DRQ 0x08 /* data request */ 77 #define ATA_S_DSC 0x10 /* drive seek completed */ 78 #define ATA_S_SERVICE 0x10 /* drive needs service */ 79 #define ATA_S_DWF 0x20 /* drive write fault */ 80 #define ATA_S_DMA 0x20 /* DMA ready */ 81 #define ATA_S_READY 0x40 /* drive ready */ 82 #define ATA_S_BUSY 0x80 /* busy */ 83 84 #define ATA_CONTROL 12 /* (W) control */ 85 86 #define ATA_CTLOFFSET 0x206 /* control register offset */ 87 #define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */ 88 #define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */ 89 #define ATA_A_IDS 0x02 /* disable interrupts */ 90 #define ATA_A_RESET 0x04 /* RESET controller */ 91 #ifdef ATA_LEGACY_SUPPORT 92 #define ATA_A_4BIT 0x08 /* 4 head bits: obsolete 1996 */ 93 #else 94 #define ATA_A_4BIT 0x00 95 #endif 96 #define ATA_A_HOB 0x80 /* High Order Byte enable */ 97 98 /* SATA register defines */ 99 #define ATA_SSTATUS 13 100 #define ATA_SS_DET_MASK 0x0000000f 101 #define ATA_SS_DET_NO_DEVICE 0x00000000 102 #define ATA_SS_DET_DEV_PRESENT 0x00000001 103 #define ATA_SS_DET_PHY_ONLINE 0x00000003 104 #define ATA_SS_DET_PHY_OFFLINE 0x00000004 105 106 #define ATA_SS_SPD_MASK 0x000000f0 107 #define ATA_SS_SPD_NO_SPEED 0x00000000 108 #define ATA_SS_SPD_GEN1 0x00000010 109 #define ATA_SS_SPD_GEN2 0x00000020 110 111 #define ATA_SS_IPM_MASK 0x00000f00 112 #define ATA_SS_IPM_NO_DEVICE 0x00000000 113 #define ATA_SS_IPM_ACTIVE 0x00000100 114 #define ATA_SS_IPM_PARTIAL 0x00000200 115 #define ATA_SS_IPM_SLUMBER 0x00000600 116 117 #define ATA_SS_CONWELL_MASK \ 118 (ATA_SS_DET_MASK|ATA_SS_SPD_MASK|ATA_SS_IPM_MASK) 119 #define ATA_SS_CONWELL_GEN1 \ 120 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN1|ATA_SS_IPM_ACTIVE) 121 #define ATA_SS_CONWELL_GEN2 \ 122 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN2|ATA_SS_IPM_ACTIVE) 123 124 #define ATA_SERROR 14 125 #define ATA_SE_DATA_CORRECTED 0x00000001 126 #define ATA_SE_COMM_CORRECTED 0x00000002 127 #define ATA_SE_DATA_ERR 0x00000100 128 #define ATA_SE_COMM_ERR 0x00000200 129 #define ATA_SE_PROT_ERR 0x00000400 130 #define ATA_SE_HOST_ERR 0x00000800 131 #define ATA_SE_PHY_CHANGED 0x00010000 132 #define ATA_SE_PHY_IERROR 0x00020000 133 #define ATA_SE_COMM_WAKE 0x00040000 134 #define ATA_SE_DECODE_ERR 0x00080000 135 #define ATA_SE_PARITY_ERR 0x00100000 136 #define ATA_SE_CRC_ERR 0x00200000 137 #define ATA_SE_HANDSHAKE_ERR 0x00400000 138 #define ATA_SE_LINKSEQ_ERR 0x00800000 139 #define ATA_SE_TRANSPORT_ERR 0x01000000 140 #define ATA_SE_UNKNOWN_FIS 0x02000000 141 142 #define ATA_SCONTROL 15 143 #define ATA_SC_DET_MASK 0x0000000f 144 #define ATA_SC_DET_IDLE 0x00000000 145 #define ATA_SC_DET_RESET 0x00000001 146 #define ATA_SC_DET_DISABLE 0x00000004 147 148 #define ATA_SC_SPD_MASK 0x000000f0 149 #define ATA_SC_SPD_NO_SPEED 0x00000000 150 #define ATA_SC_SPD_SPEED_GEN1 0x00000010 151 #define ATA_SC_SPD_SPEED_GEN2 0x00000020 152 153 #define ATA_SC_IPM_MASK 0x00000f00 154 #define ATA_SC_IPM_NONE 0x00000000 155 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100 156 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200 157 158 #define ATA_SACTIVE 16 159 160 /* SATA AHCI v1.0 register defines */ 161 #define ATA_AHCI_CAP 0x00 162 #define ATA_AHCI_CAP_NPMASK 0x0000001f 163 #define ATA_AHCI_CAP_SXS 0x00000020 164 #define ATA_AHCI_CAP_EMS 0x00000040 165 #define ATA_AHCI_CAP_CCCS 0x00000080 166 #define ATA_AHCI_CAP_NCS 0x00001F00 167 #define ATA_AHCI_CAP_NCS_SHIFT 8 168 #define ATA_AHCI_CAP_PSC 0x00002000 169 #define ATA_AHCI_CAP_SSC 0x00004000 170 #define ATA_AHCI_CAP_PMD 0x00008000 171 #define ATA_AHCI_CAP_FBSS 0x00010000 172 #define ATA_AHCI_CAP_SPM 0x00020000 173 #define ATA_AHCI_CAP_SAM 0x00080000 174 #define ATA_AHCI_CAP_ISS 0x00F00000 175 #define ATA_AHCI_CAP_ISS_SHIFT 20 176 #define ATA_AHCI_CAP_SCLO 0x01000000 177 #define ATA_AHCI_CAP_SAL 0x02000000 178 #define ATA_AHCI_CAP_SALP 0x04000000 179 #define ATA_AHCI_CAP_SSS 0x08000000 180 #define ATA_AHCI_CAP_SMPS 0x10000000 181 #define ATA_AHCI_CAP_SSNTF 0x20000000 182 #define ATA_AHCI_CAP_SNCQ 0x40000000 183 #define ATA_AHCI_CAP_64BIT 0x80000000 184 185 #define ATA_AHCI_GHC 0x04 186 #define ATA_AHCI_GHC_AE 0x80000000 187 #define ATA_AHCI_GHC_IE 0x00000002 188 #define ATA_AHCI_GHC_HR 0x00000001 189 190 #define ATA_AHCI_IS 0x08 191 #define ATA_AHCI_PI 0x0c 192 #define ATA_AHCI_VS 0x10 193 194 #define ATA_AHCI_OFFSET 0x80 195 196 #define ATA_AHCI_P_CLB 0x100 197 #define ATA_AHCI_P_CLBU 0x104 198 #define ATA_AHCI_P_FB 0x108 199 #define ATA_AHCI_P_FBU 0x10c 200 #define ATA_AHCI_P_IS 0x110 201 #define ATA_AHCI_P_IE 0x114 202 #define ATA_AHCI_P_IX_DHR 0x00000001 203 #define ATA_AHCI_P_IX_PS 0x00000002 204 #define ATA_AHCI_P_IX_DS 0x00000004 205 #define ATA_AHCI_P_IX_SDB 0x00000008 206 #define ATA_AHCI_P_IX_UF 0x00000010 207 #define ATA_AHCI_P_IX_DP 0x00000020 208 #define ATA_AHCI_P_IX_PC 0x00000040 209 #define ATA_AHCI_P_IX_DI 0x00000080 210 211 #define ATA_AHCI_P_IX_PRC 0x00400000 212 #define ATA_AHCI_P_IX_IPM 0x00800000 213 #define ATA_AHCI_P_IX_OF 0x01000000 214 #define ATA_AHCI_P_IX_INF 0x04000000 215 #define ATA_AHCI_P_IX_IF 0x08000000 216 #define ATA_AHCI_P_IX_HBD 0x10000000 217 #define ATA_AHCI_P_IX_HBF 0x20000000 218 #define ATA_AHCI_P_IX_TFE 0x40000000 219 #define ATA_AHCI_P_IX_CPD 0x80000000 220 221 #define ATA_AHCI_P_CMD 0x118 222 #define ATA_AHCI_P_CMD_ST 0x00000001 223 #define ATA_AHCI_P_CMD_SUD 0x00000002 224 #define ATA_AHCI_P_CMD_POD 0x00000004 225 #define ATA_AHCI_P_CMD_CLO 0x00000008 226 #define ATA_AHCI_P_CMD_FRE 0x00000010 227 #define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00 228 #define ATA_AHCI_P_CMD_ISS 0x00002000 229 #define ATA_AHCI_P_CMD_FR 0x00004000 230 #define ATA_AHCI_P_CMD_CR 0x00008000 231 #define ATA_AHCI_P_CMD_CPS 0x00010000 232 #define ATA_AHCI_P_CMD_PMA 0x00020000 233 #define ATA_AHCI_P_CMD_HPCP 0x00040000 234 #define ATA_AHCI_P_CMD_ISP 0x00080000 235 #define ATA_AHCI_P_CMD_CPD 0x00100000 236 #define ATA_AHCI_P_CMD_ATAPI 0x01000000 237 #define ATA_AHCI_P_CMD_DLAE 0x02000000 238 #define ATA_AHCI_P_CMD_ALPE 0x04000000 239 #define ATA_AHCI_P_CMD_ASP 0x08000000 240 #define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000 241 #define ATA_AHCI_P_CMD_NOOP 0x00000000 242 #define ATA_AHCI_P_CMD_ACTIVE 0x10000000 243 #define ATA_AHCI_P_CMD_PARTIAL 0x20000000 244 #define ATA_AHCI_P_CMD_SLUMBER 0x60000000 245 246 #define ATA_AHCI_P_TFD 0x120 247 #define ATA_AHCI_P_SIG 0x124 248 #define ATA_AHCI_P_SSTS 0x128 249 #define ATA_AHCI_P_SCTL 0x12c 250 #define ATA_AHCI_P_SERR 0x130 251 #define ATA_AHCI_P_SACT 0x134 252 #define ATA_AHCI_P_CI 0x138 253 #define ATA_AHCI_P_SNTF 0x13C 254 #define ATA_AHCI_P_FBS 0x140 255 256 #define ATA_AHCI_CL_SIZE 32 257 #define ATA_AHCI_CL_OFFSET 0 258 #define ATA_AHCI_FB_OFFSET (ATA_AHCI_CL_SIZE * 32) 259 #define ATA_AHCI_CT_OFFSET (ATA_AHCI_FB_OFFSET + 4096) 260 #define ATA_AHCI_CT_SIZE (2176 + 128) 261 262 struct ata_ahci_dma_prd { 263 u_int64_t dba; 264 u_int32_t reserved; 265 u_int32_t dbc; /* 0 based */ 266 #define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */ 267 #define ATA_AHCI_PRD_IPC (1<<31) 268 } __packed; 269 270 struct ata_ahci_cmd_tab { 271 u_int8_t cfis[64]; 272 u_int8_t acmd[32]; 273 u_int8_t reserved[32]; 274 #define ATA_AHCI_DMA_ENTRIES 129 275 struct ata_ahci_dma_prd prd_tab[ATA_AHCI_DMA_ENTRIES]; 276 } __packed; 277 278 struct ata_ahci_cmd_list { 279 u_int16_t cmd_flags; 280 #define ATA_AHCI_CMD_ATAPI 0x0020 281 #define ATA_AHCI_CMD_WRITE 0x0040 282 #define ATA_AHCI_CMD_PREFETCH 0x0080 283 #define ATA_AHCI_CMD_RESET 0x0100 284 #define ATA_AHCI_CMD_BIST 0x0200 285 #define ATA_AHCI_CMD_CLR_BUSY 0x0400 286 287 u_int16_t prd_length; /* PRD entries */ 288 u_int32_t bytecount; 289 u_int64_t cmd_table_phys; /* 128byte aligned */ 290 } __packed; 291 292 293 /* DMA register defines */ 294 #define ATA_DMA_ENTRIES 256 295 #define ATA_DMA_EOT 0x80000000 296 297 #define ATA_BMCMD_PORT 17 298 #define ATA_BMCMD_START_STOP 0x01 299 #define ATA_BMCMD_WRITE_READ 0x08 300 301 #define ATA_BMDEVSPEC_0 18 302 #define ATA_BMSTAT_PORT 19 303 #define ATA_BMSTAT_ACTIVE 0x01 304 #define ATA_BMSTAT_ERROR 0x02 305 #define ATA_BMSTAT_INTERRUPT 0x04 306 #define ATA_BMSTAT_MASK 0x07 307 #define ATA_BMSTAT_DMA_MASTER 0x20 308 #define ATA_BMSTAT_DMA_SLAVE 0x40 309 #define ATA_BMSTAT_DMA_SIMPLEX 0x80 310 311 #define ATA_BMDEVSPEC_1 20 312 #define ATA_BMDTP_PORT 21 313 314 #define ATA_IDX_ADDR 22 315 #define ATA_IDX_DATA 23 316 #define ATA_MAX_RES 24 317 318 /* misc defines */ 319 #define ATA_PRIMARY 0x1f0 320 #define ATA_SECONDARY 0x170 321 #define ATA_PC98_BANK 0x432 322 #define ATA_IOSIZE 0x08 323 #define ATA_PC98_IOSIZE 0x10 324 #define ATA_CTLIOSIZE 0x01 325 #define ATA_BMIOSIZE 0x08 326 #define ATA_PC98_BANKIOSIZE 0x01 327 #define ATA_IOADDR_RID 0 328 #define ATA_CTLADDR_RID 1 329 #define ATA_BMADDR_RID 0x20 330 #define ATA_PC98_CTLADDR_RID 8 331 #define ATA_PC98_BANKADDR_RID 9 332 #define ATA_IRQ_RID 0 333 #define ATA_DEV(unit) ((unit > 0) ? 0x10 : 0) 334 #define ATA_CFA_MAGIC1 0x844A 335 #define ATA_CFA_MAGIC2 0x848A 336 #define ATA_CFA_MAGIC3 0x8400 337 #define ATAPI_MAGIC_LSB 0x14 338 #define ATAPI_MAGIC_MSB 0xeb 339 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 340 #define ATAPI_P_WRITE (ATA_S_DRQ) 341 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 342 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 343 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 344 #define ATAPI_P_ABORT 0 345 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 346 #define ATA_OP_CONTINUES 0 347 #define ATA_OP_FINISHED 1 348 #define ATA_MAX_28BIT_LBA 268435455UL 349 350 #ifndef ATA_REQUEST_TIMEOUT 351 #define ATA_REQUEST_TIMEOUT 10 352 #endif 353 354 /* structure used for composite atomic operations */ 355 #define MAX_COMPOSITES 32 /* u_int32_t bits */ 356 struct ata_composite { 357 struct mtx lock; /* control lock */ 358 u_int32_t rd_needed; /* needed read subdisks */ 359 u_int32_t rd_done; /* done read subdisks */ 360 u_int32_t wr_needed; /* needed write subdisks */ 361 u_int32_t wr_depend; /* write depends on subdisks */ 362 u_int32_t wr_done; /* done write subdisks */ 363 struct ata_request *request[MAX_COMPOSITES]; 364 u_int32_t residual; /* bytes still to transfer */ 365 caddr_t data_1; 366 caddr_t data_2; 367 }; 368 369 /* structure used to queue an ATA/ATAPI request */ 370 struct ata_request { 371 device_t dev; /* device handle */ 372 device_t parent; /* channel handle */ 373 int unit; /* physical unit */ 374 union { 375 struct { 376 u_int8_t command; /* command reg */ 377 u_int16_t feature; /* feature reg */ 378 u_int16_t count; /* count reg */ 379 u_int64_t lba; /* lba reg */ 380 } ata; 381 struct { 382 u_int8_t ccb[16]; /* ATAPI command block */ 383 struct atapi_sense sense; /* ATAPI request sense data */ 384 u_int8_t saved_cmd; /* ATAPI saved command */ 385 } atapi; 386 } u; 387 u_int32_t bytecount; /* bytes to transfer */ 388 u_int32_t transfersize; /* bytes pr transfer */ 389 caddr_t data; /* pointer to data buf */ 390 u_int32_t tag; /* HW tag of this request */ 391 int flags; 392 #define ATA_R_CONTROL 0x00000001 393 #define ATA_R_READ 0x00000002 394 #define ATA_R_WRITE 0x00000004 395 #define ATA_R_ATAPI 0x00000008 396 #define ATA_R_DMA 0x00000010 397 #define ATA_R_QUIET 0x00000020 398 #define ATA_R_TIMEOUT 0x00000040 399 #define ATA_R_48BIT 0x00000080 400 401 #define ATA_R_ORDERED 0x00000100 402 #define ATA_R_AT_HEAD 0x00000200 403 #define ATA_R_REQUEUE 0x00000400 404 #define ATA_R_THREAD 0x00000800 405 #define ATA_R_DIRECT 0x00001000 406 407 #define ATA_R_ATAPI16 0x00010000 408 #define ATA_R_ATAPI_INTR 0x00020000 409 410 #define ATA_R_DEBUG 0x10000000 411 #define ATA_R_DANGER1 0x20000000 412 #define ATA_R_DANGER2 0x40000000 413 414 struct ata_dmaslot *dma; /* DMA slot of this request */ 415 u_int8_t status; /* ATA status */ 416 u_int8_t error; /* ATA error */ 417 u_int32_t donecount; /* bytes transferred */ 418 int result; /* result error code */ 419 void (*callback)(struct ata_request *request); 420 struct sema done; /* request done sema */ 421 int retries; /* retry count */ 422 int timeout; /* timeout for this cmd */ 423 struct callout callout; /* callout management */ 424 struct task task; /* task management */ 425 struct bio *bio; /* bio for this request */ 426 int this; /* this request ID */ 427 struct ata_composite *composite; /* for composite atomic ops */ 428 void *driver; /* driver specific */ 429 TAILQ_ENTRY(ata_request) chain; /* list management */ 430 #ifdef ATA_CAM 431 union ccb *ccb; 432 #endif 433 }; 434 435 /* define this for debugging request processing */ 436 #if 0 437 #define ATA_DEBUG_RQ(request, string) \ 438 { \ 439 if (request->flags & ATA_R_DEBUG) \ 440 device_printf(request->parent, "req=%p %s " string "\n", \ 441 request, ata_cmd2str(request)); \ 442 } 443 #else 444 #define ATA_DEBUG_RQ(request, string) 445 #endif 446 447 448 /* structure describing an ATA/ATAPI device */ 449 struct ata_device { 450 device_t dev; /* device handle */ 451 int unit; /* physical unit */ 452 #define ATA_MASTER 0x00 453 #define ATA_SLAVE 0x01 454 #define ATA_PM 0x0f 455 456 struct ata_params param; /* ata param structure */ 457 int mode; /* current transfermode */ 458 u_int32_t max_iosize; /* max IO size */ 459 int spindown; /* idle spindown timeout */ 460 struct callout spindown_timer; 461 int spindown_state; 462 int flags; 463 #define ATA_D_USE_CHS 0x0001 464 #define ATA_D_MEDIA_CHANGED 0x0002 465 #define ATA_D_ENC_PRESENT 0x0004 466 }; 467 468 /* structure for holding DMA Physical Region Descriptors (PRD) entries */ 469 struct ata_dma_prdentry { 470 u_int32_t addr; 471 u_int32_t count; 472 }; 473 474 /* structure used by the setprd function */ 475 struct ata_dmasetprd_args { 476 void *dmatab; 477 int nsegs; 478 int error; 479 }; 480 481 struct ata_dmaslot { 482 u_int8_t status; /* DMA status */ 483 bus_dma_tag_t sg_tag; /* SG list DMA tag */ 484 bus_dmamap_t sg_map; /* SG list DMA map */ 485 void *sg; /* DMA transfer table */ 486 bus_addr_t sg_bus; /* bus address of dmatab */ 487 bus_dma_tag_t data_tag; /* data DMA tag */ 488 bus_dmamap_t data_map; /* data DMA map */ 489 }; 490 491 /* structure holding DMA related information */ 492 struct ata_dma { 493 bus_dma_tag_t dmatag; /* parent DMA tag */ 494 bus_dma_tag_t work_tag; /* workspace DMA tag */ 495 bus_dmamap_t work_map; /* workspace DMA map */ 496 u_int8_t *work; /* workspace */ 497 bus_addr_t work_bus; /* bus address of dmatab */ 498 499 #define ATA_DMA_SLOTS 1 500 int dma_slots; /* DMA slots allocated */ 501 struct ata_dmaslot slot[ATA_DMA_SLOTS]; 502 u_int32_t alignment; /* DMA SG list alignment */ 503 u_int32_t boundary; /* DMA SG list boundary */ 504 u_int32_t segsize; /* DMA SG list segment size */ 505 u_int32_t max_iosize; /* DMA data max IO size */ 506 u_int64_t max_address; /* highest DMA'able address */ 507 int flags; 508 #define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress */ 509 510 void (*alloc)(device_t dev); 511 void (*free)(device_t dev); 512 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 513 int (*load)(struct ata_request *request, void *addr, int *nsegs); 514 int (*unload)(struct ata_request *request); 515 int (*start)(struct ata_request *request); 516 int (*stop)(struct ata_request *request); 517 void (*reset)(device_t dev); 518 }; 519 520 /* structure holding lowlevel functions */ 521 struct ata_lowlevel { 522 u_int32_t (*softreset)(device_t dev, int pmport); 523 int (*pm_read)(device_t dev, int port, int reg, u_int32_t *result); 524 int (*pm_write)(device_t dev, int port, int reg, u_int32_t value); 525 int (*status)(device_t dev); 526 int (*begin_transaction)(struct ata_request *request); 527 int (*end_transaction)(struct ata_request *request); 528 int (*command)(struct ata_request *request); 529 void (*tf_read)(struct ata_request *request); 530 void (*tf_write)(struct ata_request *request); 531 }; 532 533 /* structure holding resources for an ATA channel */ 534 struct ata_resource { 535 struct resource *res; 536 int offset; 537 }; 538 539 #ifdef ATA_CAM 540 struct ata_cam_device { 541 u_int revision; 542 int mode; 543 u_int bytecount; 544 u_int atapi; 545 }; 546 #endif 547 548 /* structure describing an ATA channel */ 549 struct ata_channel { 550 device_t dev; /* device handle */ 551 int unit; /* physical channel */ 552 int attached; /* channel is attached */ 553 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ 554 struct resource *r_irq; /* interrupt of this channel */ 555 void *ih; /* interrupt handle */ 556 struct ata_lowlevel hw; /* lowlevel HW functions */ 557 struct ata_dma dma; /* DMA data / functions */ 558 int flags; /* channel flags */ 559 #define ATA_NO_SLAVE 0x01 560 #define ATA_USE_16BIT 0x02 561 #define ATA_ATAPI_DMA_RO 0x04 562 #define ATA_NO_48BIT_DMA 0x08 563 #define ATA_ALWAYS_DMASTAT 0x10 564 #define ATA_CHECKS_CABLE 0x20 565 #define ATA_NO_ATAPI_DMA 0x40 566 #define ATA_SATA 0x80 567 #define ATA_DMA_BEFORE_CMD 0x100 568 569 int pm_level; /* power management level */ 570 int devices; /* what is present */ 571 #define ATA_ATA_MASTER 0x00000001 572 #define ATA_ATA_SLAVE 0x00000002 573 #define ATA_PORTMULTIPLIER 0x00008000 574 #define ATA_ATAPI_MASTER 0x00010000 575 #define ATA_ATAPI_SLAVE 0x00020000 576 577 struct mtx state_mtx; /* state lock */ 578 int state; /* ATA channel state */ 579 #define ATA_IDLE 0x0000 580 #define ATA_ACTIVE 0x0001 581 #define ATA_STALL_QUEUE 0x0002 582 583 struct mtx queue_mtx; /* queue lock */ 584 TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */ 585 struct ata_request *freezepoint; /* composite freezepoint */ 586 struct ata_request *running; /* currently running request */ 587 struct task conntask; /* PHY events handling task */ 588 #ifdef ATA_CAM 589 struct cam_sim *sim; 590 struct cam_path *path; 591 struct ata_cam_device user[16]; /* User-specified settings */ 592 struct ata_cam_device curr[16]; /* Current settings */ 593 #endif 594 }; 595 596 /* disk bay/enclosure related */ 597 #define ATA_LED_OFF 0x00 598 #define ATA_LED_RED 0x01 599 #define ATA_LED_GREEN 0x02 600 #define ATA_LED_ORANGE 0x03 601 #define ATA_LED_MASK 0x03 602 603 /* externs */ 604 extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data); 605 extern struct intr_config_hook *ata_delayed_attach; 606 extern devclass_t ata_devclass; 607 extern int ata_wc; 608 extern int ata_setmax; 609 extern int ata_dma_check_80pin; 610 611 /* public prototypes */ 612 /* ata-all.c: */ 613 int ata_probe(device_t dev); 614 int ata_attach(device_t dev); 615 int ata_detach(device_t dev); 616 int ata_reinit(device_t dev); 617 int ata_suspend(device_t dev); 618 int ata_resume(device_t dev); 619 void ata_interrupt(void *data); 620 int ata_device_ioctl(device_t dev, u_long cmd, caddr_t data); 621 int ata_getparam(struct ata_device *atadev, int init); 622 int ata_identify(device_t dev); 623 void ata_default_registers(device_t dev); 624 void ata_modify_if_48bit(struct ata_request *request); 625 void ata_udelay(int interval); 626 char *ata_unit2str(struct ata_device *atadev); 627 const char *ata_mode2str(int mode); 628 const char *ata_satarev2str(int rev); 629 int ata_atapi(device_t dev, int target); 630 int ata_pmode(struct ata_params *ap); 631 int ata_wmode(struct ata_params *ap); 632 int ata_umode(struct ata_params *ap); 633 int ata_limit_mode(device_t dev, int mode, int maxmode); 634 void ata_setmode(device_t dev); 635 void ata_print_cable(device_t dev, u_int8_t *who); 636 int ata_check_80pin(device_t dev, int mode); 637 #ifdef ATA_CAM 638 void ata_cam_begin_transaction(device_t dev, union ccb *ccb); 639 void ata_cam_end_transaction(device_t dev, struct ata_request *request); 640 #endif 641 642 /* ata-queue.c: */ 643 int ata_controlcmd(device_t dev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count); 644 int ata_atapicmd(device_t dev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout); 645 void ata_queue_request(struct ata_request *request); 646 void ata_start(device_t dev); 647 void ata_finish(struct ata_request *request); 648 void ata_timeout(struct ata_request *); 649 void ata_catch_inflight(device_t dev); 650 void ata_fail_requests(device_t dev); 651 void ata_drop_requests(device_t dev); 652 char *ata_cmd2str(struct ata_request *request); 653 654 /* ata-lowlevel.c: */ 655 void ata_generic_hw(device_t dev); 656 int ata_begin_transaction(struct ata_request *); 657 int ata_end_transaction(struct ata_request *); 658 void ata_generic_reset(device_t dev); 659 int ata_generic_command(struct ata_request *request); 660 661 /* ata-dma.c: */ 662 void ata_dmainit(device_t); 663 void ata_dmafini(device_t dev); 664 665 /* ata-sata.c: */ 666 void ata_sata_phy_check_events(device_t dev); 667 int ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val); 668 int ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val); 669 int ata_sata_phy_reset(device_t dev, int port, int quick); 670 int ata_sata_setmode(device_t dev, int target, int mode); 671 int ata_sata_getrev(device_t dev, int target); 672 int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis); 673 void ata_pm_identify(device_t dev); 674 675 /* macros for alloc/free of struct ata_request */ 676 extern uma_zone_t ata_request_zone; 677 #define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT | M_ZERO) 678 #define ata_free_request(request) { \ 679 if (!(request->flags & ATA_R_DANGER2)) \ 680 uma_zfree(ata_request_zone, request); \ 681 } 682 683 /* macros for alloc/free of struct ata_composite */ 684 extern uma_zone_t ata_composite_zone; 685 #define ata_alloc_composite() uma_zalloc(ata_composite_zone, M_NOWAIT | M_ZERO) 686 #define ata_free_composite(composite) uma_zfree(ata_composite_zone, composite) 687 688 MALLOC_DECLARE(M_ATA); 689 690 /* misc newbus defines */ 691 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 692 693 /* macros to hide busspace uglyness */ 694 #define ATA_INB(res, offset) \ 695 bus_read_1((res), (offset)) 696 697 #define ATA_INW(res, offset) \ 698 bus_read_2((res), (offset)) 699 #define ATA_INL(res, offset) \ 700 bus_read_4((res), (offset)) 701 #define ATA_INSW(res, offset, addr, count) \ 702 bus_read_multi_2((res), (offset), (addr), (count)) 703 #define ATA_INSW_STRM(res, offset, addr, count) \ 704 bus_read_multi_stream_2((res), (offset), (addr), (count)) 705 #define ATA_INSL(res, offset, addr, count) \ 706 bus_read_multi_4((res), (offset), (addr), (count)) 707 #define ATA_INSL_STRM(res, offset, addr, count) \ 708 bus_read_multi_stream_4((res), (offset), (addr), (count)) 709 #define ATA_OUTB(res, offset, value) \ 710 bus_write_1((res), (offset), (value)) 711 #define ATA_OUTW(res, offset, value) \ 712 bus_write_2((res), (offset), (value)) 713 #define ATA_OUTL(res, offset, value) \ 714 bus_write_4((res), (offset), (value)) 715 #define ATA_OUTSW(res, offset, addr, count) \ 716 bus_write_multi_2((res), (offset), (addr), (count)) 717 #define ATA_OUTSW_STRM(res, offset, addr, count) \ 718 bus_write_multi_stream_2((res), (offset), (addr), (count)) 719 #define ATA_OUTSL(res, offset, addr, count) \ 720 bus_write_multi_4((res), (offset), (addr), (count)) 721 #define ATA_OUTSL_STRM(res, offset, addr, count) \ 722 bus_write_multi_stream_4((res), (offset), (addr), (count)) 723 724 #define ATA_IDX_INB(ch, idx) \ 725 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) 726 727 #define ATA_IDX_INW(ch, idx) \ 728 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) 729 730 #define ATA_IDX_INL(ch, idx) \ 731 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) 732 733 #define ATA_IDX_INSW(ch, idx, addr, count) \ 734 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 735 736 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 737 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 738 739 #define ATA_IDX_INSL(ch, idx, addr, count) \ 740 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 741 742 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 743 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 744 745 #define ATA_IDX_OUTB(ch, idx, value) \ 746 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) 747 748 #define ATA_IDX_OUTW(ch, idx, value) \ 749 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) 750 751 #define ATA_IDX_OUTL(ch, idx, value) \ 752 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) 753 754 #define ATA_IDX_OUTSW(ch, idx, addr, count) \ 755 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 756 757 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 758 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 759 760 #define ATA_IDX_OUTSL(ch, idx, addr, count) \ 761 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 762 763 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 764 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 765