1 /*- 2 * Copyright (c) 1998 - 2003 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* ATA register defines */ 32 #define ATA_DATA 0x00 /* data register */ 33 #define ATA_ERROR 0x01 /* (R) error register */ 34 #define ATA_E_NM 0x02 /* no media */ 35 #define ATA_E_ABORT 0x04 /* command aborted */ 36 #define ATA_E_MCR 0x08 /* media change request */ 37 #define ATA_E_IDNF 0x10 /* ID not found */ 38 #define ATA_E_MC 0x20 /* media changed */ 39 #define ATA_E_UNC 0x40 /* uncorrectable data */ 40 #define ATA_E_ICRC 0x80 /* UDMA crc error */ 41 42 #define ATA_FEATURE 0x01 /* (W) feature register */ 43 #define ATA_F_DMA 0x01 /* enable DMA */ 44 #define ATA_F_OVL 0x02 /* enable overlap */ 45 46 #define ATA_COUNT 0x02 /* (W) sector count */ 47 #define ATA_IREASON 0x02 /* (R) interrupt reason */ 48 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 49 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 50 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 51 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 52 53 #define ATA_SECTOR 0x03 /* sector # */ 54 #define ATA_CYL_LSB 0x04 /* cylinder# LSB */ 55 #define ATA_CYL_MSB 0x05 /* cylinder# MSB */ 56 #define ATA_DRIVE 0x06 /* Sector/Drive/Head register */ 57 #define ATA_D_LBA 0x40 /* use LBA addressing */ 58 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 59 60 #define ATA_CMD 0x07 /* command register */ 61 #define ATA_C_NOP 0x00 /* NOP command */ 62 #define ATA_C_F_FLUSHQUEUE 0x00 /* flush queued cmd's */ 63 #define ATA_C_F_AUTOPOLL 0x01 /* start autopoll function */ 64 #define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */ 65 #define ATA_C_READ 0x20 /* read command */ 66 #define ATA_C_READ48 0x24 /* read command */ 67 #define ATA_C_READ_DMA48 0x25 /* read w/DMA command */ 68 #define ATA_C_READ_DMA_QUEUED48 0x26 /* read w/DMA QUEUED command */ 69 #define ATA_C_READ_MUL48 0x29 /* read multi command */ 70 #define ATA_C_WRITE 0x30 /* write command */ 71 #define ATA_C_WRITE48 0x34 /* write command */ 72 #define ATA_C_WRITE_DMA48 0x35 /* write w/DMA command */ 73 #define ATA_C_WRITE_DMA_QUEUED48 0x36 /* write w/DMA QUEUED command */ 74 #define ATA_C_WRITE_MUL48 0x39 /* write multi command */ 75 #define ATA_C_PACKET_CMD 0xa0 /* packet command */ 76 #define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/ 77 #define ATA_C_SERVICE 0xa2 /* service command */ 78 #define ATA_C_READ_MUL 0xc4 /* read multi command */ 79 #define ATA_C_WRITE_MUL 0xc5 /* write multi command */ 80 #define ATA_C_SET_MULTI 0xc6 /* set multi size command */ 81 #define ATA_C_READ_DMA_QUEUED 0xc7 /* read w/DMA QUEUED command */ 82 #define ATA_C_READ_DMA 0xc8 /* read w/DMA command */ 83 #define ATA_C_WRITE_DMA 0xca /* write w/DMA command */ 84 #define ATA_C_WRITE_DMA_QUEUED 0xcc /* write w/DMA QUEUED command */ 85 #define ATA_C_SLEEP 0xe6 /* sleep command */ 86 #define ATA_C_FLUSHCACHE 0xe7 /* flush cache to disk */ 87 #define ATA_C_FLUSHCACHE48 0xea /* flush cache to disk */ 88 #define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */ 89 #define ATA_C_SETFEATURES 0xef /* features command */ 90 #define ATA_C_F_SETXFER 0x03 /* set transfer mode */ 91 #define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */ 92 #define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */ 93 #define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */ 94 #define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */ 95 #define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */ 96 #define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */ 97 #define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */ 98 #define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */ 99 100 #define ATA_STATUS 0x07 /* status register */ 101 #define ATA_S_ERROR 0x01 /* error */ 102 #define ATA_S_INDEX 0x02 /* index */ 103 #define ATA_S_CORR 0x04 /* data corrected */ 104 #define ATA_S_DRQ 0x08 /* data request */ 105 #define ATA_S_DSC 0x10 /* drive seek completed */ 106 #define ATA_S_SERVICE 0x10 /* drive needs service */ 107 #define ATA_S_DWF 0x20 /* drive write fault */ 108 #define ATA_S_DMA 0x20 /* DMA ready */ 109 #define ATA_S_READY 0x40 /* drive ready */ 110 #define ATA_S_BUSY 0x80 /* busy */ 111 112 #define ATA_ALTSTAT 0x00 /* alternate status register */ 113 #define ATA_ALTOFFSET 0x206 /* alternate registers offset */ 114 #define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */ 115 #define ATA_PC98_ALTOFFSET 0x10c /* do for PC98 devices */ 116 #define ATA_A_IDS 0x02 /* disable interrupts */ 117 #define ATA_A_RESET 0x04 /* RESET controller */ 118 #define ATA_A_4BIT 0x08 /* 4 head bits */ 119 120 /* misc defines */ 121 #define ATA_PRIMARY 0x1f0 122 #define ATA_SECONDARY 0x170 123 #define ATA_PC98_BANK 0x432 124 #define ATA_IOSIZE 0x08 125 #define ATA_ALTIOSIZE 0x01 126 #define ATA_BMIOSIZE 0x08 127 #define ATA_PC98_BANKIOSIZE 0x01 128 #define ATA_OP_FINISHED 0x00 129 #define ATA_OP_CONTINUES 0x01 130 #define ATA_IOADDR_RID 0 131 #define ATA_ALTADDR_RID 1 132 #define ATA_BMADDR_RID 2 133 #define ATA_PC98_ALTADDR_RID 8 134 #define ATA_PC98_BANKADDR_RID 9 135 136 #define ATA_IRQ_RID 0 137 #define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1) 138 139 /* busmaster DMA related defines */ 140 #define ATA_DMA_ENTRIES 256 141 #define ATA_DMA_EOT 0x80000000 142 143 #define ATA_BMCMD_PORT 0x00 144 #define ATA_BMCMD_START_STOP 0x01 145 #define ATA_BMCMD_WRITE_READ 0x08 146 147 #define ATA_BMDEVSPEC_0 0x01 148 #define ATA_BMSTAT_PORT 0x02 149 #define ATA_BMSTAT_ACTIVE 0x01 150 #define ATA_BMSTAT_ERROR 0x02 151 #define ATA_BMSTAT_INTERRUPT 0x04 152 #define ATA_BMSTAT_MASK 0x07 153 #define ATA_BMSTAT_DMA_MASTER 0x20 154 #define ATA_BMSTAT_DMA_SLAVE 0x40 155 #define ATA_BMSTAT_DMA_SIMPLEX 0x80 156 157 #define ATA_BMDEVSPEC_1 0x03 158 #define ATA_BMDTP_PORT 0x04 159 160 /* structure for holding DMA address data */ 161 struct ata_dmaentry { 162 u_int32_t base; 163 u_int32_t count; 164 }; 165 166 struct ata_dmastate { 167 bus_dma_tag_t ddmatag; /* data DMA tag */ 168 bus_dmamap_t ddmamap; /* data DMA map */ 169 bus_dma_tag_t cdmatag; /* control DMA tag */ 170 bus_dmamap_t cdmamap; /* control DMA map */ 171 struct ata_dmaentry *dmatab; /* DMA transfer table */ 172 bus_addr_t mdmatab; /* bus address of dmatab */ 173 int flags; /* debugging */ 174 #define ATA_DS_ACTIVE 0x01 /* debugging */ 175 #define ATA_DS_READ 0x02 /* transaction is a read */ 176 }; 177 178 /* structure describing an ATA/ATAPI device */ 179 struct ata_device { 180 struct ata_channel *channel; 181 int unit; /* unit number */ 182 #define ATA_MASTER 0x00 183 #define ATA_SLAVE 0x10 184 185 char *name; /* device name */ 186 struct ata_params *param; /* ata param structure */ 187 void *driver; /* ptr to driver for device */ 188 int flags; 189 #define ATA_D_USE_CHS 0x0001 190 #define ATA_D_DETACHING 0x0002 191 #define ATA_D_MEDIA_CHANGED 0x0004 192 #define ATA_D_ENC_PRESENT 0x0008 193 194 int cmd; /* last cmd executed */ 195 void *result; /* misc data */ 196 int mode; /* transfermode */ 197 void (*setmode)(struct ata_device *, int); 198 struct ata_dmastate dmastate; /* dma state */ 199 }; 200 201 /* structure holding DMA function pointers */ 202 struct ata_dma_funcs { 203 void (*create)(struct ata_channel *); 204 void (*destroy)(struct ata_channel *); 205 int (*alloc)(struct ata_device *); 206 void (*free)(struct ata_device *); 207 int (*setup)(struct ata_device *, caddr_t, int32_t); 208 int (*start)(struct ata_device *, caddr_t, int32_t, int); 209 int (*stop)(struct ata_device *); 210 int (*status)(struct ata_channel *); 211 u_int32_t alignment; /* dma engine alignment */ 212 }; 213 214 /* structure describing an ATA channel */ 215 struct ata_channel { 216 struct device *dev; /* device handle */ 217 int unit; /* channel number */ 218 struct resource *r_io; /* io addr resource handle */ 219 struct resource *r_altio; /* altio addr resource handle */ 220 struct resource *r_bmio; /* bmio addr resource handle */ 221 bus_dma_tag_t dmatag; /* parent dma tag */ 222 struct resource *r_irq; /* interrupt of this channel */ 223 void *ih; /* interrupt handle */ 224 struct ata_dma_funcs *dma; /* DMA functions */ 225 u_int32_t chiptype; /* controller chip PCI id */ 226 int flags; /* channel flags */ 227 #define ATA_NO_SLAVE 0x01 228 #define ATA_USE_16BIT 0x02 229 #define ATA_USE_PC98GEOM 0x04 230 #define ATA_ATAPI_DMA_RO 0x08 231 #define ATA_QUEUED 0x10 232 #define ATA_DMA_ACTIVE 0x20 233 #define ATA_48BIT_ACTIVE 0x40 234 235 struct ata_device device[2]; /* devices on this channel */ 236 #define MASTER 0x00 237 #define SLAVE 0x01 238 239 int devices; /* what is present */ 240 #define ATA_ATA_MASTER 0x01 241 #define ATA_ATA_SLAVE 0x02 242 #define ATA_ATAPI_MASTER 0x04 243 #define ATA_ATAPI_SLAVE 0x08 244 245 u_int8_t status; /* last controller status */ 246 u_int8_t error; /* last controller error */ 247 int active; /* ATA channel state control */ 248 #define ATA_IDLE 0x0000 249 #define ATA_IMMEDIATE 0x0001 250 #define ATA_WAIT_INTR 0x0002 251 #define ATA_WAIT_READY 0x0004 252 #define ATA_WAIT_MASK 0x0007 253 #define ATA_ACTIVE 0x0010 254 #define ATA_ACTIVE_ATA 0x0020 255 #define ATA_ACTIVE_ATAPI 0x0040 256 #define ATA_CONTROL 0x0080 257 258 void (*locking)(struct ata_channel *, int); 259 #define ATA_LF_LOCK 0x0001 260 #define ATA_LF_UNLOCK 0x0002 261 262 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */ 263 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */ 264 void *running; /* currently running request */ 265 }; 266 267 /* disk bay/enclosure related */ 268 #define ATA_LED_OFF 0x00 269 #define ATA_LED_RED 0x01 270 #define ATA_LED_GREEN 0x02 271 #define ATA_LED_ORANGE 0x03 272 #define ATA_LED_MASK 0x03 273 274 /* externs */ 275 extern devclass_t ata_devclass; 276 extern struct intr_config_hook *ata_delayed_attach; 277 278 /* public prototypes */ 279 int ata_probe(device_t); 280 int ata_attach(device_t); 281 int ata_detach(device_t); 282 int ata_resume(device_t); 283 void ata_start(struct ata_channel *); 284 void ata_reset(struct ata_channel *); 285 int ata_reinit(struct ata_channel *); 286 int ata_wait(struct ata_device *, u_int8_t); 287 int ata_command(struct ata_device *, u_int8_t, u_int64_t, u_int16_t, u_int16_t, int); 288 void ata_enclosure_leds(struct ata_device *, u_int8_t); 289 void ata_enclosure_print(struct ata_device *); 290 int ata_printf(struct ata_channel *, int, const char *, ...) __printflike(3, 4); 291 int ata_prtdev(struct ata_device *, const char *, ...) __printflike(2, 3); 292 void ata_set_name(struct ata_device *, char *, int); 293 void ata_free_name(struct ata_device *); 294 int ata_get_lun(u_int32_t *); 295 int ata_test_lun(u_int32_t *, int); 296 void ata_free_lun(u_int32_t *, int); 297 char *ata_mode2str(int); 298 int ata_pmode(struct ata_params *); 299 int ata_wmode(struct ata_params *); 300 int ata_umode(struct ata_params *); 301 int ata_limit_mode(struct ata_device *, int, int); 302 303 /* macros for locking a channel */ 304 #define ATA_LOCK_CH(ch, value) \ 305 atomic_cmpset_acq_int(&(ch)->active, ATA_IDLE, (value)) 306 307 #define ATA_SLEEPLOCK_CH(ch, value) \ 308 while (!atomic_cmpset_acq_int(&(ch)->active, ATA_IDLE, (value))) \ 309 tsleep((caddr_t)&(ch), PRIBIO, "atalck", 1); 310 311 #define ATA_FORCELOCK_CH(ch, value) atomic_store_rel_int(&(ch)->active, (value)) 312 313 #define ATA_UNLOCK_CH(ch) atomic_store_rel_int(&(ch)->active, ATA_IDLE) 314 315 /* macros to hide busspace uglyness */ 316 #define ATA_INB(res, offset) \ 317 bus_space_read_1(rman_get_bustag((res)), \ 318 rman_get_bushandle((res)), (offset)) 319 #define ATA_INW(res, offset) \ 320 bus_space_read_2(rman_get_bustag((res)), \ 321 rman_get_bushandle((res)), (offset)) 322 #define ATA_INL(res, offset) \ 323 bus_space_read_4(rman_get_bustag((res)), \ 324 rman_get_bushandle((res)), (offset)) 325 #define ATA_INSW(res, offset, addr, count) \ 326 bus_space_read_multi_2(rman_get_bustag((res)), \ 327 rman_get_bushandle((res)), \ 328 (offset), (addr), (count)) 329 #define ATA_INSW_STRM(res, offset, addr, count) \ 330 bus_space_read_multi_stream_2(rman_get_bustag((res)), \ 331 rman_get_bushandle((res)), \ 332 (offset), (addr), (count)) 333 #define ATA_INSL(res, offset, addr, count) \ 334 bus_space_read_multi_4(rman_get_bustag((res)), \ 335 rman_get_bushandle((res)), \ 336 (offset), (addr), (count)) 337 #define ATA_INSL_STRM(res, offset, addr, count) \ 338 bus_space_read_multi_stream_4(rman_get_bustag((res)), \ 339 rman_get_bushandle((res)), \ 340 (offset), (addr), (count)) 341 #define ATA_OUTB(res, offset, value) \ 342 bus_space_write_1(rman_get_bustag((res)), \ 343 rman_get_bushandle((res)), (offset), (value)) 344 #define ATA_OUTW(res, offset, value) \ 345 bus_space_write_2(rman_get_bustag((res)), \ 346 rman_get_bushandle((res)), (offset), (value)) 347 #define ATA_OUTL(res, offset, value) \ 348 bus_space_write_4(rman_get_bustag((res)), \ 349 rman_get_bushandle((res)), (offset), (value)) 350 #define ATA_OUTSW(res, offset, addr, count) \ 351 bus_space_write_multi_2(rman_get_bustag((res)), \ 352 rman_get_bushandle((res)), \ 353 (offset), (addr), (count)) 354 #define ATA_OUTSW_STRM(res, offset, addr, count) \ 355 bus_space_write_multi_stream_2(rman_get_bustag((res)), \ 356 rman_get_bushandle((res)), \ 357 (offset), (addr), (count)) 358 #define ATA_OUTSL(res, offset, addr, count) \ 359 bus_space_write_multi_4(rman_get_bustag((res)), \ 360 rman_get_bushandle((res)), \ 361 (offset), (addr), (count)) 362 #define ATA_OUTSL_STRM(res, offset, addr, count) \ 363 bus_space_write_multi_stream_4(rman_get_bustag((res)), \ 364 rman_get_bushandle((res)), \ 365 (offset), (addr), (count)) 366