1 /*- 2 * Copyright (c) 1998 - 2003 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* ATA register defines */ 32 #define ATA_DATA 0x00 /* data register */ 33 34 #define ATA_ERROR 0x01 /* (R) error register */ 35 #define ATA_E_ILI 0x01 /* illegal length */ 36 #define ATA_E_NM 0x02 /* no media */ 37 #define ATA_E_ABORT 0x04 /* command aborted */ 38 #define ATA_E_MCR 0x08 /* media change request */ 39 #define ATA_E_IDNF 0x10 /* ID not found */ 40 #define ATA_E_MC 0x20 /* media changed */ 41 #define ATA_E_UNC 0x40 /* uncorrectable data */ 42 #define ATA_E_ICRC 0x80 /* UDMA crc error */ 43 #define ATA_E_MASK 0x0f /* error mask */ 44 #define ATA_SK_MASK 0xf0 /* sense key mask */ 45 #define ATA_SK_NO_SENSE 0x00 /* no specific sense key info */ 46 #define ATA_SK_RECOVERED_ERROR 0x10 /* command OK, data recovered */ 47 #define ATA_SK_NOT_READY 0x20 /* no access to drive */ 48 #define ATA_SK_MEDIUM_ERROR 0x30 /* non-recovered data error */ 49 #define ATA_SK_HARDWARE_ERROR 0x40 /* non-recoverable HW failure */ 50 #define ATA_SK_ILLEGAL_REQUEST 0x50 /* invalid command param(s) */ 51 #define ATA_SK_UNIT_ATTENTION 0x60 /* media changed */ 52 #define ATA_SK_DATA_PROTECT 0x70 /* write protect */ 53 #define ATA_SK_BLANK_CHECK 0x80 /* blank check */ 54 #define ATA_SK_VENDOR_SPECIFIC 0x90 /* vendor specific skey */ 55 #define ATA_SK_COPY_ABORTED 0xa0 /* copy aborted */ 56 #define ATA_SK_ABORTED_COMMAND 0xb0 /* command aborted, try again */ 57 #define ATA_SK_EQUAL 0xc0 /* equal */ 58 #define ATA_SK_VOLUME_OVERFLOW 0xd0 /* volume overflow */ 59 #define ATA_SK_MISCOMPARE 0xe0 /* data dont match the medium */ 60 #define ATA_SK_RESERVED 0xf0 61 62 #define ATA_FEATURE 0x01 /* (W) feature register */ 63 #define ATA_F_DMA 0x01 /* enable DMA */ 64 #define ATA_F_OVL 0x02 /* enable overlap */ 65 66 #define ATA_COUNT 0x02 /* (W) sector count */ 67 #define ATA_IREASON 0x02 /* (R) interrupt reason */ 68 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 69 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 70 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 71 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 72 73 #define ATA_SECTOR 0x03 /* sector # */ 74 #define ATA_CYL_LSB 0x04 /* cylinder# LSB */ 75 #define ATA_CYL_MSB 0x05 /* cylinder# MSB */ 76 #define ATA_DRIVE 0x06 /* Sector/Drive/Head register */ 77 #define ATA_D_LBA 0x40 /* use LBA addressing */ 78 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 79 80 #define ATA_CMD 0x07 /* command register */ 81 82 #define ATA_STATUS 0x07 /* status register */ 83 #define ATA_S_ERROR 0x01 /* error */ 84 #define ATA_S_INDEX 0x02 /* index */ 85 #define ATA_S_CORR 0x04 /* data corrected */ 86 #define ATA_S_DRQ 0x08 /* data request */ 87 #define ATA_S_DSC 0x10 /* drive seek completed */ 88 #define ATA_S_SERVICE 0x10 /* drive needs service */ 89 #define ATA_S_DWF 0x20 /* drive write fault */ 90 #define ATA_S_DMA 0x20 /* DMA ready */ 91 #define ATA_S_READY 0x40 /* drive ready */ 92 #define ATA_S_BUSY 0x80 /* busy */ 93 94 #define ATA_ALTSTAT 0x08 /* alternate status register */ 95 #define ATA_ALTOFFSET 0x206 /* alternate registers offset */ 96 #define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */ 97 #define ATA_PC98_ALTOFFSET 0x10c /* do for PC98 devices */ 98 #define ATA_A_IDS 0x02 /* disable interrupts */ 99 #define ATA_A_RESET 0x04 /* RESET controller */ 100 #define ATA_A_4BIT 0x08 /* 4 head bits */ 101 102 /* ATAPI misc defines */ 103 #define ATAPI_MAGIC_LSB 0x14 104 #define ATAPI_MAGIC_MSB 0xeb 105 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 106 #define ATAPI_P_WRITE (ATA_S_DRQ) 107 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 108 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 109 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 110 #define ATAPI_P_ABORT 0 111 112 /* misc defines */ 113 #define ATA_PRIMARY 0x1f0 114 #define ATA_SECONDARY 0x170 115 #define ATA_PC98_BANK 0x432 116 #define ATA_IOSIZE 0x08 117 #define ATA_PC98_IOSIZE 0x10 118 #define ATA_ALTIOSIZE 0x01 119 #define ATA_BMIOSIZE 0x08 120 #define ATA_PC98_BANKIOSIZE 0x01 121 #define ATA_IOADDR_RID 0 122 #define ATA_ALTADDR_RID 1 123 #define ATA_BMADDR_RID 0x20 124 #define ATA_PC98_ALTADDR_RID 8 125 #define ATA_PC98_BANKADDR_RID 9 126 127 #define ATA_IRQ_RID 0 128 #define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1) 129 130 /* busmaster DMA related defines */ 131 #define ATA_DMA_ENTRIES 256 132 #define ATA_DMA_EOT 0x80000000 133 134 #define ATA_BMCMD_PORT 0x09 135 #define ATA_BMCMD_START_STOP 0x01 136 #define ATA_BMCMD_WRITE_READ 0x08 137 138 #define ATA_BMCTL_PORT 0x09 139 #define ATA_BMDEVSPEC_0 0x0a 140 #define ATA_BMSTAT_PORT 0x0b 141 #define ATA_BMSTAT_ACTIVE 0x01 142 #define ATA_BMSTAT_ERROR 0x02 143 #define ATA_BMSTAT_INTERRUPT 0x04 144 #define ATA_BMSTAT_MASK 0x07 145 #define ATA_BMSTAT_DMA_MASTER 0x20 146 #define ATA_BMSTAT_DMA_SLAVE 0x40 147 #define ATA_BMSTAT_DMA_SIMPLEX 0x80 148 149 #define ATA_BMDEVSPEC_1 0x0c 150 #define ATA_BMDTP_PORT 0x0d 151 152 #define ATA_IDX_ADDR 0x0e 153 #define ATA_IDX_DATA 0x0f 154 #define ATA_MAX_RES 0x10 155 156 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 157 #define ATA_OP_CONTINUES 0 158 #define ATA_OP_FINISHED 1 159 160 struct ata_request { 161 struct ata_device *device; /* ptr to device softc */ 162 void *driver; /* driver specific */ 163 164 union { 165 struct { 166 u_int8_t command; /* command reg */ 167 u_int8_t feature; /* feature reg */ 168 u_int64_t lba; /* lba reg */ 169 u_int16_t count; /* count reg */ 170 } ata; 171 struct { 172 u_int8_t ccb[16]; /* ATAPI command block */ 173 } atapi; 174 } u; 175 176 u_int8_t status; /* ATA status */ 177 u_int8_t error; /* ATA error */ 178 u_int8_t dmastat; /* DMA status */ 179 180 u_int32_t bytecount; /* bytes to transfer */ 181 u_int32_t transfersize; /* bytes pr transfer */ 182 u_int32_t donecount; /* bytes transferred */ 183 caddr_t data; /* pointer to data buf */ 184 int flags; 185 #define ATA_R_DONE 0x0001 186 #define ATA_R_CONTROL 0x0002 187 #define ATA_R_READ 0x0004 188 #define ATA_R_WRITE 0x0008 189 190 #define ATA_R_ATAPI 0x0010 191 #define ATA_R_QUIET 0x0020 192 #define ATA_R_DMA 0x0040 193 194 #define ATA_R_ORDERED 0x0100 195 #define ATA_R_AT_HEAD 0x0200 196 #define ATA_R_REQUEUE 0x0400 197 #define ATA_R_SKIPSTART 0x0800 198 199 void (*callback)(struct ata_request *request); 200 int retries; /* retry count */ 201 int timeout; /* timeout for this cmd */ 202 struct callout_handle timeout_handle; /* handle for untimeout */ 203 int result; /* result error code */ 204 struct task task; /* task management */ 205 TAILQ_ENTRY(ata_request) sequence; /* sequence management */ 206 TAILQ_ENTRY(ata_request) chain; /* list management */ 207 }; 208 209 /* structure describing an ATA/ATAPI device */ 210 struct ata_device { 211 struct ata_channel *channel; 212 int unit; /* unit number */ 213 #define ATA_MASTER 0x00 214 #define ATA_SLAVE 0x10 215 216 char *name; /* device name */ 217 struct ata_params *param; /* ata param structure */ 218 void *softc; /* ptr to softc for device */ 219 void (*attach)(struct ata_device *atadev); 220 void (*detach)(struct ata_device *atadev); 221 void (*start)(struct ata_device *atadev); 222 int flags; 223 #define ATA_D_USE_CHS 0x0001 224 #define ATA_D_DETACHING 0x0002 225 #define ATA_D_MEDIA_CHANGED 0x0004 226 #define ATA_D_ENC_PRESENT 0x0008 227 228 int cmd; /* last cmd executed */ 229 int mode; /* transfermode */ 230 void (*setmode)(struct ata_device *atadev, int mode); 231 }; 232 233 /* structure for holding DMA address data */ 234 struct ata_dmaentry { 235 u_int32_t base; 236 u_int32_t count; 237 }; 238 239 /* structure holding DMA related information */ 240 struct ata_dma { 241 bus_dma_tag_t dmatag; /* parent DMA tag */ 242 bus_dma_tag_t cdmatag; /* control DMA tag */ 243 bus_dmamap_t cdmamap; /* control DMA map */ 244 bus_dma_tag_t ddmatag; /* data DMA tag */ 245 bus_dmamap_t ddmamap; /* data DMA map */ 246 struct ata_dmaentry *dmatab; /* DMA transfer table */ 247 bus_addr_t mdmatab; /* bus address of dmatab */ 248 u_int32_t alignment; /* DMA engine alignment */ 249 u_int32_t max_iosize; /* DMA engine max IO size */ 250 u_int32_t cur_iosize; /* DMA engine current IO size */ 251 int flags; 252 #define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress */ 253 #define ATA_DMA_READ 0x02 /* transaction is a read */ 254 255 void (*alloc)(struct ata_channel *ch); 256 void (*free)(struct ata_channel *ch); 257 int (*load)(struct ata_device *atadev, caddr_t data, int32_t count,int dir); 258 int (*unload)(struct ata_channel *ch); 259 int (*start)(struct ata_channel *ch); 260 int (*stop)(struct ata_channel *ch); 261 }; 262 263 /* structure holding lowlevel functions */ 264 struct ata_lowlevel { 265 void (*reset)(struct ata_channel *ch); 266 int (*transaction)(struct ata_request *request); 267 void (*interrupt)(void *channel); 268 }; 269 270 /* structure holding resources for an ATA channel */ 271 struct ata_resource { 272 struct resource *res; 273 int offset; 274 }; 275 276 /* structure describing an ATA channel */ 277 struct ata_channel { 278 struct device *dev; /* device handle */ 279 int unit; /* channel number */ 280 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ 281 struct resource *r_irq; /* interrupt of this channel */ 282 void *ih; /* interrupt handle */ 283 struct ata_lowlevel hw; /* lowlevel HW functions */ 284 struct ata_dma *dma; /* DMA data / functions */ 285 int flags; /* channel flags */ 286 #define ATA_NO_SLAVE 0x01 287 #define ATA_USE_16BIT 0x02 288 #define ATA_USE_PC98GEOM 0x04 289 #define ATA_ATAPI_DMA_RO 0x08 290 #define ATA_48BIT_ACTIVE 0x10 291 292 struct ata_device device[2]; /* devices on this channel */ 293 #define MASTER 0x00 294 #define SLAVE 0x01 295 296 int devices; /* what is present */ 297 #define ATA_ATA_MASTER 0x01 298 #define ATA_ATA_SLAVE 0x02 299 #define ATA_ATAPI_MASTER 0x04 300 #define ATA_ATAPI_SLAVE 0x08 301 302 int state; /* ATA channel state control */ 303 #define ATA_IDLE 0x0000 304 #define ATA_ACTIVE 0x0001 305 #define ATA_CONTROL 0x0002 306 307 void (*locking)(struct ata_channel *, int); 308 #define ATA_LF_LOCK 0x0001 309 #define ATA_LF_UNLOCK 0x0002 310 311 struct mtx queue_mtx; 312 TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */ 313 void *running; /* currently running request */ 314 }; 315 316 /* ATAPI request sense structure */ 317 struct atapi_sense { 318 u_int8_t error_code :7; /* current or deferred errors */ 319 u_int8_t valid :1; /* follows ATAPI spec */ 320 u_int8_t segment; /* Segment number */ 321 u_int8_t sense_key :4; /* sense key */ 322 u_int8_t reserved2_4 :1; /* reserved */ 323 u_int8_t ili :1; /* incorrect length indicator */ 324 u_int8_t eom :1; /* end of medium */ 325 u_int8_t filemark :1; /* filemark */ 326 u_int32_t cmd_info __packed; /* cmd information */ 327 u_int8_t sense_length; /* additional sense len (n-7) */ 328 u_int32_t cmd_specific_info __packed; /* additional cmd spec info */ 329 u_int8_t asc; /* additional sense code */ 330 u_int8_t ascq; /* additional sense code qual */ 331 u_int8_t replaceable_unit_code; /* replaceable unit code */ 332 u_int8_t sk_specific :7; /* sense key specific */ 333 u_int8_t sksv :1; /* sense key specific info OK */ 334 u_int8_t sk_specific1; /* sense key specific */ 335 u_int8_t sk_specific2; /* sense key specific */ 336 }; 337 338 /* disk bay/enclosure related */ 339 #define ATA_LED_OFF 0x00 340 #define ATA_LED_RED 0x01 341 #define ATA_LED_GREEN 0x02 342 #define ATA_LED_ORANGE 0x03 343 #define ATA_LED_MASK 0x03 344 345 /* externs */ 346 extern devclass_t ata_devclass; 347 extern struct intr_config_hook *ata_delayed_attach; 348 extern int ata_dma, ata_wc, atapi_dma; 349 350 /* public prototypes */ 351 /* ata-all.c: */ 352 int ata_probe(device_t dev); 353 int ata_attach(device_t dev); 354 int ata_detach(device_t dev); 355 int ata_suspend(device_t dev); 356 int ata_resume(device_t dev); 357 int ata_printf(struct ata_channel *ch, int device, const char *fmt, ...) __printflike(3, 4); 358 int ata_prtdev(struct ata_device *atadev, const char *fmt, ...) __printflike(2, 3); 359 void ata_set_name(struct ata_device *atadev, char *name, int lun); 360 void ata_free_name(struct ata_device *atadev); 361 int ata_get_lun(u_int32_t *map); 362 int ata_test_lun(u_int32_t *map, int lun); 363 void ata_free_lun(u_int32_t *map, int lun); 364 char *ata_mode2str(int mode); 365 int ata_pmode(struct ata_params *ap); 366 int ata_wmode(struct ata_params *ap); 367 int ata_umode(struct ata_params *ap); 368 int ata_limit_mode(struct ata_device *atadev, int mode, int maxmode); 369 370 /* ata-queue.c: */ 371 int ata_reinit(struct ata_channel *ch); 372 void ata_start(struct ata_channel *ch); 373 struct ata_request *ata_alloc_request(void); 374 void ata_free_request(struct ata_request *request); 375 int ata_controlcmd(struct ata_device *atadev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count); 376 int ata_atapicmd(struct ata_device *atadev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout); 377 void ata_queue_request(struct ata_request *request); 378 void ata_finish(struct ata_request *request); 379 char *ata_cmd2str(struct ata_request *request); 380 381 /* ata-lowlevel.c: */ 382 void ata_generic_hw(struct ata_channel *ch); 383 384 /* subdrivers */ 385 void ad_attach(struct ata_device *atadev); 386 void acd_attach(struct ata_device *atadev); 387 void afd_attach(struct ata_device *atadev); 388 void ast_attach(struct ata_device *atadev); 389 void atapi_cam_attach_bus(struct ata_channel *ch); 390 void atapi_cam_detach_bus(struct ata_channel *ch); 391 void atapi_cam_reinit_bus(struct ata_channel *ch); 392 393 /* macros for locking a channel */ 394 #define ATA_LOCK_CH(ch, value) \ 395 atomic_cmpset_acq_int(&(ch)->state, ATA_IDLE, (value)) 396 397 #define ATA_SLEEPLOCK_CH(ch, value) \ 398 while (!atomic_cmpset_acq_int(&(ch)->state, ATA_IDLE, (value))) \ 399 tsleep((caddr_t)&(ch), PRIBIO, "atalck", 1); 400 401 #define ATA_FORCELOCK_CH(ch, value) atomic_store_rel_int(&(ch)->state, (value)) 402 403 #define ATA_UNLOCK_CH(ch) atomic_store_rel_int(&(ch)->state, ATA_IDLE) 404 405 /* macros to hide busspace uglyness */ 406 #define ATA_INB(res, offset) \ 407 bus_space_read_1(rman_get_bustag((res)), \ 408 rman_get_bushandle((res)), (offset)) 409 410 #define ATA_INW(res, offset) \ 411 bus_space_read_2(rman_get_bustag((res)), \ 412 rman_get_bushandle((res)), (offset)) 413 #define ATA_INL(res, offset) \ 414 bus_space_read_4(rman_get_bustag((res)), \ 415 rman_get_bushandle((res)), (offset)) 416 #define ATA_INSW(res, offset, addr, count) \ 417 bus_space_read_multi_2(rman_get_bustag((res)), \ 418 rman_get_bushandle((res)), \ 419 (offset), (addr), (count)) 420 #define ATA_INSW_STRM(res, offset, addr, count) \ 421 bus_space_read_multi_stream_2(rman_get_bustag((res)), \ 422 rman_get_bushandle((res)), \ 423 (offset), (addr), (count)) 424 #define ATA_INSL(res, offset, addr, count) \ 425 bus_space_read_multi_4(rman_get_bustag((res)), \ 426 rman_get_bushandle((res)), \ 427 (offset), (addr), (count)) 428 #define ATA_INSL_STRM(res, offset, addr, count) \ 429 bus_space_read_multi_stream_4(rman_get_bustag((res)), \ 430 rman_get_bushandle((res)), \ 431 (offset), (addr), (count)) 432 #define ATA_OUTB(res, offset, value) \ 433 bus_space_write_1(rman_get_bustag((res)), \ 434 rman_get_bushandle((res)), (offset), (value)) 435 #define ATA_OUTW(res, offset, value) \ 436 bus_space_write_2(rman_get_bustag((res)), \ 437 rman_get_bushandle((res)), (offset), (value)) 438 #define ATA_OUTL(res, offset, value) \ 439 bus_space_write_4(rman_get_bustag((res)), \ 440 rman_get_bushandle((res)), (offset), (value)) 441 #define ATA_OUTSW(res, offset, addr, count) \ 442 bus_space_write_multi_2(rman_get_bustag((res)), \ 443 rman_get_bushandle((res)), \ 444 (offset), (addr), (count)) 445 #define ATA_OUTSW_STRM(res, offset, addr, count) \ 446 bus_space_write_multi_stream_2(rman_get_bustag((res)), \ 447 rman_get_bushandle((res)), \ 448 (offset), (addr), (count)) 449 #define ATA_OUTSL(res, offset, addr, count) \ 450 bus_space_write_multi_4(rman_get_bustag((res)), \ 451 rman_get_bushandle((res)), \ 452 (offset), (addr), (count)) 453 #define ATA_OUTSL_STRM(res, offset, addr, count) \ 454 bus_space_write_multi_stream_4(rman_get_bustag((res)), \ 455 rman_get_bushandle((res)), \ 456 (offset), (addr), (count)) 457 458 #define ATA_IDX_SET(ch, idx) \ 459 ATA_OUTB(ch->r_io[ATA_IDX_ADDR].res, ch->r_io[ATA_IDX_ADDR].offset, \ 460 ch->r_io[idx].offset) 461 462 #define ATA_IDX_INB(ch, idx) \ 463 ((ch->r_io[idx].res) \ 464 ? ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) \ 465 : (ATA_IDX_SET(ch, idx), \ 466 ATA_INB(ch->r_io[ATA_IDX_DATA].res, ch->r_io[ATA_IDX_DATA].offset))) 467 468 #define ATA_IDX_INW(ch, idx) \ 469 ((ch->r_io[idx].res) \ 470 ? ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) \ 471 : (ATA_IDX_SET(ch, idx), \ 472 ATA_INW(ch->r_io[ATA_IDX_DATA].res, ch->r_io[ATA_IDX_DATA].offset))) 473 474 #define ATA_IDX_INL(ch, idx) \ 475 ((ch->r_io[idx].res) \ 476 ? ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) \ 477 : (ATA_IDX_SET(ch, idx), \ 478 ATA_INL(ch->r_io[ATA_IDX_DATA].res, ch->r_io[ATA_IDX_DATA].offset))) 479 480 #define ATA_IDX_INSW(ch, idx, addr, count) \ 481 ((ch->r_io[idx].res) \ 482 ? ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ 483 : (ATA_IDX_SET(ch, idx), \ 484 ATA_INSW(ch->r_io[ATA_IDX_DATA].res, \ 485 ch->r_io[ATA_IDX_DATA].offset, addr, count))) 486 487 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 488 ((ch->r_io[idx].res) \ 489 ? ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ 490 : (ATA_IDX_SET(ch, idx), \ 491 ATA_INSW_STRM(ch->r_io[ATA_IDX_DATA].res, \ 492 ch->r_io[ATA_IDX_DATA].offset, addr, count))) 493 494 #define ATA_IDX_INSL(ch, idx, addr, count) \ 495 ((ch->r_io[idx].res) \ 496 ? ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ 497 : (ATA_IDX_SET(ch, idx), \ 498 ATA_INSL(ch->r_io[ATA_IDX_DATA].res, \ 499 ch->r_io[ATA_IDX_DATA].offset, addr, count))) 500 501 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 502 ((ch->r_io[idx].res) \ 503 ? ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ 504 : (ATA_IDX_SET(ch, idx), \ 505 ATA_INSL_STRM(ch->r_io[ATA_IDX_DATA].res, \ 506 ch->r_io[ATA_IDX_DATA].offset, addr, count))) 507 508 #define ATA_IDX_OUTB(ch, idx, value) \ 509 ((ch->r_io[idx].res) \ 510 ? ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) \ 511 : (ATA_IDX_SET(ch, idx), \ 512 ATA_OUTB(ch->r_io[ATA_IDX_DATA].res, \ 513 ch->r_io[ATA_IDX_DATA].offset, value))) 514 515 #define ATA_IDX_OUTW(ch, idx, value) \ 516 ((ch->r_io[idx].res) \ 517 ? ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) \ 518 : (ATA_IDX_SET(ch, idx), \ 519 ATA_OUTW(ch->r_io[ATA_IDX_DATA].res, \ 520 ch->r_io[ATA_IDX_DATA].offset, value))) 521 522 #define ATA_IDX_OUTL(ch, idx, value) \ 523 ((ch->r_io[idx].res) \ 524 ? ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) \ 525 : (ATA_IDX_SET(ch, idx), \ 526 ATA_OUTL(ch->r_io[ATA_IDX_DATA].res, \ 527 ch->r_io[ATA_IDX_DATA].offset, value))) 528 529 #define ATA_IDX_OUTSW(ch, idx, addr, count) \ 530 ((ch->r_io[idx].res) \ 531 ? ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ 532 : (ATA_IDX_SET(ch, idx), \ 533 ATA_OUTSW(ch->r_io[ATA_IDX_DATA].res, \ 534 ch->r_io[ATA_IDX_DATA].offset, addr, count))) 535 536 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 537 ((ch->r_io[idx].res) \ 538 ? ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ 539 : (ATA_IDX_SET(ch, idx), \ 540 ATA_OUTSW_STRM(ch->r_io[ATA_IDX_DATA].res, \ 541 ch->r_io[ATA_IDX_DATA].offset, addr, count))) 542 543 #define ATA_IDX_OUTSL(ch, idx, addr, count) \ 544 ((ch->r_io[idx].res) \ 545 ? ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ 546 : (ATA_IDX_SET(ch, idx), \ 547 ATA_OUTSL(ch->r_io[ATA_IDX_DATA].res, \ 548 ch->r_io[ATA_IDX_DATA].offset, addr, count))) 549 550 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 551 ((ch->r_io[idx].res) \ 552 ? ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ 553 : (ATA_IDX_SET(ch, idx), \ 554 ATA_OUTSL_STRM(ch->r_io[ATA_IDX_DATA].res, \ 555 ch->r_io[ATA_IDX_DATA].offset, addr, count))) 556