1 /*- 2 * Copyright (c) 1998 - 2004 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* ATA register defines */ 32 #define ATA_DATA 0x00 /* data register */ 33 34 #define ATA_ERROR 0x01 /* (R) error register */ 35 #define ATA_E_ILI 0x01 /* illegal length */ 36 #define ATA_E_NM 0x02 /* no media */ 37 #define ATA_E_ABORT 0x04 /* command aborted */ 38 #define ATA_E_MCR 0x08 /* media change request */ 39 #define ATA_E_IDNF 0x10 /* ID not found */ 40 #define ATA_E_MC 0x20 /* media changed */ 41 #define ATA_E_UNC 0x40 /* uncorrectable data */ 42 #define ATA_E_ICRC 0x80 /* UDMA crc error */ 43 #define ATA_E_MASK 0x0f /* error mask */ 44 #define ATA_SK_MASK 0xf0 /* sense key mask */ 45 #define ATA_SK_NO_SENSE 0x00 /* no specific sense key info */ 46 #define ATA_SK_RECOVERED_ERROR 0x10 /* command OK, data recovered */ 47 #define ATA_SK_NOT_READY 0x20 /* no access to drive */ 48 #define ATA_SK_MEDIUM_ERROR 0x30 /* non-recovered data error */ 49 #define ATA_SK_HARDWARE_ERROR 0x40 /* non-recoverable HW failure */ 50 #define ATA_SK_ILLEGAL_REQUEST 0x50 /* invalid command param(s) */ 51 #define ATA_SK_UNIT_ATTENTION 0x60 /* media changed */ 52 #define ATA_SK_DATA_PROTECT 0x70 /* write protect */ 53 #define ATA_SK_BLANK_CHECK 0x80 /* blank check */ 54 #define ATA_SK_VENDOR_SPECIFIC 0x90 /* vendor specific skey */ 55 #define ATA_SK_COPY_ABORTED 0xa0 /* copy aborted */ 56 #define ATA_SK_ABORTED_COMMAND 0xb0 /* command aborted, try again */ 57 #define ATA_SK_EQUAL 0xc0 /* equal */ 58 #define ATA_SK_VOLUME_OVERFLOW 0xd0 /* volume overflow */ 59 #define ATA_SK_MISCOMPARE 0xe0 /* data dont match the medium */ 60 #define ATA_SK_RESERVED 0xf0 61 62 #define ATA_FEATURE 0x01 /* (W) feature register */ 63 #define ATA_F_DMA 0x01 /* enable DMA */ 64 #define ATA_F_OVL 0x02 /* enable overlap */ 65 66 #define ATA_COUNT 0x02 /* (W) sector count */ 67 #define ATA_IREASON 0x02 /* (R) interrupt reason */ 68 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 69 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 70 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 71 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 72 73 #define ATA_SECTOR 0x03 /* sector # */ 74 #define ATA_CYL_LSB 0x04 /* cylinder# LSB */ 75 #define ATA_CYL_MSB 0x05 /* cylinder# MSB */ 76 #define ATA_DRIVE 0x06 /* Sector/Drive/Head register */ 77 #define ATA_D_LBA 0x40 /* use LBA addressing */ 78 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 79 80 #define ATA_CMD 0x07 /* command register */ 81 82 #define ATA_STATUS 0x07 /* status register */ 83 #define ATA_S_ERROR 0x01 /* error */ 84 #define ATA_S_INDEX 0x02 /* index */ 85 #define ATA_S_CORR 0x04 /* data corrected */ 86 #define ATA_S_DRQ 0x08 /* data request */ 87 #define ATA_S_DSC 0x10 /* drive seek completed */ 88 #define ATA_S_SERVICE 0x10 /* drive needs service */ 89 #define ATA_S_DWF 0x20 /* drive write fault */ 90 #define ATA_S_DMA 0x20 /* DMA ready */ 91 #define ATA_S_READY 0x40 /* drive ready */ 92 #define ATA_S_BUSY 0x80 /* busy */ 93 94 #define ATA_ALTSTAT 0x08 /* alternate status register */ 95 #define ATA_ALTOFFSET 0x206 /* alternate registers offset */ 96 #define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */ 97 #define ATA_PC98_ALTOFFSET 0x10c /* do for PC98 devices */ 98 #define ATA_A_IDS 0x02 /* disable interrupts */ 99 #define ATA_A_RESET 0x04 /* RESET controller */ 100 #define ATA_A_4BIT 0x08 /* 4 head bits */ 101 102 /* ATAPI misc defines */ 103 #define ATAPI_MAGIC_LSB 0x14 104 #define ATAPI_MAGIC_MSB 0xeb 105 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 106 #define ATAPI_P_WRITE (ATA_S_DRQ) 107 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 108 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 109 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 110 #define ATAPI_P_ABORT 0 111 112 /* misc defines */ 113 #define ATA_PRIMARY 0x1f0 114 #define ATA_SECONDARY 0x170 115 #define ATA_PC98_BANK 0x432 116 #define ATA_IOSIZE 0x08 117 #define ATA_PC98_IOSIZE 0x10 118 #define ATA_ALTIOSIZE 0x01 119 #define ATA_BMIOSIZE 0x08 120 #define ATA_PC98_BANKIOSIZE 0x01 121 #define ATA_IOADDR_RID 0 122 #define ATA_ALTADDR_RID 1 123 #define ATA_BMADDR_RID 0x20 124 #define ATA_PC98_ALTADDR_RID 8 125 #define ATA_PC98_BANKADDR_RID 9 126 127 #define ATA_IRQ_RID 0 128 #define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1) 129 130 /* busmaster DMA related defines */ 131 #define ATA_DMA_ENTRIES 256 132 #define ATA_DMA_EOT 0x80000000 133 134 #define ATA_BMCMD_PORT 0x09 135 #define ATA_BMCMD_START_STOP 0x01 136 #define ATA_BMCMD_WRITE_READ 0x08 137 138 #define ATA_BMCTL_PORT 0x09 139 #define ATA_BMDEVSPEC_0 0x0a 140 #define ATA_BMSTAT_PORT 0x0b 141 #define ATA_BMSTAT_ACTIVE 0x01 142 #define ATA_BMSTAT_ERROR 0x02 143 #define ATA_BMSTAT_INTERRUPT 0x04 144 #define ATA_BMSTAT_MASK 0x07 145 #define ATA_BMSTAT_DMA_MASTER 0x20 146 #define ATA_BMSTAT_DMA_SLAVE 0x40 147 #define ATA_BMSTAT_DMA_SIMPLEX 0x80 148 149 #define ATA_BMDEVSPEC_1 0x0c 150 #define ATA_BMDTP_PORT 0x0d 151 152 #define ATA_IDX_ADDR 0x0e 153 #define ATA_IDX_DATA 0x0f 154 #define ATA_MAX_RES 0x10 155 156 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 157 #define ATA_OP_CONTINUES 0 158 #define ATA_OP_FINISHED 1 159 160 struct ata_request { 161 struct ata_device *device; /* ptr to device softc */ 162 void *driver; /* driver specific */ 163 164 union { 165 struct { 166 u_int8_t command; /* command reg */ 167 u_int8_t feature; /* feature reg */ 168 u_int64_t lba; /* lba reg */ 169 u_int16_t count; /* count reg */ 170 } ata; 171 struct { 172 u_int8_t ccb[16]; /* ATAPI command block */ 173 } atapi; 174 } u; 175 176 u_int8_t status; /* ATA status */ 177 u_int8_t error; /* ATA error */ 178 u_int8_t dmastat; /* DMA status */ 179 180 u_int32_t bytecount; /* bytes to transfer */ 181 u_int32_t transfersize; /* bytes pr transfer */ 182 u_int32_t donecount; /* bytes transferred */ 183 caddr_t data; /* pointer to data buf */ 184 int flags; 185 #define ATA_R_CONTROL 0x0001 186 #define ATA_R_READ 0x0002 187 #define ATA_R_WRITE 0x0004 188 #define ATA_R_DMA 0x0008 189 190 #define ATA_R_ATAPI 0x0010 191 #define ATA_R_QUIET 0x0020 192 #define ATA_R_INTR_SEEN 0x0040 193 #define ATA_R_TIMEOUT 0x0080 194 195 #define ATA_R_ORDERED 0x0100 196 #define ATA_R_AT_HEAD 0x0200 197 #define ATA_R_REQUEUE 0x0400 198 #define ATA_R_SKIPSTART 0x0800 199 200 #define ATA_R_DEBUG 0x1000 201 202 void (*callback)(struct ata_request *request); 203 struct sema done; /* request done sema */ 204 int retries; /* retry count */ 205 int timeout; /* timeout for this cmd */ 206 struct callout_handle timeout_handle; /* handle for untimeout */ 207 int result; /* result error code */ 208 struct task task; /* task management */ 209 TAILQ_ENTRY(ata_request) sequence; /* sequence management */ 210 TAILQ_ENTRY(ata_request) chain; /* list management */ 211 }; 212 213 /* define this for debugging request processing */ 214 #if 0 215 #define ATA_DEBUG_RQ(request, string) \ 216 { \ 217 if (request->flags & ATA_R_DEBUG) \ 218 ata_prtdev(request->device, "req=%08x %s " string "\n", \ 219 (u_int)request, ata_cmd2str(request)); \ 220 } 221 #else 222 #define ATA_DEBUG_RQ(request, string) 223 #endif 224 225 226 /* structure describing an ATA/ATAPI device */ 227 struct ata_device { 228 struct ata_channel *channel; 229 int unit; /* unit number */ 230 #define ATA_MASTER 0x00 231 #define ATA_SLAVE 0x10 232 233 char *name; /* device name */ 234 struct ata_params *param; /* ata param structure */ 235 void *softc; /* ptr to softc for device */ 236 void (*attach)(struct ata_device *atadev); 237 void (*detach)(struct ata_device *atadev); 238 void (*config)(struct ata_device *atadev); 239 void (*start)(struct ata_device *atadev); 240 int flags; 241 #define ATA_D_USE_CHS 0x0001 242 #define ATA_D_DETACHING 0x0002 243 #define ATA_D_MEDIA_CHANGED 0x0004 244 #define ATA_D_ENC_PRESENT 0x0008 245 246 int cmd; /* last cmd executed */ 247 int mode; /* transfermode */ 248 void (*setmode)(struct ata_device *atadev, int mode); 249 }; 250 251 /* structure for holding DMA address data */ 252 struct ata_dmaentry { 253 u_int32_t base; 254 u_int32_t count; 255 }; 256 257 /* structure holding DMA related information */ 258 struct ata_dma { 259 bus_dma_tag_t dmatag; /* parent DMA tag */ 260 bus_dma_tag_t cdmatag; /* control DMA tag */ 261 bus_dmamap_t cdmamap; /* control DMA map */ 262 bus_dma_tag_t ddmatag; /* data DMA tag */ 263 bus_dmamap_t ddmamap; /* data DMA map */ 264 struct ata_dmaentry *dmatab; /* DMA transfer table */ 265 bus_addr_t mdmatab; /* bus address of dmatab */ 266 u_int32_t alignment; /* DMA engine alignment */ 267 u_int32_t boundary; /* DMA engine boundary */ 268 u_int32_t max_iosize; /* DMA engine max IO size */ 269 u_int32_t cur_iosize; /* DMA engine current IO size */ 270 int flags; 271 #define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress */ 272 #define ATA_DMA_READ 0x02 /* transaction is a read */ 273 274 void (*alloc)(struct ata_channel *ch); 275 void (*free)(struct ata_channel *ch); 276 int (*load)(struct ata_device *atadev, caddr_t data, int32_t count,int dir); 277 int (*unload)(struct ata_channel *ch); 278 int (*start)(struct ata_channel *ch); 279 int (*stop)(struct ata_channel *ch); 280 }; 281 282 /* structure holding lowlevel functions */ 283 struct ata_lowlevel { 284 void (*reset)(struct ata_channel *ch); 285 int (*transaction)(struct ata_request *request); 286 void (*interrupt)(void *channel); 287 }; 288 289 /* structure holding resources for an ATA channel */ 290 struct ata_resource { 291 struct resource *res; 292 int offset; 293 }; 294 295 /* structure describing an ATA channel */ 296 struct ata_channel { 297 struct device *dev; /* device handle */ 298 int unit; /* channel number */ 299 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ 300 struct resource *r_irq; /* interrupt of this channel */ 301 void *ih; /* interrupt handle */ 302 struct ata_lowlevel hw; /* lowlevel HW functions */ 303 struct ata_dma *dma; /* DMA data / functions */ 304 int flags; /* channel flags */ 305 #define ATA_NO_SLAVE 0x01 306 #define ATA_USE_16BIT 0x02 307 #define ATA_USE_PC98GEOM 0x04 308 #define ATA_ATAPI_DMA_RO 0x08 309 #define ATA_48BIT_ACTIVE 0x10 310 #define ATA_IMMEDIATE_MODE 0x20 311 312 struct ata_device device[2]; /* devices on this channel */ 313 #define MASTER 0x00 314 #define SLAVE 0x01 315 316 int devices; /* what is present */ 317 #define ATA_ATA_MASTER 0x01 318 #define ATA_ATA_SLAVE 0x02 319 #define ATA_ATAPI_MASTER 0x04 320 #define ATA_ATAPI_SLAVE 0x08 321 322 int state; /* ATA channel state control */ 323 #define ATA_IDLE 0x0000 324 #define ATA_ACTIVE 0x0001 325 #define ATA_CONTROL 0x0002 326 327 void (*reset)(struct ata_channel *); 328 void (*locking)(struct ata_channel *, int); 329 #define ATA_LF_LOCK 0x0001 330 #define ATA_LF_UNLOCK 0x0002 331 332 struct mtx queue_mtx; /* queue lock */ 333 TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */ 334 void *running; /* currently running request */ 335 }; 336 337 /* ATAPI request sense structure */ 338 struct atapi_sense { 339 u_int8_t error_code :7; /* current or deferred errors */ 340 u_int8_t valid :1; /* follows ATAPI spec */ 341 u_int8_t segment; /* Segment number */ 342 u_int8_t sense_key :4; /* sense key */ 343 u_int8_t reserved2_4 :1; /* reserved */ 344 u_int8_t ili :1; /* incorrect length indicator */ 345 u_int8_t eom :1; /* end of medium */ 346 u_int8_t filemark :1; /* filemark */ 347 u_int32_t cmd_info __packed; /* cmd information */ 348 u_int8_t sense_length; /* additional sense len (n-7) */ 349 u_int32_t cmd_specific_info __packed; /* additional cmd spec info */ 350 u_int8_t asc; /* additional sense code */ 351 u_int8_t ascq; /* additional sense code qual */ 352 u_int8_t replaceable_unit_code; /* replaceable unit code */ 353 u_int8_t sk_specific :7; /* sense key specific */ 354 u_int8_t sksv :1; /* sense key specific info OK */ 355 u_int8_t sk_specific1; /* sense key specific */ 356 u_int8_t sk_specific2; /* sense key specific */ 357 }; 358 359 /* disk bay/enclosure related */ 360 #define ATA_LED_OFF 0x00 361 #define ATA_LED_RED 0x01 362 #define ATA_LED_GREEN 0x02 363 #define ATA_LED_ORANGE 0x03 364 #define ATA_LED_MASK 0x03 365 366 /* externs */ 367 extern devclass_t ata_devclass; 368 extern int ata_wc; 369 370 /* public prototypes */ 371 /* ata-all.c: */ 372 int ata_probe(device_t dev); 373 int ata_attach(device_t dev); 374 int ata_detach(device_t dev); 375 int ata_suspend(device_t dev); 376 int ata_resume(device_t dev); 377 int ata_printf(struct ata_channel *ch, int device, const char *fmt, ...) __printflike(3, 4); 378 int ata_prtdev(struct ata_device *atadev, const char *fmt, ...) __printflike(2, 3); 379 void ata_set_name(struct ata_device *atadev, char *name, int lun); 380 void ata_free_name(struct ata_device *atadev); 381 int ata_get_lun(u_int32_t *map); 382 int ata_test_lun(u_int32_t *map, int lun); 383 void ata_free_lun(u_int32_t *map, int lun); 384 char *ata_mode2str(int mode); 385 int ata_pmode(struct ata_params *ap); 386 int ata_wmode(struct ata_params *ap); 387 int ata_umode(struct ata_params *ap); 388 int ata_limit_mode(struct ata_device *atadev, int mode, int maxmode); 389 390 /* ata-queue.c: */ 391 int ata_reinit(struct ata_channel *ch); 392 void ata_start(struct ata_channel *ch); 393 int ata_controlcmd(struct ata_device *atadev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count); 394 int ata_atapicmd(struct ata_device *atadev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout); 395 void ata_queue_request(struct ata_request *request); 396 void ata_finish(struct ata_request *request); 397 char *ata_cmd2str(struct ata_request *request); 398 399 /* ata-lowlevel.c: */ 400 void ata_generic_hw(struct ata_channel *ch); 401 402 /* subdrivers */ 403 void ad_attach(struct ata_device *atadev); 404 void acd_attach(struct ata_device *atadev); 405 void afd_attach(struct ata_device *atadev); 406 void ast_attach(struct ata_device *atadev); 407 void atapi_cam_attach_bus(struct ata_channel *ch); 408 void atapi_cam_detach_bus(struct ata_channel *ch); 409 void atapi_cam_reinit_bus(struct ata_channel *ch); 410 411 /* macros for alloc/free of ata_requests */ 412 extern uma_zone_t ata_zone; 413 #define ata_alloc_request() uma_zalloc(ata_zone, M_NOWAIT | M_ZERO) 414 #define ata_free_request(request) uma_zfree(ata_zone, request) 415 416 /* macros for locking a channel */ 417 #define ATA_LOCK_CH(ch, value) \ 418 atomic_cmpset_acq_int(&(ch)->state, ATA_IDLE, (value)) 419 420 #define ATA_SLEEPLOCK_CH(ch, value) \ 421 while (!atomic_cmpset_acq_int(&(ch)->state, ATA_IDLE, (value))) \ 422 tsleep((caddr_t)&(ch), PRIBIO, "atalck", 1); 423 424 #define ATA_FORCELOCK_CH(ch, value) atomic_store_rel_int(&(ch)->state, (value)) 425 426 #define ATA_UNLOCK_CH(ch) atomic_store_rel_int(&(ch)->state, ATA_IDLE) 427 428 /* macros to hide busspace uglyness */ 429 #define ATA_INB(res, offset) \ 430 bus_space_read_1(rman_get_bustag((res)), \ 431 rman_get_bushandle((res)), (offset)) 432 433 #define ATA_INW(res, offset) \ 434 bus_space_read_2(rman_get_bustag((res)), \ 435 rman_get_bushandle((res)), (offset)) 436 #define ATA_INL(res, offset) \ 437 bus_space_read_4(rman_get_bustag((res)), \ 438 rman_get_bushandle((res)), (offset)) 439 #define ATA_INSW(res, offset, addr, count) \ 440 bus_space_read_multi_2(rman_get_bustag((res)), \ 441 rman_get_bushandle((res)), \ 442 (offset), (addr), (count)) 443 #define ATA_INSW_STRM(res, offset, addr, count) \ 444 bus_space_read_multi_stream_2(rman_get_bustag((res)), \ 445 rman_get_bushandle((res)), \ 446 (offset), (addr), (count)) 447 #define ATA_INSL(res, offset, addr, count) \ 448 bus_space_read_multi_4(rman_get_bustag((res)), \ 449 rman_get_bushandle((res)), \ 450 (offset), (addr), (count)) 451 #define ATA_INSL_STRM(res, offset, addr, count) \ 452 bus_space_read_multi_stream_4(rman_get_bustag((res)), \ 453 rman_get_bushandle((res)), \ 454 (offset), (addr), (count)) 455 #define ATA_OUTB(res, offset, value) \ 456 bus_space_write_1(rman_get_bustag((res)), \ 457 rman_get_bushandle((res)), (offset), (value)) 458 #define ATA_OUTW(res, offset, value) \ 459 bus_space_write_2(rman_get_bustag((res)), \ 460 rman_get_bushandle((res)), (offset), (value)) 461 #define ATA_OUTL(res, offset, value) \ 462 bus_space_write_4(rman_get_bustag((res)), \ 463 rman_get_bushandle((res)), (offset), (value)) 464 #define ATA_OUTSW(res, offset, addr, count) \ 465 bus_space_write_multi_2(rman_get_bustag((res)), \ 466 rman_get_bushandle((res)), \ 467 (offset), (addr), (count)) 468 #define ATA_OUTSW_STRM(res, offset, addr, count) \ 469 bus_space_write_multi_stream_2(rman_get_bustag((res)), \ 470 rman_get_bushandle((res)), \ 471 (offset), (addr), (count)) 472 #define ATA_OUTSL(res, offset, addr, count) \ 473 bus_space_write_multi_4(rman_get_bustag((res)), \ 474 rman_get_bushandle((res)), \ 475 (offset), (addr), (count)) 476 #define ATA_OUTSL_STRM(res, offset, addr, count) \ 477 bus_space_write_multi_stream_4(rman_get_bustag((res)), \ 478 rman_get_bushandle((res)), \ 479 (offset), (addr), (count)) 480 481 #define ATA_IDX_SET(ch, idx) \ 482 ATA_OUTB(ch->r_io[ATA_IDX_ADDR].res, ch->r_io[ATA_IDX_ADDR].offset, \ 483 ch->r_io[idx].offset) 484 485 #define ATA_IDX_INB(ch, idx) \ 486 ((ch->r_io[idx].res) \ 487 ? ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) \ 488 : (ATA_IDX_SET(ch, idx), \ 489 ATA_INB(ch->r_io[ATA_IDX_DATA].res, ch->r_io[ATA_IDX_DATA].offset))) 490 491 #define ATA_IDX_INW(ch, idx) \ 492 ((ch->r_io[idx].res) \ 493 ? ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) \ 494 : (ATA_IDX_SET(ch, idx), \ 495 ATA_INW(ch->r_io[ATA_IDX_DATA].res, ch->r_io[ATA_IDX_DATA].offset))) 496 497 #define ATA_IDX_INL(ch, idx) \ 498 ((ch->r_io[idx].res) \ 499 ? ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) \ 500 : (ATA_IDX_SET(ch, idx), \ 501 ATA_INL(ch->r_io[ATA_IDX_DATA].res, ch->r_io[ATA_IDX_DATA].offset))) 502 503 #define ATA_IDX_INSW(ch, idx, addr, count) \ 504 ((ch->r_io[idx].res) \ 505 ? ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ 506 : (ATA_IDX_SET(ch, idx), \ 507 ATA_INSW(ch->r_io[ATA_IDX_DATA].res, \ 508 ch->r_io[ATA_IDX_DATA].offset, addr, count))) 509 510 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 511 ((ch->r_io[idx].res) \ 512 ? ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ 513 : (ATA_IDX_SET(ch, idx), \ 514 ATA_INSW_STRM(ch->r_io[ATA_IDX_DATA].res, \ 515 ch->r_io[ATA_IDX_DATA].offset, addr, count))) 516 517 #define ATA_IDX_INSL(ch, idx, addr, count) \ 518 ((ch->r_io[idx].res) \ 519 ? ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ 520 : (ATA_IDX_SET(ch, idx), \ 521 ATA_INSL(ch->r_io[ATA_IDX_DATA].res, \ 522 ch->r_io[ATA_IDX_DATA].offset, addr, count))) 523 524 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 525 ((ch->r_io[idx].res) \ 526 ? ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ 527 : (ATA_IDX_SET(ch, idx), \ 528 ATA_INSL_STRM(ch->r_io[ATA_IDX_DATA].res, \ 529 ch->r_io[ATA_IDX_DATA].offset, addr, count))) 530 531 #define ATA_IDX_OUTB(ch, idx, value) \ 532 ((ch->r_io[idx].res) \ 533 ? ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) \ 534 : (ATA_IDX_SET(ch, idx), \ 535 ATA_OUTB(ch->r_io[ATA_IDX_DATA].res, \ 536 ch->r_io[ATA_IDX_DATA].offset, value))) 537 538 #define ATA_IDX_OUTW(ch, idx, value) \ 539 ((ch->r_io[idx].res) \ 540 ? ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) \ 541 : (ATA_IDX_SET(ch, idx), \ 542 ATA_OUTW(ch->r_io[ATA_IDX_DATA].res, \ 543 ch->r_io[ATA_IDX_DATA].offset, value))) 544 545 #define ATA_IDX_OUTL(ch, idx, value) \ 546 ((ch->r_io[idx].res) \ 547 ? ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) \ 548 : (ATA_IDX_SET(ch, idx), \ 549 ATA_OUTL(ch->r_io[ATA_IDX_DATA].res, \ 550 ch->r_io[ATA_IDX_DATA].offset, value))) 551 552 #define ATA_IDX_OUTSW(ch, idx, addr, count) \ 553 ((ch->r_io[idx].res) \ 554 ? ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ 555 : (ATA_IDX_SET(ch, idx), \ 556 ATA_OUTSW(ch->r_io[ATA_IDX_DATA].res, \ 557 ch->r_io[ATA_IDX_DATA].offset, addr, count))) 558 559 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 560 ((ch->r_io[idx].res) \ 561 ? ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ 562 : (ATA_IDX_SET(ch, idx), \ 563 ATA_OUTSW_STRM(ch->r_io[ATA_IDX_DATA].res, \ 564 ch->r_io[ATA_IDX_DATA].offset, addr, count))) 565 566 #define ATA_IDX_OUTSL(ch, idx, addr, count) \ 567 ((ch->r_io[idx].res) \ 568 ? ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ 569 : (ATA_IDX_SET(ch, idx), \ 570 ATA_OUTSL(ch->r_io[ATA_IDX_DATA].res, \ 571 ch->r_io[ATA_IDX_DATA].offset, addr, count))) 572 573 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 574 ((ch->r_io[idx].res) \ 575 ? ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ 576 : (ATA_IDX_SET(ch, idx), \ 577 ATA_OUTSL_STRM(ch->r_io[ATA_IDX_DATA].res, \ 578 ch->r_io[ATA_IDX_DATA].offset, addr, count))) 579