1 /*- 2 * Copyright (c) 1998,1999 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* ATA register defines */ 32 #define ATA_DATA 0x00 /* data register */ 33 #define ATA_ERROR 0x01 /* (R) error register */ 34 #define ATA_E_ABORT 0x04 /* command aborted */ 35 36 #define ATA_FEATURE 0x01 /* (W) feature register */ 37 #define ATA_F_DMA 0x01 /* enable DMA */ 38 #define ATA_F_OVL 0x02 /* enable overlap */ 39 40 #define ATA_COUNT 0x02 /* (W) sector count */ 41 #define ATA_IREASON 0x02 /* (R) interrupt reason */ 42 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 43 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 44 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 45 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 46 47 #define ATA_SECTOR 0x03 /* sector # */ 48 #define ATA_CYL_LSB 0x04 /* cylinder# LSB */ 49 #define ATA_CYL_MSB 0x05 /* cylinder# MSB */ 50 #define ATA_DRIVE 0x06 /* Sector/Drive/Head register */ 51 #define ATA_D_LBA 0x40 /* use LBA adressing */ 52 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 53 54 #define ATA_CMD 0x07 /* command register */ 55 #define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */ 56 #define ATA_C_READ 0x20 /* read command */ 57 #define ATA_C_WRITE 0x30 /* write command */ 58 #define ATA_C_PACKET_CMD 0xa0 /* packet command */ 59 #define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/ 60 #define ATA_C_READ_MULTI 0xc4 /* read multi command */ 61 #define ATA_C_WRITE_MULTI 0xc5 /* write multi command */ 62 #define ATA_C_SET_MULTI 0xc6 /* set multi size command */ 63 #define ATA_C_READ_DMA 0xc8 /* read w/DMA command */ 64 #define ATA_C_WRITE_DMA 0xca /* write w/DMA command */ 65 #define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */ 66 #define ATA_C_SETFEATURES 0xef /* features command */ 67 #define ATA_C_FEA_SETXFER 0x03 /* set transfer mode */ 68 69 #define ATA_STATUS 0x07 /* status register */ 70 #define ATA_S_ERROR 0x01 /* error */ 71 #define ATA_S_INDEX 0x02 /* index */ 72 #define ATA_S_CORR 0x04 /* data corrected */ 73 #define ATA_S_DRQ 0x08 /* data request */ 74 #define ATA_S_DSC 0x10 /* drive seek completed */ 75 #define ATA_S_SERVICE 0x10 /* drive needs service */ 76 #define ATA_S_DWF 0x20 /* drive write fault */ 77 #define ATA_S_DMA 0x20 /* DMA ready */ 78 #define ATA_S_READY 0x40 /* drive ready */ 79 #define ATA_S_BUSY 0x80 /* busy */ 80 81 #define ATA_ALTPORT 0x206 /* alternate Status register */ 82 #define ATA_A_IDS 0x02 /* disable interrupts */ 83 #define ATA_A_RESET 0x04 /* RESET controller */ 84 #define ATA_A_4BIT 0x08 /* 4 head bits */ 85 86 /* misc defines */ 87 #define ATA_MASTER 0x00 88 #define ATA_SLAVE 0x10 89 #define ATA_IOSIZE 0x08 90 #define ATA_OP_FINISHED 0x00 91 #define ATA_OP_CONTINUES 0x01 92 93 /* busmaster DMA related defines */ 94 #define ATA_BM_OFFSET1 0x08 95 #define ATA_DMA_ENTRIES 256 96 #define ATA_DMA_EOT 0x80000000 97 98 #define ATA_BMCMD_PORT 0x00 99 #define ATA_BMCMD_START_STOP 0x01 100 #define ATA_BMCMD_WRITE_READ 0x08 101 102 #define ATA_BMSTAT_PORT 0x02 103 #define ATA_BMSTAT_ACTIVE 0x01 104 #define ATA_BMSTAT_ERROR 0x02 105 #define ATA_BMSTAT_INTERRUPT 0x04 106 #define ATA_BMSTAT_MASK 0x07 107 #define ATA_BMSTAT_DMA_MASTER 0x20 108 #define ATA_BMSTAT_DMA_SLAVE 0x40 109 #define ATA_BMSTAT_DMA_SIMPLEX 0x80 110 111 #define ATA_BMDTP_PORT 0x04 112 113 /* structure for holding DMA address data */ 114 struct ata_dmaentry { 115 u_int32_t base; 116 u_int32_t count; 117 }; 118 119 /* ATA device DMA access modes */ 120 #define ATA_WDMA2 0x22 121 #define ATA_UDMA2 0x42 122 #define ATA_UDMA3 0x43 123 #define ATA_UDMA4 0x44 124 125 /* structure describing an ATA device */ 126 struct ata_softc { 127 int32_t unit; /* unit on this controller */ 128 int32_t lun; /* logical unit # */ 129 struct device *dev; /* device handle */ 130 int32_t ioaddr; /* port addr */ 131 int32_t altioaddr; /* alternate port addr */ 132 int32_t bmaddr; /* bus master DMA port */ 133 void *dev_softc[2]; /* ptr to devices softc's */ 134 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */ 135 int32_t mode[2]; /* transfer mode for devices */ 136 #define ATA_MODE_PIO 0x00 137 #define ATA_MODE_WDMA2 0x01 138 #define ATA_MODE_UDMA2 0x02 139 #define ATA_MODE_UDMA3 0x04 140 #define ATA_MODE_UDMA4 0x08 141 142 int32_t flags; /* controller flags */ 143 #define ATA_DMA_ACTIVE 0x01 144 #define ATA_ATAPI_DMA_RO 0x02 145 146 int32_t devices; /* what is present */ 147 #define ATA_ATA_MASTER 0x01 148 #define ATA_ATA_SLAVE 0x02 149 #define ATA_ATAPI_MASTER 0x04 150 #define ATA_ATAPI_SLAVE 0x08 151 152 u_int8_t status; /* last controller status */ 153 u_int8_t error; /* last controller error */ 154 int32_t active; /* active processing request */ 155 #define ATA_IDLE 0x0 156 #define ATA_IMMEDIATE 0x0 157 #define ATA_WAIT_INTR 0x1 158 #define ATA_IGNORE_INTR 0x2 159 #define ATA_ACTIVE_ATA 0x3 160 #define ATA_ACTIVE_ATAPI 0x4 161 #define ATA_REINITING 0x5 162 163 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */ 164 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */ 165 void *running; /* currently running request */ 166 #if NAPM > 0 167 struct apmhook resume_hook; /* hook for apm */ 168 #endif 169 170 }; 171 172 /* array to hold all ata softc's */ 173 extern struct ata_softc *atadevices[]; 174 #define MAXATA 16 175 176 /* public prototypes */ 177 void ata_start(struct ata_softc *); 178 void ata_reset(struct ata_softc *, int32_t *); 179 int32_t ata_reinit(struct ata_softc *); 180 int32_t ata_wait(struct ata_softc *, int32_t, u_int8_t); 181 int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t); 182 int32_t ata_dmainit(struct ata_softc *, int32_t, int32_t, int32_t, int32_t); 183 int32_t ata_dmasetup(struct ata_softc *, int32_t, int8_t *, int32_t, int32_t); 184 void ata_dmastart(struct ata_softc *); 185 int32_t ata_dmastatus(struct ata_softc *); 186 int32_t ata_dmadone(struct ata_softc *); 187 int8_t *ata_mode2str(int32_t); 188 void bswap(int8_t *, int32_t); 189 void btrim(int8_t *, int32_t); 190 void bpack(int8_t *, int8_t *, int32_t); 191