1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #if 0 30 #define ATA_LEGACY_SUPPORT /* Enable obsolete features that break 31 * some modern devices */ 32 #endif 33 34 /* ATA register defines */ 35 #define ATA_DATA 0 /* (RW) data */ 36 37 #define ATA_FEATURE 1 /* (W) feature */ 38 #define ATA_F_DMA 0x01 /* enable DMA */ 39 #define ATA_F_OVL 0x02 /* enable overlap */ 40 41 #define ATA_COUNT 2 /* (W) sector count */ 42 43 #define ATA_SECTOR 3 /* (RW) sector # */ 44 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 45 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 46 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 47 #define ATA_D_LBA 0x40 /* use LBA addressing */ 48 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 49 50 #define ATA_COMMAND 7 /* (W) command */ 51 52 #define ATA_ERROR 8 /* (R) error */ 53 #define ATA_E_ILI 0x01 /* illegal length */ 54 #define ATA_E_NM 0x02 /* no media */ 55 #define ATA_E_ABORT 0x04 /* command aborted */ 56 #define ATA_E_MCR 0x08 /* media change request */ 57 #define ATA_E_IDNF 0x10 /* ID not found */ 58 #define ATA_E_MC 0x20 /* media changed */ 59 #define ATA_E_UNC 0x40 /* uncorrectable data */ 60 #define ATA_E_ICRC 0x80 /* UDMA crc error */ 61 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 62 63 #define ATA_IREASON 9 /* (R) interrupt reason */ 64 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 65 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 66 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 67 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 68 69 #define ATA_STATUS 10 /* (R) status */ 70 #define ATA_ALTSTAT 11 /* (R) alternate status */ 71 #define ATA_S_ERROR 0x01 /* error */ 72 #define ATA_S_INDEX 0x02 /* index */ 73 #define ATA_S_CORR 0x04 /* data corrected */ 74 #define ATA_S_DRQ 0x08 /* data request */ 75 #define ATA_S_DSC 0x10 /* drive seek completed */ 76 #define ATA_S_SERVICE 0x10 /* drive needs service */ 77 #define ATA_S_DWF 0x20 /* drive write fault */ 78 #define ATA_S_DMA 0x20 /* DMA ready */ 79 #define ATA_S_READY 0x40 /* drive ready */ 80 #define ATA_S_BUSY 0x80 /* busy */ 81 82 #define ATA_CONTROL 12 /* (W) control */ 83 84 #define ATA_CTLOFFSET 0x206 /* control register offset */ 85 #define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */ 86 #define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */ 87 #define ATA_A_IDS 0x02 /* disable interrupts */ 88 #define ATA_A_RESET 0x04 /* RESET controller */ 89 #ifdef ATA_LEGACY_SUPPORT 90 #define ATA_A_4BIT 0x08 /* 4 head bits: obsolete 1996 */ 91 #else 92 #define ATA_A_4BIT 0x00 93 #endif 94 #define ATA_A_HOB 0x80 /* High Order Byte enable */ 95 96 /* SATA register defines */ 97 #define ATA_SSTATUS 13 98 #define ATA_SS_DET_MASK 0x0000000f 99 #define ATA_SS_DET_NO_DEVICE 0x00000000 100 #define ATA_SS_DET_DEV_PRESENT 0x00000001 101 #define ATA_SS_DET_PHY_ONLINE 0x00000003 102 #define ATA_SS_DET_PHY_OFFLINE 0x00000004 103 104 #define ATA_SS_SPD_MASK 0x000000f0 105 #define ATA_SS_SPD_NO_SPEED 0x00000000 106 #define ATA_SS_SPD_GEN1 0x00000010 107 #define ATA_SS_SPD_GEN2 0x00000020 108 109 #define ATA_SS_IPM_MASK 0x00000f00 110 #define ATA_SS_IPM_NO_DEVICE 0x00000000 111 #define ATA_SS_IPM_ACTIVE 0x00000100 112 #define ATA_SS_IPM_PARTIAL 0x00000200 113 #define ATA_SS_IPM_SLUMBER 0x00000600 114 115 #define ATA_SERROR 14 116 #define ATA_SE_DATA_CORRECTED 0x00000001 117 #define ATA_SE_COMM_CORRECTED 0x00000002 118 #define ATA_SE_DATA_ERR 0x00000100 119 #define ATA_SE_COMM_ERR 0x00000200 120 #define ATA_SE_PROT_ERR 0x00000400 121 #define ATA_SE_HOST_ERR 0x00000800 122 #define ATA_SE_PHY_CHANGED 0x00010000 123 #define ATA_SE_PHY_IERROR 0x00020000 124 #define ATA_SE_COMM_WAKE 0x00040000 125 #define ATA_SE_DECODE_ERR 0x00080000 126 #define ATA_SE_PARITY_ERR 0x00100000 127 #define ATA_SE_CRC_ERR 0x00200000 128 #define ATA_SE_HANDSHAKE_ERR 0x00400000 129 #define ATA_SE_LINKSEQ_ERR 0x00800000 130 #define ATA_SE_TRANSPORT_ERR 0x01000000 131 #define ATA_SE_UNKNOWN_FIS 0x02000000 132 133 #define ATA_SCONTROL 15 134 #define ATA_SC_DET_MASK 0x0000000f 135 #define ATA_SC_DET_IDLE 0x00000000 136 #define ATA_SC_DET_RESET 0x00000001 137 #define ATA_SC_DET_DISABLE 0x00000004 138 139 #define ATA_SC_SPD_MASK 0x000000f0 140 #define ATA_SC_SPD_NO_SPEED 0x00000000 141 #define ATA_SC_SPD_SPEED_GEN1 0x00000010 142 #define ATA_SC_SPD_SPEED_GEN2 0x00000020 143 #define ATA_SC_SPD_SPEED_GEN3 0x00000040 144 145 #define ATA_SC_IPM_MASK 0x00000f00 146 #define ATA_SC_IPM_NONE 0x00000000 147 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100 148 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200 149 150 #define ATA_SACTIVE 16 151 152 /* SATA AHCI v1.0 register defines */ 153 #define ATA_AHCI_CAP 0x00 154 #define ATA_AHCI_CAP_NPMASK 0x0000001f 155 #define ATA_AHCI_CAP_SXS 0x00000020 156 #define ATA_AHCI_CAP_EMS 0x00000040 157 #define ATA_AHCI_CAP_CCCS 0x00000080 158 #define ATA_AHCI_CAP_NCS 0x00001F00 159 #define ATA_AHCI_CAP_NCS_SHIFT 8 160 #define ATA_AHCI_CAP_PSC 0x00002000 161 #define ATA_AHCI_CAP_SSC 0x00004000 162 #define ATA_AHCI_CAP_PMD 0x00008000 163 #define ATA_AHCI_CAP_FBSS 0x00010000 164 #define ATA_AHCI_CAP_SPM 0x00020000 165 #define ATA_AHCI_CAP_SAM 0x00080000 166 #define ATA_AHCI_CAP_ISS 0x00F00000 167 #define ATA_AHCI_CAP_ISS_SHIFT 20 168 #define ATA_AHCI_CAP_SCLO 0x01000000 169 #define ATA_AHCI_CAP_SAL 0x02000000 170 #define ATA_AHCI_CAP_SALP 0x04000000 171 #define ATA_AHCI_CAP_SSS 0x08000000 172 #define ATA_AHCI_CAP_SMPS 0x10000000 173 #define ATA_AHCI_CAP_SSNTF 0x20000000 174 #define ATA_AHCI_CAP_SNCQ 0x40000000 175 #define ATA_AHCI_CAP_64BIT 0x80000000 176 177 #define ATA_AHCI_GHC 0x04 178 #define ATA_AHCI_GHC_AE 0x80000000 179 #define ATA_AHCI_GHC_IE 0x00000002 180 #define ATA_AHCI_GHC_HR 0x00000001 181 182 #define ATA_AHCI_IS 0x08 183 #define ATA_AHCI_PI 0x0c 184 #define ATA_AHCI_VS 0x10 185 186 #define ATA_AHCI_OFFSET 0x80 187 188 #define ATA_AHCI_P_CLB 0x100 189 #define ATA_AHCI_P_CLBU 0x104 190 #define ATA_AHCI_P_FB 0x108 191 #define ATA_AHCI_P_FBU 0x10c 192 #define ATA_AHCI_P_IS 0x110 193 #define ATA_AHCI_P_IE 0x114 194 #define ATA_AHCI_P_IX_DHR 0x00000001 195 #define ATA_AHCI_P_IX_PS 0x00000002 196 #define ATA_AHCI_P_IX_DS 0x00000004 197 #define ATA_AHCI_P_IX_SDB 0x00000008 198 #define ATA_AHCI_P_IX_UF 0x00000010 199 #define ATA_AHCI_P_IX_DP 0x00000020 200 #define ATA_AHCI_P_IX_PC 0x00000040 201 #define ATA_AHCI_P_IX_DI 0x00000080 202 203 #define ATA_AHCI_P_IX_PRC 0x00400000 204 #define ATA_AHCI_P_IX_IPM 0x00800000 205 #define ATA_AHCI_P_IX_OF 0x01000000 206 #define ATA_AHCI_P_IX_INF 0x04000000 207 #define ATA_AHCI_P_IX_IF 0x08000000 208 #define ATA_AHCI_P_IX_HBD 0x10000000 209 #define ATA_AHCI_P_IX_HBF 0x20000000 210 #define ATA_AHCI_P_IX_TFE 0x40000000 211 #define ATA_AHCI_P_IX_CPD 0x80000000 212 213 #define ATA_AHCI_P_CMD 0x118 214 #define ATA_AHCI_P_CMD_ST 0x00000001 215 #define ATA_AHCI_P_CMD_SUD 0x00000002 216 #define ATA_AHCI_P_CMD_POD 0x00000004 217 #define ATA_AHCI_P_CMD_CLO 0x00000008 218 #define ATA_AHCI_P_CMD_FRE 0x00000010 219 #define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00 220 #define ATA_AHCI_P_CMD_ISS 0x00002000 221 #define ATA_AHCI_P_CMD_FR 0x00004000 222 #define ATA_AHCI_P_CMD_CR 0x00008000 223 #define ATA_AHCI_P_CMD_CPS 0x00010000 224 #define ATA_AHCI_P_CMD_PMA 0x00020000 225 #define ATA_AHCI_P_CMD_HPCP 0x00040000 226 #define ATA_AHCI_P_CMD_ISP 0x00080000 227 #define ATA_AHCI_P_CMD_CPD 0x00100000 228 #define ATA_AHCI_P_CMD_ATAPI 0x01000000 229 #define ATA_AHCI_P_CMD_DLAE 0x02000000 230 #define ATA_AHCI_P_CMD_ALPE 0x04000000 231 #define ATA_AHCI_P_CMD_ASP 0x08000000 232 #define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000 233 #define ATA_AHCI_P_CMD_NOOP 0x00000000 234 #define ATA_AHCI_P_CMD_ACTIVE 0x10000000 235 #define ATA_AHCI_P_CMD_PARTIAL 0x20000000 236 #define ATA_AHCI_P_CMD_SLUMBER 0x60000000 237 238 #define ATA_AHCI_P_TFD 0x120 239 #define ATA_AHCI_P_SIG 0x124 240 #define ATA_AHCI_P_SSTS 0x128 241 #define ATA_AHCI_P_SCTL 0x12c 242 #define ATA_AHCI_P_SERR 0x130 243 #define ATA_AHCI_P_SACT 0x134 244 #define ATA_AHCI_P_CI 0x138 245 #define ATA_AHCI_P_SNTF 0x13C 246 #define ATA_AHCI_P_FBS 0x140 247 248 #define ATA_AHCI_CL_SIZE 32 249 #define ATA_AHCI_CL_OFFSET 0 250 #define ATA_AHCI_FB_OFFSET (ATA_AHCI_CL_SIZE * 32) 251 #define ATA_AHCI_CT_OFFSET (ATA_AHCI_FB_OFFSET + 4096) 252 #define ATA_AHCI_CT_SIZE (2176 + 128) 253 254 struct ata_ahci_dma_prd { 255 u_int64_t dba; 256 u_int32_t reserved; 257 u_int32_t dbc; /* 0 based */ 258 #define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */ 259 #define ATA_AHCI_PRD_IPC (1<<31) 260 } __packed; 261 262 struct ata_ahci_cmd_tab { 263 u_int8_t cfis[64]; 264 u_int8_t acmd[32]; 265 u_int8_t reserved[32]; 266 #define ATA_AHCI_DMA_ENTRIES 129 267 struct ata_ahci_dma_prd prd_tab[ATA_AHCI_DMA_ENTRIES]; 268 } __packed; 269 270 struct ata_ahci_cmd_list { 271 u_int16_t cmd_flags; 272 #define ATA_AHCI_CMD_ATAPI 0x0020 273 #define ATA_AHCI_CMD_WRITE 0x0040 274 #define ATA_AHCI_CMD_PREFETCH 0x0080 275 #define ATA_AHCI_CMD_RESET 0x0100 276 #define ATA_AHCI_CMD_BIST 0x0200 277 #define ATA_AHCI_CMD_CLR_BUSY 0x0400 278 279 u_int16_t prd_length; /* PRD entries */ 280 u_int32_t bytecount; 281 u_int64_t cmd_table_phys; /* 128byte aligned */ 282 } __packed; 283 284 285 /* DMA register defines */ 286 #define ATA_DMA_ENTRIES 256 287 #define ATA_DMA_EOT 0x80000000 288 289 #define ATA_BMCMD_PORT 17 290 #define ATA_BMCMD_START_STOP 0x01 291 #define ATA_BMCMD_WRITE_READ 0x08 292 293 #define ATA_BMDEVSPEC_0 18 294 #define ATA_BMSTAT_PORT 19 295 #define ATA_BMSTAT_ACTIVE 0x01 296 #define ATA_BMSTAT_ERROR 0x02 297 #define ATA_BMSTAT_INTERRUPT 0x04 298 #define ATA_BMSTAT_MASK 0x07 299 #define ATA_BMSTAT_DMA_MASTER 0x20 300 #define ATA_BMSTAT_DMA_SLAVE 0x40 301 #define ATA_BMSTAT_DMA_SIMPLEX 0x80 302 303 #define ATA_BMDEVSPEC_1 20 304 #define ATA_BMDTP_PORT 21 305 306 #define ATA_IDX_ADDR 22 307 #define ATA_IDX_DATA 23 308 #define ATA_MAX_RES 24 309 310 /* misc defines */ 311 #define ATA_PRIMARY 0x1f0 312 #define ATA_SECONDARY 0x170 313 #define ATA_PC98_BANK 0x432 314 #define ATA_IOSIZE 0x08 315 #define ATA_PC98_IOSIZE 0x10 316 #define ATA_CTLIOSIZE 0x01 317 #define ATA_BMIOSIZE 0x08 318 #define ATA_PC98_BANKIOSIZE 0x01 319 #define ATA_IOADDR_RID 0 320 #define ATA_CTLADDR_RID 1 321 #define ATA_BMADDR_RID 0x20 322 #define ATA_PC98_CTLADDR_RID 8 323 #define ATA_PC98_BANKADDR_RID 9 324 #define ATA_IRQ_RID 0 325 #define ATA_DEV(unit) ((unit > 0) ? 0x10 : 0) 326 #define ATA_CFA_MAGIC1 0x844A 327 #define ATA_CFA_MAGIC2 0x848A 328 #define ATA_CFA_MAGIC3 0x8400 329 #define ATAPI_MAGIC_LSB 0x14 330 #define ATAPI_MAGIC_MSB 0xeb 331 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 332 #define ATAPI_P_WRITE (ATA_S_DRQ) 333 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 334 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 335 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 336 #define ATAPI_P_ABORT 0 337 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 338 #define ATA_OP_CONTINUES 0 339 #define ATA_OP_FINISHED 1 340 #define ATA_MAX_28BIT_LBA 268435455UL 341 342 #ifndef ATA_REQUEST_TIMEOUT 343 #define ATA_REQUEST_TIMEOUT 10 344 #endif 345 346 /* structure used for composite atomic operations */ 347 #define MAX_COMPOSITES 32 /* u_int32_t bits */ 348 struct ata_composite { 349 struct mtx lock; /* control lock */ 350 u_int32_t rd_needed; /* needed read subdisks */ 351 u_int32_t rd_done; /* done read subdisks */ 352 u_int32_t wr_needed; /* needed write subdisks */ 353 u_int32_t wr_depend; /* write depends on subdisks */ 354 u_int32_t wr_done; /* done write subdisks */ 355 struct ata_request *request[MAX_COMPOSITES]; 356 u_int32_t residual; /* bytes still to transfer */ 357 caddr_t data_1; 358 caddr_t data_2; 359 }; 360 361 /* structure used to queue an ATA/ATAPI request */ 362 struct ata_request { 363 device_t dev; /* device handle */ 364 device_t parent; /* channel handle */ 365 int unit; /* physical unit */ 366 union { 367 struct { 368 u_int8_t command; /* command reg */ 369 u_int16_t feature; /* feature reg */ 370 u_int16_t count; /* count reg */ 371 u_int64_t lba; /* lba reg */ 372 } ata; 373 struct { 374 u_int8_t ccb[16]; /* ATAPI command block */ 375 struct atapi_sense sense; /* ATAPI request sense data */ 376 u_int8_t saved_cmd; /* ATAPI saved command */ 377 } atapi; 378 } u; 379 u_int32_t bytecount; /* bytes to transfer */ 380 u_int32_t transfersize; /* bytes pr transfer */ 381 caddr_t data; /* pointer to data buf */ 382 u_int32_t tag; /* HW tag of this request */ 383 int flags; 384 #define ATA_R_CONTROL 0x00000001 385 #define ATA_R_READ 0x00000002 386 #define ATA_R_WRITE 0x00000004 387 #define ATA_R_ATAPI 0x00000008 388 #define ATA_R_DMA 0x00000010 389 #define ATA_R_QUIET 0x00000020 390 #define ATA_R_TIMEOUT 0x00000040 391 #define ATA_R_48BIT 0x00000080 392 393 #define ATA_R_ORDERED 0x00000100 394 #define ATA_R_AT_HEAD 0x00000200 395 #define ATA_R_REQUEUE 0x00000400 396 #define ATA_R_THREAD 0x00000800 397 #define ATA_R_DIRECT 0x00001000 398 #define ATA_R_NEEDRESULT 0x00002000 399 #define ATA_R_DATA_IN_CCB 0x00004000 400 401 #define ATA_R_ATAPI16 0x00010000 402 #define ATA_R_ATAPI_INTR 0x00020000 403 404 #define ATA_R_DEBUG 0x10000000 405 #define ATA_R_DANGER1 0x20000000 406 #define ATA_R_DANGER2 0x40000000 407 408 struct ata_dmaslot *dma; /* DMA slot of this request */ 409 u_int8_t status; /* ATA status */ 410 u_int8_t error; /* ATA error */ 411 u_int32_t donecount; /* bytes transferred */ 412 int result; /* result error code */ 413 void (*callback)(struct ata_request *request); 414 struct sema done; /* request done sema */ 415 int retries; /* retry count */ 416 int timeout; /* timeout for this cmd */ 417 struct callout callout; /* callout management */ 418 struct task task; /* task management */ 419 struct bio *bio; /* bio for this request */ 420 int this; /* this request ID */ 421 struct ata_composite *composite; /* for composite atomic ops */ 422 void *driver; /* driver specific */ 423 TAILQ_ENTRY(ata_request) chain; /* list management */ 424 union ccb *ccb; 425 }; 426 427 /* define this for debugging request processing */ 428 #if 0 429 #define ATA_DEBUG_RQ(request, string) \ 430 { \ 431 if (request->flags & ATA_R_DEBUG) \ 432 device_printf(request->parent, "req=%p %s " string "\n", \ 433 request, ata_cmd2str(request)); \ 434 } 435 #else 436 #define ATA_DEBUG_RQ(request, string) 437 #endif 438 439 440 /* structure describing an ATA/ATAPI device */ 441 struct ata_device { 442 device_t dev; /* device handle */ 443 int unit; /* physical unit */ 444 #define ATA_MASTER 0x00 445 #define ATA_SLAVE 0x01 446 #define ATA_PM 0x0f 447 448 struct ata_params param; /* ata param structure */ 449 int mode; /* current transfermode */ 450 u_int32_t max_iosize; /* max IO size */ 451 int spindown; /* idle spindown timeout */ 452 struct callout spindown_timer; 453 int spindown_state; 454 int flags; 455 #define ATA_D_USE_CHS 0x0001 456 #define ATA_D_MEDIA_CHANGED 0x0002 457 #define ATA_D_ENC_PRESENT 0x0004 458 }; 459 460 /* structure for holding DMA Physical Region Descriptors (PRD) entries */ 461 struct ata_dma_prdentry { 462 u_int32_t addr; 463 u_int32_t count; 464 }; 465 466 /* structure used by the setprd function */ 467 struct ata_dmasetprd_args { 468 void *dmatab; 469 int nsegs; 470 int error; 471 }; 472 473 struct ata_dmaslot { 474 u_int8_t status; /* DMA status */ 475 bus_dma_tag_t sg_tag; /* SG list DMA tag */ 476 bus_dmamap_t sg_map; /* SG list DMA map */ 477 void *sg; /* DMA transfer table */ 478 bus_addr_t sg_bus; /* bus address of dmatab */ 479 bus_dma_tag_t data_tag; /* data DMA tag */ 480 bus_dmamap_t data_map; /* data DMA map */ 481 }; 482 483 /* structure holding DMA related information */ 484 struct ata_dma { 485 bus_dma_tag_t dmatag; /* parent DMA tag */ 486 bus_dma_tag_t work_tag; /* workspace DMA tag */ 487 bus_dmamap_t work_map; /* workspace DMA map */ 488 u_int8_t *work; /* workspace */ 489 bus_addr_t work_bus; /* bus address of dmatab */ 490 491 #define ATA_DMA_SLOTS 1 492 int dma_slots; /* DMA slots allocated */ 493 struct ata_dmaslot slot[ATA_DMA_SLOTS]; 494 u_int32_t alignment; /* DMA SG list alignment */ 495 u_int32_t boundary; /* DMA SG list boundary */ 496 u_int32_t segsize; /* DMA SG list segment size */ 497 u_int32_t max_iosize; /* DMA data max IO size */ 498 u_int64_t max_address; /* highest DMA'able address */ 499 int flags; 500 #define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress */ 501 502 void (*alloc)(device_t dev); 503 void (*free)(device_t dev); 504 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 505 int (*load)(struct ata_request *request, void *addr, int *nsegs); 506 int (*unload)(struct ata_request *request); 507 int (*start)(struct ata_request *request); 508 int (*stop)(struct ata_request *request); 509 void (*reset)(device_t dev); 510 }; 511 512 /* structure holding lowlevel functions */ 513 struct ata_lowlevel { 514 u_int32_t (*softreset)(device_t dev, int pmport); 515 int (*pm_read)(device_t dev, int port, int reg, u_int32_t *result); 516 int (*pm_write)(device_t dev, int port, int reg, u_int32_t value); 517 int (*status)(device_t dev); 518 int (*begin_transaction)(struct ata_request *request); 519 int (*end_transaction)(struct ata_request *request); 520 int (*command)(struct ata_request *request); 521 void (*tf_read)(struct ata_request *request); 522 void (*tf_write)(struct ata_request *request); 523 }; 524 525 /* structure holding resources for an ATA channel */ 526 struct ata_resource { 527 struct resource *res; 528 int offset; 529 }; 530 531 struct ata_cam_device { 532 u_int revision; 533 int mode; 534 u_int bytecount; 535 u_int atapi; 536 u_int caps; 537 }; 538 539 /* structure describing an ATA channel */ 540 struct ata_channel { 541 device_t dev; /* device handle */ 542 int unit; /* physical channel */ 543 int attached; /* channel is attached */ 544 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ 545 struct resource *r_irq; /* interrupt of this channel */ 546 void *ih; /* interrupt handle */ 547 struct ata_lowlevel hw; /* lowlevel HW functions */ 548 struct ata_dma dma; /* DMA data / functions */ 549 int flags; /* channel flags */ 550 #define ATA_NO_SLAVE 0x01 551 #define ATA_USE_16BIT 0x02 552 #define ATA_ATAPI_DMA_RO 0x04 553 #define ATA_NO_48BIT_DMA 0x08 554 #define ATA_ALWAYS_DMASTAT 0x10 555 #define ATA_CHECKS_CABLE 0x20 556 #define ATA_NO_ATAPI_DMA 0x40 557 #define ATA_SATA 0x80 558 #define ATA_DMA_BEFORE_CMD 0x100 559 #define ATA_KNOWN_PRESENCE 0x200 560 #define ATA_STATUS_IS_LONG 0x400 561 #define ATA_PERIODIC_POLL 0x800 562 563 int pm_level; /* power management level */ 564 int devices; /* what is present */ 565 #define ATA_ATA_MASTER 0x00000001 566 #define ATA_ATA_SLAVE 0x00000002 567 #define ATA_PORTMULTIPLIER 0x00008000 568 #define ATA_ATAPI_MASTER 0x00010000 569 #define ATA_ATAPI_SLAVE 0x00020000 570 571 struct mtx state_mtx; /* state lock */ 572 int state; /* ATA channel state */ 573 #define ATA_IDLE 0x0000 574 #define ATA_ACTIVE 0x0001 575 #define ATA_STALL_QUEUE 0x0002 576 577 struct ata_request *running; /* currently running request */ 578 struct task conntask; /* PHY events handling task */ 579 struct cam_sim *sim; 580 struct cam_path *path; 581 struct ata_cam_device user[16]; /* User-specified settings */ 582 struct ata_cam_device curr[16]; /* Current settings */ 583 int requestsense; /* CCB waiting for SENSE. */ 584 struct callout poll_callout; /* Periodic status poll. */ 585 }; 586 587 /* disk bay/enclosure related */ 588 #define ATA_LED_OFF 0x00 589 #define ATA_LED_RED 0x01 590 #define ATA_LED_GREEN 0x02 591 #define ATA_LED_ORANGE 0x03 592 #define ATA_LED_MASK 0x03 593 594 /* externs */ 595 extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data); 596 extern struct intr_config_hook *ata_delayed_attach; 597 extern devclass_t ata_devclass; 598 extern int ata_wc; 599 extern int ata_setmax; 600 extern int ata_dma_check_80pin; 601 602 /* public prototypes */ 603 /* ata-all.c: */ 604 int ata_probe(device_t dev); 605 int ata_attach(device_t dev); 606 int ata_detach(device_t dev); 607 int ata_reinit(device_t dev); 608 int ata_suspend(device_t dev); 609 int ata_resume(device_t dev); 610 void ata_interrupt(void *data); 611 int ata_getparam(struct ata_device *atadev, int init); 612 void ata_default_registers(device_t dev); 613 void ata_udelay(int interval); 614 const char *ata_cmd2str(struct ata_request *request); 615 const char *ata_mode2str(int mode); 616 void ata_setmode(device_t dev); 617 void ata_print_cable(device_t dev, u_int8_t *who); 618 int ata_atapi(device_t dev, int target); 619 void ata_timeout(struct ata_request *); 620 621 /* ata-lowlevel.c: */ 622 void ata_generic_hw(device_t dev); 623 int ata_begin_transaction(struct ata_request *); 624 int ata_end_transaction(struct ata_request *); 625 void ata_generic_reset(device_t dev); 626 int ata_generic_command(struct ata_request *request); 627 628 /* ata-dma.c: */ 629 void ata_dmainit(device_t); 630 void ata_dmafini(device_t dev); 631 632 /* ata-sata.c: */ 633 void ata_sata_phy_check_events(device_t dev, int port); 634 int ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val); 635 int ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val); 636 int ata_sata_phy_reset(device_t dev, int port, int quick); 637 int ata_sata_setmode(device_t dev, int target, int mode); 638 int ata_sata_getrev(device_t dev, int target); 639 int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis); 640 void ata_pm_identify(device_t dev); 641 642 /* macros for alloc/free of struct ata_request */ 643 extern uma_zone_t ata_request_zone; 644 #define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT | M_ZERO) 645 #define ata_free_request(request) { \ 646 if (!(request->flags & ATA_R_DANGER2)) \ 647 uma_zfree(ata_request_zone, request); \ 648 } 649 650 MALLOC_DECLARE(M_ATA); 651 652 /* misc newbus defines */ 653 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 654 655 /* macros to hide busspace uglyness */ 656 #define ATA_INB(res, offset) \ 657 bus_read_1((res), (offset)) 658 659 #define ATA_INW(res, offset) \ 660 bus_read_2((res), (offset)) 661 #define ATA_INW_STRM(res, offset) \ 662 bus_read_stream_2((res), (offset)) 663 #define ATA_INL(res, offset) \ 664 bus_read_4((res), (offset)) 665 #define ATA_INSW(res, offset, addr, count) \ 666 bus_read_multi_2((res), (offset), (addr), (count)) 667 #define ATA_INSW_STRM(res, offset, addr, count) \ 668 bus_read_multi_stream_2((res), (offset), (addr), (count)) 669 #define ATA_INSL(res, offset, addr, count) \ 670 bus_read_multi_4((res), (offset), (addr), (count)) 671 #define ATA_INSL_STRM(res, offset, addr, count) \ 672 bus_read_multi_stream_4((res), (offset), (addr), (count)) 673 #define ATA_OUTB(res, offset, value) \ 674 bus_write_1((res), (offset), (value)) 675 #define ATA_OUTW(res, offset, value) \ 676 bus_write_2((res), (offset), (value)) 677 #define ATA_OUTW_STRM(res, offset, value) \ 678 bus_write_stream_2((res), (offset), (value)) 679 #define ATA_OUTL(res, offset, value) \ 680 bus_write_4((res), (offset), (value)) 681 #define ATA_OUTSW(res, offset, addr, count) \ 682 bus_write_multi_2((res), (offset), (addr), (count)) 683 #define ATA_OUTSW_STRM(res, offset, addr, count) \ 684 bus_write_multi_stream_2((res), (offset), (addr), (count)) 685 #define ATA_OUTSL(res, offset, addr, count) \ 686 bus_write_multi_4((res), (offset), (addr), (count)) 687 #define ATA_OUTSL_STRM(res, offset, addr, count) \ 688 bus_write_multi_stream_4((res), (offset), (addr), (count)) 689 690 #define ATA_IDX_INB(ch, idx) \ 691 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) 692 693 #define ATA_IDX_INW(ch, idx) \ 694 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) 695 696 #define ATA_IDX_INW_STRM(ch, idx) \ 697 ATA_INW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset) 698 699 #define ATA_IDX_INL(ch, idx) \ 700 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) 701 702 #define ATA_IDX_INSW(ch, idx, addr, count) \ 703 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 704 705 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 706 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 707 708 #define ATA_IDX_INSL(ch, idx, addr, count) \ 709 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 710 711 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 712 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 713 714 #define ATA_IDX_OUTB(ch, idx, value) \ 715 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) 716 717 #define ATA_IDX_OUTW(ch, idx, value) \ 718 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) 719 720 #define ATA_IDX_OUTW_STRM(ch, idx, value) \ 721 ATA_OUTW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, value) 722 723 #define ATA_IDX_OUTL(ch, idx, value) \ 724 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) 725 726 #define ATA_IDX_OUTSW(ch, idx, addr, count) \ 727 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 728 729 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 730 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 731 732 #define ATA_IDX_OUTSL(ch, idx, addr, count) \ 733 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 734 735 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 736 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 737