1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* ATA register defines */ 30 #define ATA_DATA 0 /* (RW) data */ 31 32 #define ATA_FEATURE 1 /* (W) feature */ 33 #define ATA_F_DMA 0x01 /* enable DMA */ 34 #define ATA_F_OVL 0x02 /* enable overlap */ 35 36 #define ATA_COUNT 2 /* (W) sector count */ 37 38 #define ATA_SECTOR 3 /* (RW) sector # */ 39 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 40 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 41 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 42 #define ATA_D_LBA 0x40 /* use LBA addressing */ 43 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 44 45 #define ATA_COMMAND 7 /* (W) command */ 46 47 #define ATA_ERROR 8 /* (R) error */ 48 #define ATA_E_ILI 0x01 /* illegal length */ 49 #define ATA_E_NM 0x02 /* no media */ 50 #define ATA_E_ABORT 0x04 /* command aborted */ 51 #define ATA_E_MCR 0x08 /* media change request */ 52 #define ATA_E_IDNF 0x10 /* ID not found */ 53 #define ATA_E_MC 0x20 /* media changed */ 54 #define ATA_E_UNC 0x40 /* uncorrectable data */ 55 #define ATA_E_ICRC 0x80 /* UDMA crc error */ 56 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 57 58 #define ATA_IREASON 9 /* (R) interrupt reason */ 59 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 60 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 61 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 62 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 63 64 #define ATA_STATUS 10 /* (R) status */ 65 #define ATA_ALTSTAT 11 /* (R) alternate status */ 66 #define ATA_S_ERROR 0x01 /* error */ 67 #define ATA_S_INDEX 0x02 /* index */ 68 #define ATA_S_CORR 0x04 /* data corrected */ 69 #define ATA_S_DRQ 0x08 /* data request */ 70 #define ATA_S_DSC 0x10 /* drive seek completed */ 71 #define ATA_S_SERVICE 0x10 /* drive needs service */ 72 #define ATA_S_DWF 0x20 /* drive write fault */ 73 #define ATA_S_DMA 0x20 /* DMA ready */ 74 #define ATA_S_READY 0x40 /* drive ready */ 75 #define ATA_S_BUSY 0x80 /* busy */ 76 77 #define ATA_CONTROL 12 /* (W) control */ 78 79 #define ATA_CTLOFFSET 0x206 /* control register offset */ 80 #define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */ 81 #define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */ 82 #define ATA_A_IDS 0x02 /* disable interrupts */ 83 #define ATA_A_RESET 0x04 /* RESET controller */ 84 #define ATA_A_4BIT 0x08 /* 4 head bits */ 85 #define ATA_A_HOB 0x80 /* High Order Byte enable */ 86 87 /* SATA register defines */ 88 #define ATA_SSTATUS 13 89 #define ATA_SS_DET_MASK 0x0000000f 90 #define ATA_SS_DET_NO_DEVICE 0x00000000 91 #define ATA_SS_DET_DEV_PRESENT 0x00000001 92 #define ATA_SS_DET_PHY_ONLINE 0x00000003 93 #define ATA_SS_DET_PHY_OFFLINE 0x00000004 94 95 #define ATA_SS_SPD_MASK 0x000000f0 96 #define ATA_SS_SPD_NO_SPEED 0x00000000 97 #define ATA_SS_SPD_GEN1 0x00000010 98 #define ATA_SS_SPD_GEN2 0x00000020 99 100 #define ATA_SS_IPM_MASK 0x00000f00 101 #define ATA_SS_IPM_NO_DEVICE 0x00000000 102 #define ATA_SS_IPM_ACTIVE 0x00000100 103 #define ATA_SS_IPM_PARTIAL 0x00000200 104 #define ATA_SS_IPM_SLUMBER 0x00000600 105 106 #define ATA_SS_CONWELL_MASK \ 107 (ATA_SS_DET_MASK|ATA_SS_SPD_MASK|ATA_SS_IPM_MASK) 108 #define ATA_SS_CONWELL_GEN1 \ 109 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN1|ATA_SS_IPM_ACTIVE) 110 #define ATA_SS_CONWELL_GEN2 \ 111 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN2|ATA_SS_IPM_ACTIVE) 112 113 #define ATA_SERROR 14 114 #define ATA_SE_DATA_CORRECTED 0x00000001 115 #define ATA_SE_COMM_CORRECTED 0x00000002 116 #define ATA_SE_DATA_ERR 0x00000100 117 #define ATA_SE_COMM_ERR 0x00000200 118 #define ATA_SE_PROT_ERR 0x00000400 119 #define ATA_SE_HOST_ERR 0x00000800 120 #define ATA_SE_PHY_CHANGED 0x00010000 121 #define ATA_SE_PHY_IERROR 0x00020000 122 #define ATA_SE_COMM_WAKE 0x00040000 123 #define ATA_SE_DECODE_ERR 0x00080000 124 #define ATA_SE_PARITY_ERR 0x00100000 125 #define ATA_SE_CRC_ERR 0x00200000 126 #define ATA_SE_HANDSHAKE_ERR 0x00400000 127 #define ATA_SE_LINKSEQ_ERR 0x00800000 128 #define ATA_SE_TRANSPORT_ERR 0x01000000 129 #define ATA_SE_UNKNOWN_FIS 0x02000000 130 131 #define ATA_SCONTROL 15 132 #define ATA_SC_DET_MASK 0x0000000f 133 #define ATA_SC_DET_IDLE 0x00000000 134 #define ATA_SC_DET_RESET 0x00000001 135 #define ATA_SC_DET_DISABLE 0x00000004 136 137 #define ATA_SC_SPD_MASK 0x000000f0 138 #define ATA_SC_SPD_NO_SPEED 0x00000000 139 #define ATA_SC_SPD_SPEED_GEN1 0x00000010 140 #define ATA_SC_SPD_SPEED_GEN2 0x00000020 141 142 #define ATA_SC_IPM_MASK 0x00000f00 143 #define ATA_SC_IPM_NONE 0x00000000 144 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100 145 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200 146 147 #define ATA_SACTIVE 16 148 149 /* SATA AHCI v1.0 register defines */ 150 #define ATA_AHCI_CAP 0x00 151 #define ATA_AHCI_CAP_NPMASK 0x0000001f 152 #define ATA_AHCI_CAP_SXS 0x00000020 153 #define ATA_AHCI_CAP_EMS 0x00000040 154 #define ATA_AHCI_CAP_CCCS 0x00000080 155 #define ATA_AHCI_CAP_NCS 0x00001F00 156 #define ATA_AHCI_CAP_NCS_SHIFT 8 157 #define ATA_AHCI_CAP_PSC 0x00002000 158 #define ATA_AHCI_CAP_SSC 0x00004000 159 #define ATA_AHCI_CAP_PMD 0x00008000 160 #define ATA_AHCI_CAP_FBSS 0x00010000 161 #define ATA_AHCI_CAP_SPM 0x00020000 162 #define ATA_AHCI_CAP_SAM 0x00080000 163 #define ATA_AHCI_CAP_ISS 0x00F00000 164 #define ATA_AHCI_CAP_ISS_SHIFT 20 165 #define ATA_AHCI_CAP_SCLO 0x01000000 166 #define ATA_AHCI_CAP_SAL 0x02000000 167 #define ATA_AHCI_CAP_SALP 0x04000000 168 #define ATA_AHCI_CAP_SSS 0x08000000 169 #define ATA_AHCI_CAP_SMPS 0x10000000 170 #define ATA_AHCI_CAP_SSNTF 0x20000000 171 #define ATA_AHCI_CAP_SNCQ 0x40000000 172 #define ATA_AHCI_CAP_64BIT 0x80000000 173 174 #define ATA_AHCI_GHC 0x04 175 #define ATA_AHCI_GHC_AE 0x80000000 176 #define ATA_AHCI_GHC_IE 0x00000002 177 #define ATA_AHCI_GHC_HR 0x00000001 178 179 #define ATA_AHCI_IS 0x08 180 #define ATA_AHCI_PI 0x0c 181 #define ATA_AHCI_VS 0x10 182 183 #define ATA_AHCI_OFFSET 0x80 184 185 #define ATA_AHCI_P_CLB 0x100 186 #define ATA_AHCI_P_CLBU 0x104 187 #define ATA_AHCI_P_FB 0x108 188 #define ATA_AHCI_P_FBU 0x10c 189 #define ATA_AHCI_P_IS 0x110 190 #define ATA_AHCI_P_IE 0x114 191 #define ATA_AHCI_P_IX_DHR 0x00000001 192 #define ATA_AHCI_P_IX_PS 0x00000002 193 #define ATA_AHCI_P_IX_DS 0x00000004 194 #define ATA_AHCI_P_IX_SDB 0x00000008 195 #define ATA_AHCI_P_IX_UF 0x00000010 196 #define ATA_AHCI_P_IX_DP 0x00000020 197 #define ATA_AHCI_P_IX_PC 0x00000040 198 #define ATA_AHCI_P_IX_DI 0x00000080 199 200 #define ATA_AHCI_P_IX_PRC 0x00400000 201 #define ATA_AHCI_P_IX_IPM 0x00800000 202 #define ATA_AHCI_P_IX_OF 0x01000000 203 #define ATA_AHCI_P_IX_INF 0x04000000 204 #define ATA_AHCI_P_IX_IF 0x08000000 205 #define ATA_AHCI_P_IX_HBD 0x10000000 206 #define ATA_AHCI_P_IX_HBF 0x20000000 207 #define ATA_AHCI_P_IX_TFE 0x40000000 208 #define ATA_AHCI_P_IX_CPD 0x80000000 209 210 #define ATA_AHCI_P_CMD 0x118 211 #define ATA_AHCI_P_CMD_ST 0x00000001 212 #define ATA_AHCI_P_CMD_SUD 0x00000002 213 #define ATA_AHCI_P_CMD_POD 0x00000004 214 #define ATA_AHCI_P_CMD_CLO 0x00000008 215 #define ATA_AHCI_P_CMD_FRE 0x00000010 216 #define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00 217 #define ATA_AHCI_P_CMD_ISS 0x00002000 218 #define ATA_AHCI_P_CMD_FR 0x00004000 219 #define ATA_AHCI_P_CMD_CR 0x00008000 220 #define ATA_AHCI_P_CMD_CPS 0x00010000 221 #define ATA_AHCI_P_CMD_PMA 0x00020000 222 #define ATA_AHCI_P_CMD_HPCP 0x00040000 223 #define ATA_AHCI_P_CMD_ISP 0x00080000 224 #define ATA_AHCI_P_CMD_CPD 0x00100000 225 #define ATA_AHCI_P_CMD_ATAPI 0x01000000 226 #define ATA_AHCI_P_CMD_DLAE 0x02000000 227 #define ATA_AHCI_P_CMD_ALPE 0x04000000 228 #define ATA_AHCI_P_CMD_ASP 0x08000000 229 #define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000 230 #define ATA_AHCI_P_CMD_NOOP 0x00000000 231 #define ATA_AHCI_P_CMD_ACTIVE 0x10000000 232 #define ATA_AHCI_P_CMD_PARTIAL 0x20000000 233 #define ATA_AHCI_P_CMD_SLUMBER 0x60000000 234 235 #define ATA_AHCI_P_TFD 0x120 236 #define ATA_AHCI_P_SIG 0x124 237 #define ATA_AHCI_P_SSTS 0x128 238 #define ATA_AHCI_P_SCTL 0x12c 239 #define ATA_AHCI_P_SERR 0x130 240 #define ATA_AHCI_P_SACT 0x134 241 #define ATA_AHCI_P_CI 0x138 242 #define ATA_AHCI_P_SNTF 0x13C 243 #define ATA_AHCI_P_FBS 0x140 244 245 #define ATA_AHCI_CL_SIZE 32 246 #define ATA_AHCI_CL_OFFSET 0 247 #define ATA_AHCI_FB_OFFSET (ATA_AHCI_CL_SIZE * 32) 248 #define ATA_AHCI_CT_OFFSET (ATA_AHCI_FB_OFFSET + 4096) 249 #define ATA_AHCI_CT_SIZE (1024 + 128) 250 251 struct ata_ahci_dma_prd { 252 u_int64_t dba; 253 u_int32_t reserved; 254 u_int32_t dbc; /* 0 based */ 255 #define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */ 256 #define ATA_AHCI_PRD_IPC (1<<31) 257 } __packed; 258 259 struct ata_ahci_cmd_tab { 260 u_int8_t cfis[64]; 261 u_int8_t acmd[32]; 262 u_int8_t reserved[32]; 263 #define ATA_AHCI_DMA_ENTRIES 64 264 struct ata_ahci_dma_prd prd_tab[ATA_AHCI_DMA_ENTRIES]; 265 } __packed; 266 267 struct ata_ahci_cmd_list { 268 u_int16_t cmd_flags; 269 #define ATA_AHCI_CMD_ATAPI 0x0020 270 #define ATA_AHCI_CMD_WRITE 0x0040 271 #define ATA_AHCI_CMD_PREFETCH 0x0080 272 #define ATA_AHCI_CMD_RESET 0x0100 273 #define ATA_AHCI_CMD_BIST 0x0200 274 #define ATA_AHCI_CMD_CLR_BUSY 0x0400 275 276 u_int16_t prd_length; /* PRD entries */ 277 u_int32_t bytecount; 278 u_int64_t cmd_table_phys; /* 128byte aligned */ 279 } __packed; 280 281 282 /* DMA register defines */ 283 #define ATA_DMA_ENTRIES 256 284 #define ATA_DMA_EOT 0x80000000 285 286 #define ATA_BMCMD_PORT 17 287 #define ATA_BMCMD_START_STOP 0x01 288 #define ATA_BMCMD_WRITE_READ 0x08 289 290 #define ATA_BMDEVSPEC_0 18 291 #define ATA_BMSTAT_PORT 19 292 #define ATA_BMSTAT_ACTIVE 0x01 293 #define ATA_BMSTAT_ERROR 0x02 294 #define ATA_BMSTAT_INTERRUPT 0x04 295 #define ATA_BMSTAT_MASK 0x07 296 #define ATA_BMSTAT_DMA_MASTER 0x20 297 #define ATA_BMSTAT_DMA_SLAVE 0x40 298 #define ATA_BMSTAT_DMA_SIMPLEX 0x80 299 300 #define ATA_BMDEVSPEC_1 20 301 #define ATA_BMDTP_PORT 21 302 303 #define ATA_IDX_ADDR 22 304 #define ATA_IDX_DATA 23 305 #define ATA_MAX_RES 24 306 307 /* misc defines */ 308 #define ATA_PRIMARY 0x1f0 309 #define ATA_SECONDARY 0x170 310 #define ATA_PC98_BANK 0x432 311 #define ATA_IOSIZE 0x08 312 #define ATA_PC98_IOSIZE 0x10 313 #define ATA_CTLIOSIZE 0x01 314 #define ATA_BMIOSIZE 0x08 315 #define ATA_PC98_BANKIOSIZE 0x01 316 #define ATA_IOADDR_RID 0 317 #define ATA_CTLADDR_RID 1 318 #define ATA_BMADDR_RID 0x20 319 #define ATA_PC98_CTLADDR_RID 8 320 #define ATA_PC98_BANKADDR_RID 9 321 #define ATA_IRQ_RID 0 322 #define ATA_DEV(unit) ((unit > 0) ? 0x10 : 0) 323 #define ATA_CFA_MAGIC1 0x844A 324 #define ATA_CFA_MAGIC2 0x848A 325 #define ATA_CFA_MAGIC3 0x8400 326 #define ATAPI_MAGIC_LSB 0x14 327 #define ATAPI_MAGIC_MSB 0xeb 328 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 329 #define ATAPI_P_WRITE (ATA_S_DRQ) 330 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 331 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 332 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 333 #define ATAPI_P_ABORT 0 334 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 335 #define ATA_OP_CONTINUES 0 336 #define ATA_OP_FINISHED 1 337 #define ATA_MAX_28BIT_LBA 268435455UL 338 339 /* structure used for composite atomic operations */ 340 #define MAX_COMPOSITES 32 /* u_int32_t bits */ 341 struct ata_composite { 342 struct mtx lock; /* control lock */ 343 u_int32_t rd_needed; /* needed read subdisks */ 344 u_int32_t rd_done; /* done read subdisks */ 345 u_int32_t wr_needed; /* needed write subdisks */ 346 u_int32_t wr_depend; /* write depends on subdisks */ 347 u_int32_t wr_done; /* done write subdisks */ 348 struct ata_request *request[MAX_COMPOSITES]; 349 u_int32_t residual; /* bytes still to transfer */ 350 caddr_t data_1; 351 caddr_t data_2; 352 }; 353 354 /* structure used to queue an ATA/ATAPI request */ 355 struct ata_request { 356 device_t dev; /* device handle */ 357 device_t parent; /* channel handle */ 358 union { 359 struct { 360 u_int8_t command; /* command reg */ 361 u_int16_t feature; /* feature reg */ 362 u_int16_t count; /* count reg */ 363 u_int64_t lba; /* lba reg */ 364 } ata; 365 struct { 366 u_int8_t ccb[16]; /* ATAPI command block */ 367 struct atapi_sense sense; /* ATAPI request sense data */ 368 u_int8_t saved_cmd; /* ATAPI saved command */ 369 } atapi; 370 } u; 371 u_int32_t bytecount; /* bytes to transfer */ 372 u_int32_t transfersize; /* bytes pr transfer */ 373 caddr_t data; /* pointer to data buf */ 374 u_int32_t tag; /* HW tag of this request */ 375 int flags; 376 #define ATA_R_CONTROL 0x00000001 377 #define ATA_R_READ 0x00000002 378 #define ATA_R_WRITE 0x00000004 379 #define ATA_R_ATAPI 0x00000008 380 #define ATA_R_DMA 0x00000010 381 #define ATA_R_QUIET 0x00000020 382 #define ATA_R_TIMEOUT 0x00000040 383 384 #define ATA_R_ORDERED 0x00000100 385 #define ATA_R_AT_HEAD 0x00000200 386 #define ATA_R_REQUEUE 0x00000400 387 #define ATA_R_THREAD 0x00000800 388 #define ATA_R_DIRECT 0x00001000 389 390 #define ATA_R_DEBUG 0x10000000 391 #define ATA_R_DANGER1 0x20000000 392 #define ATA_R_DANGER2 0x40000000 393 394 struct ata_dmaslot *dma; /* DMA slot of this request */ 395 u_int8_t status; /* ATA status */ 396 u_int8_t error; /* ATA error */ 397 u_int32_t donecount; /* bytes transferred */ 398 int result; /* result error code */ 399 void (*callback)(struct ata_request *request); 400 struct sema done; /* request done sema */ 401 int retries; /* retry count */ 402 int timeout; /* timeout for this cmd */ 403 struct callout callout; /* callout management */ 404 struct task task; /* task management */ 405 struct bio *bio; /* bio for this request */ 406 int this; /* this request ID */ 407 struct ata_composite *composite; /* for composite atomic ops */ 408 void *driver; /* driver specific */ 409 TAILQ_ENTRY(ata_request) chain; /* list management */ 410 }; 411 412 /* define this for debugging request processing */ 413 #if 0 414 #define ATA_DEBUG_RQ(request, string) \ 415 { \ 416 if (request->flags & ATA_R_DEBUG) \ 417 device_printf(request->dev, "req=%p %s " string "\n", \ 418 request, ata_cmd2str(request)); \ 419 } 420 #else 421 #define ATA_DEBUG_RQ(request, string) 422 #endif 423 424 425 /* structure describing an ATA/ATAPI device */ 426 struct ata_device { 427 device_t dev; /* device handle */ 428 int unit; /* physical unit */ 429 #define ATA_MASTER 0x00 430 #define ATA_SLAVE 0x01 431 #define ATA_PM 0x0f 432 433 struct ata_params param; /* ata param structure */ 434 int mode; /* current transfermode */ 435 u_int32_t max_iosize; /* max IO size */ 436 int spindown; /* idle spindown timeout */ 437 struct callout spindown_timer; 438 int spindown_state; 439 int flags; 440 #define ATA_D_USE_CHS 0x0001 441 #define ATA_D_MEDIA_CHANGED 0x0002 442 #define ATA_D_ENC_PRESENT 0x0004 443 #define ATA_D_48BIT_ACTIVE 0x0008 444 }; 445 446 /* structure for holding DMA Physical Region Descriptors (PRD) entries */ 447 struct ata_dma_prdentry { 448 u_int32_t addr; 449 u_int32_t count; 450 }; 451 452 /* structure used by the setprd function */ 453 struct ata_dmasetprd_args { 454 void *dmatab; 455 int nsegs; 456 int error; 457 }; 458 459 struct ata_dmaslot { 460 u_int8_t status; /* DMA status */ 461 bus_dma_tag_t sg_tag; /* SG list DMA tag */ 462 bus_dmamap_t sg_map; /* SG list DMA map */ 463 void *sg; /* DMA transfer table */ 464 bus_addr_t sg_bus; /* bus address of dmatab */ 465 bus_dma_tag_t data_tag; /* data DMA tag */ 466 bus_dmamap_t data_map; /* data DMA map */ 467 }; 468 469 /* structure holding DMA related information */ 470 struct ata_dma { 471 bus_dma_tag_t dmatag; /* parent DMA tag */ 472 bus_dma_tag_t work_tag; /* workspace DMA tag */ 473 bus_dmamap_t work_map; /* workspace DMA map */ 474 u_int8_t *work; /* workspace */ 475 bus_addr_t work_bus; /* bus address of dmatab */ 476 477 #define ATA_DMA_SLOTS 32 478 int dma_slots; /* DMA slots allocated */ 479 struct ata_dmaslot slot[ATA_DMA_SLOTS]; 480 u_int32_t alignment; /* DMA SG list alignment */ 481 u_int32_t boundary; /* DMA SG list boundary */ 482 u_int32_t segsize; /* DMA SG list segment size */ 483 u_int32_t max_iosize; /* DMA data max IO size */ 484 u_int64_t max_address; /* highest DMA'able address */ 485 int flags; 486 #define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress */ 487 488 void (*alloc)(device_t dev); 489 void (*free)(device_t dev); 490 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 491 int (*load)(struct ata_request *request, void *addr, int *nsegs); 492 int (*unload)(struct ata_request *request); 493 int (*start)(struct ata_request *request); 494 int (*stop)(struct ata_request *request); 495 void (*reset)(device_t dev); 496 }; 497 498 /* structure holding lowlevel functions */ 499 struct ata_lowlevel { 500 u_int32_t (*softreset)(device_t dev, int pmport); 501 int (*pm_read)(device_t dev, int port, int reg, u_int32_t *result); 502 int (*pm_write)(device_t dev, int port, int reg, u_int32_t value); 503 int (*status)(device_t dev); 504 int (*begin_transaction)(struct ata_request *request); 505 int (*end_transaction)(struct ata_request *request); 506 int (*command)(struct ata_request *request); 507 void (*tf_read)(struct ata_request *request); 508 void (*tf_write)(struct ata_request *request); 509 }; 510 511 /* structure holding resources for an ATA channel */ 512 struct ata_resource { 513 struct resource *res; 514 int offset; 515 }; 516 517 /* structure describing an ATA channel */ 518 struct ata_channel { 519 device_t dev; /* device handle */ 520 int unit; /* physical channel */ 521 int attached; /* channel is attached */ 522 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ 523 struct resource *r_irq; /* interrupt of this channel */ 524 void *ih; /* interrupt handle */ 525 struct ata_lowlevel hw; /* lowlevel HW functions */ 526 struct ata_dma dma; /* DMA data / functions */ 527 int flags; /* channel flags */ 528 #define ATA_NO_SLAVE 0x01 529 #define ATA_USE_16BIT 0x02 530 #define ATA_ATAPI_DMA_RO 0x04 531 #define ATA_NO_48BIT_DMA 0x08 532 #define ATA_ALWAYS_DMASTAT 0x10 533 534 int pm_level; /* power management level */ 535 int devices; /* what is present */ 536 #define ATA_ATA_MASTER 0x00000001 537 #define ATA_ATA_SLAVE 0x00000002 538 #define ATA_PORTMULTIPLIER 0x00008000 539 #define ATA_ATAPI_MASTER 0x00010000 540 #define ATA_ATAPI_SLAVE 0x00020000 541 542 struct mtx state_mtx; /* state lock */ 543 int state; /* ATA channel state */ 544 #define ATA_IDLE 0x0000 545 #define ATA_ACTIVE 0x0001 546 #define ATA_STALL_QUEUE 0x0002 547 548 struct mtx queue_mtx; /* queue lock */ 549 TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */ 550 struct ata_request *freezepoint; /* composite freezepoint */ 551 struct ata_request *running; /* currently running request */ 552 struct task conntask; /* PHY events handling task */ 553 }; 554 555 /* disk bay/enclosure related */ 556 #define ATA_LED_OFF 0x00 557 #define ATA_LED_RED 0x01 558 #define ATA_LED_GREEN 0x02 559 #define ATA_LED_ORANGE 0x03 560 #define ATA_LED_MASK 0x03 561 562 /* externs */ 563 extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data); 564 extern struct intr_config_hook *ata_delayed_attach; 565 extern devclass_t ata_devclass; 566 extern int ata_wc; 567 extern int ata_setmax; 568 extern int ata_dma_check_80pin; 569 570 /* public prototypes */ 571 /* ata-all.c: */ 572 int ata_probe(device_t dev); 573 int ata_attach(device_t dev); 574 int ata_detach(device_t dev); 575 int ata_reinit(device_t dev); 576 int ata_suspend(device_t dev); 577 int ata_resume(device_t dev); 578 void ata_interrupt(void *data); 579 int ata_device_ioctl(device_t dev, u_long cmd, caddr_t data); 580 int ata_getparam(struct ata_device *atadev, int init); 581 int ata_identify(device_t dev); 582 void ata_default_registers(device_t dev); 583 void ata_modify_if_48bit(struct ata_request *request); 584 void ata_udelay(int interval); 585 char *ata_unit2str(struct ata_device *atadev); 586 char *ata_mode2str(int mode); 587 int ata_atapi(device_t dev); 588 int ata_pmode(struct ata_params *ap); 589 int ata_wmode(struct ata_params *ap); 590 int ata_umode(struct ata_params *ap); 591 int ata_limit_mode(device_t dev, int mode, int maxmode); 592 593 /* ata-queue.c: */ 594 int ata_controlcmd(device_t dev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count); 595 int ata_atapicmd(device_t dev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout); 596 void ata_queue_request(struct ata_request *request); 597 void ata_start(device_t dev); 598 void ata_finish(struct ata_request *request); 599 void ata_timeout(struct ata_request *); 600 void ata_catch_inflight(device_t dev); 601 void ata_fail_requests(device_t dev); 602 void ata_drop_requests(device_t dev); 603 char *ata_cmd2str(struct ata_request *request); 604 605 /* ata-lowlevel.c: */ 606 void ata_generic_hw(device_t dev); 607 int ata_begin_transaction(struct ata_request *); 608 int ata_end_transaction(struct ata_request *); 609 void ata_generic_reset(device_t dev); 610 int ata_generic_command(struct ata_request *request); 611 612 /* macros for alloc/free of struct ata_request */ 613 extern uma_zone_t ata_request_zone; 614 #define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT | M_ZERO) 615 #define ata_free_request(request) { \ 616 if (!(request->flags & ATA_R_DANGER2)) \ 617 uma_zfree(ata_request_zone, request); \ 618 } 619 620 /* macros for alloc/free of struct ata_composite */ 621 extern uma_zone_t ata_composite_zone; 622 #define ata_alloc_composite() uma_zalloc(ata_composite_zone, M_NOWAIT | M_ZERO) 623 #define ata_free_composite(composite) uma_zfree(ata_composite_zone, composite) 624 625 MALLOC_DECLARE(M_ATA); 626 627 /* misc newbus defines */ 628 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 629 630 /* macros to hide busspace uglyness */ 631 #define ATA_INB(res, offset) \ 632 bus_read_1((res), (offset)) 633 634 #define ATA_INW(res, offset) \ 635 bus_read_2((res), (offset)) 636 #define ATA_INL(res, offset) \ 637 bus_read_4((res), (offset)) 638 #define ATA_INSW(res, offset, addr, count) \ 639 bus_read_multi_2((res), (offset), (addr), (count)) 640 #define ATA_INSW_STRM(res, offset, addr, count) \ 641 bus_read_multi_stream_2((res), (offset), (addr), (count)) 642 #define ATA_INSL(res, offset, addr, count) \ 643 bus_read_multi_4((res), (offset), (addr), (count)) 644 #define ATA_INSL_STRM(res, offset, addr, count) \ 645 bus_read_multi_stream_4((res), (offset), (addr), (count)) 646 #define ATA_OUTB(res, offset, value) \ 647 bus_write_1((res), (offset), (value)) 648 #define ATA_OUTW(res, offset, value) \ 649 bus_write_2((res), (offset), (value)) 650 #define ATA_OUTL(res, offset, value) \ 651 bus_write_4((res), (offset), (value)) 652 #define ATA_OUTSW(res, offset, addr, count) \ 653 bus_write_multi_2((res), (offset), (addr), (count)) 654 #define ATA_OUTSW_STRM(res, offset, addr, count) \ 655 bus_write_multi_stream_2((res), (offset), (addr), (count)) 656 #define ATA_OUTSL(res, offset, addr, count) \ 657 bus_write_multi_4((res), (offset), (addr), (count)) 658 #define ATA_OUTSL_STRM(res, offset, addr, count) \ 659 bus_write_multi_stream_4((res), (offset), (addr), (count)) 660 661 #define ATA_IDX_INB(ch, idx) \ 662 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) 663 664 #define ATA_IDX_INW(ch, idx) \ 665 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) 666 667 #define ATA_IDX_INL(ch, idx) \ 668 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) 669 670 #define ATA_IDX_INSW(ch, idx, addr, count) \ 671 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 672 673 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 674 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 675 676 #define ATA_IDX_INSL(ch, idx, addr, count) \ 677 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 678 679 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 680 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 681 682 #define ATA_IDX_OUTB(ch, idx, value) \ 683 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) 684 685 #define ATA_IDX_OUTW(ch, idx, value) \ 686 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) 687 688 #define ATA_IDX_OUTL(ch, idx, value) \ 689 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) 690 691 #define ATA_IDX_OUTSW(ch, idx, addr, count) \ 692 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 693 694 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 695 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 696 697 #define ATA_IDX_OUTSL(ch, idx, addr, count) \ 698 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 699 700 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 701 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 702