1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #if 0 30 #define ATA_LEGACY_SUPPORT /* Enable obsolete features that break 31 * some modern devices */ 32 #endif 33 34 /* ATA register defines */ 35 #define ATA_DATA 0 /* (RW) data */ 36 37 #define ATA_FEATURE 1 /* (W) feature */ 38 #define ATA_F_DMA 0x01 /* enable DMA */ 39 #define ATA_F_OVL 0x02 /* enable overlap */ 40 41 #define ATA_COUNT 2 /* (W) sector count */ 42 43 #define ATA_SECTOR 3 /* (RW) sector # */ 44 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 45 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 46 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 47 #define ATA_D_LBA 0x40 /* use LBA addressing */ 48 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 49 50 #define ATA_COMMAND 7 /* (W) command */ 51 52 #define ATA_ERROR 8 /* (R) error */ 53 #define ATA_E_ILI 0x01 /* illegal length */ 54 #define ATA_E_NM 0x02 /* no media */ 55 #define ATA_E_ABORT 0x04 /* command aborted */ 56 #define ATA_E_MCR 0x08 /* media change request */ 57 #define ATA_E_IDNF 0x10 /* ID not found */ 58 #define ATA_E_MC 0x20 /* media changed */ 59 #define ATA_E_UNC 0x40 /* uncorrectable data */ 60 #define ATA_E_ICRC 0x80 /* UDMA crc error */ 61 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 62 63 #define ATA_IREASON 9 /* (R) interrupt reason */ 64 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 65 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 66 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 67 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 68 69 #define ATA_STATUS 10 /* (R) status */ 70 #define ATA_ALTSTAT 11 /* (R) alternate status */ 71 #define ATA_S_ERROR 0x01 /* error */ 72 #define ATA_S_INDEX 0x02 /* index */ 73 #define ATA_S_CORR 0x04 /* data corrected */ 74 #define ATA_S_DRQ 0x08 /* data request */ 75 #define ATA_S_DSC 0x10 /* drive seek completed */ 76 #define ATA_S_SERVICE 0x10 /* drive needs service */ 77 #define ATA_S_DWF 0x20 /* drive write fault */ 78 #define ATA_S_DMA 0x20 /* DMA ready */ 79 #define ATA_S_READY 0x40 /* drive ready */ 80 #define ATA_S_BUSY 0x80 /* busy */ 81 82 #define ATA_CONTROL 12 /* (W) control */ 83 84 #define ATA_CTLOFFSET 0x206 /* control register offset */ 85 #define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */ 86 #define ATA_A_IDS 0x02 /* disable interrupts */ 87 #define ATA_A_RESET 0x04 /* RESET controller */ 88 #ifdef ATA_LEGACY_SUPPORT 89 #define ATA_A_4BIT 0x08 /* 4 head bits: obsolete 1996 */ 90 #else 91 #define ATA_A_4BIT 0x00 92 #endif 93 #define ATA_A_HOB 0x80 /* High Order Byte enable */ 94 95 /* SATA register defines */ 96 #define ATA_SSTATUS 13 97 #define ATA_SS_DET_MASK 0x0000000f 98 #define ATA_SS_DET_NO_DEVICE 0x00000000 99 #define ATA_SS_DET_DEV_PRESENT 0x00000001 100 #define ATA_SS_DET_PHY_ONLINE 0x00000003 101 #define ATA_SS_DET_PHY_OFFLINE 0x00000004 102 103 #define ATA_SS_SPD_MASK 0x000000f0 104 #define ATA_SS_SPD_NO_SPEED 0x00000000 105 #define ATA_SS_SPD_GEN1 0x00000010 106 #define ATA_SS_SPD_GEN2 0x00000020 107 #define ATA_SS_SPD_GEN3 0x00000030 108 109 #define ATA_SS_IPM_MASK 0x00000f00 110 #define ATA_SS_IPM_NO_DEVICE 0x00000000 111 #define ATA_SS_IPM_ACTIVE 0x00000100 112 #define ATA_SS_IPM_PARTIAL 0x00000200 113 #define ATA_SS_IPM_SLUMBER 0x00000600 114 115 #define ATA_SERROR 14 116 #define ATA_SE_DATA_CORRECTED 0x00000001 117 #define ATA_SE_COMM_CORRECTED 0x00000002 118 #define ATA_SE_DATA_ERR 0x00000100 119 #define ATA_SE_COMM_ERR 0x00000200 120 #define ATA_SE_PROT_ERR 0x00000400 121 #define ATA_SE_HOST_ERR 0x00000800 122 #define ATA_SE_PHY_CHANGED 0x00010000 123 #define ATA_SE_PHY_IERROR 0x00020000 124 #define ATA_SE_COMM_WAKE 0x00040000 125 #define ATA_SE_DECODE_ERR 0x00080000 126 #define ATA_SE_PARITY_ERR 0x00100000 127 #define ATA_SE_CRC_ERR 0x00200000 128 #define ATA_SE_HANDSHAKE_ERR 0x00400000 129 #define ATA_SE_LINKSEQ_ERR 0x00800000 130 #define ATA_SE_TRANSPORT_ERR 0x01000000 131 #define ATA_SE_UNKNOWN_FIS 0x02000000 132 133 #define ATA_SCONTROL 15 134 #define ATA_SC_DET_MASK 0x0000000f 135 #define ATA_SC_DET_IDLE 0x00000000 136 #define ATA_SC_DET_RESET 0x00000001 137 #define ATA_SC_DET_DISABLE 0x00000004 138 139 #define ATA_SC_SPD_MASK 0x000000f0 140 #define ATA_SC_SPD_NO_SPEED 0x00000000 141 #define ATA_SC_SPD_SPEED_GEN1 0x00000010 142 #define ATA_SC_SPD_SPEED_GEN2 0x00000020 143 #define ATA_SC_SPD_SPEED_GEN3 0x00000030 144 145 #define ATA_SC_IPM_MASK 0x00000f00 146 #define ATA_SC_IPM_NONE 0x00000000 147 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100 148 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200 149 150 #define ATA_SACTIVE 16 151 152 /* DMA register defines */ 153 #define ATA_DMA_ENTRIES MAX(17, btoc(maxphys) + 1) 154 #define ATA_DMA_EOT 0x80000000 155 156 #define ATA_BMCMD_PORT 17 157 #define ATA_BMCMD_START_STOP 0x01 158 #define ATA_BMCMD_WRITE_READ 0x08 159 160 #define ATA_BMDEVSPEC_0 18 161 #define ATA_BMSTAT_PORT 19 162 #define ATA_BMSTAT_ACTIVE 0x01 163 #define ATA_BMSTAT_ERROR 0x02 164 #define ATA_BMSTAT_INTERRUPT 0x04 165 #define ATA_BMSTAT_MASK 0x07 166 #define ATA_BMSTAT_DMA_MASTER 0x20 167 #define ATA_BMSTAT_DMA_SLAVE 0x40 168 #define ATA_BMSTAT_DMA_SIMPLEX 0x80 169 170 #define ATA_BMDEVSPEC_1 20 171 #define ATA_BMDTP_PORT 21 172 173 #define ATA_IDX_ADDR 22 174 #define ATA_IDX_DATA 23 175 #define ATA_MAX_RES 24 176 177 /* misc defines */ 178 #define ATA_PRIMARY 0x1f0 179 #define ATA_SECONDARY 0x170 180 #define ATA_IOSIZE 0x08 181 #define ATA_CTLIOSIZE 0x01 182 #define ATA_BMIOSIZE 0x08 183 #define ATA_IOADDR_RID 0 184 #define ATA_CTLADDR_RID 1 185 #define ATA_BMADDR_RID 0x20 186 #define ATA_IRQ_RID 0 187 #define ATA_DEV(unit) ((unit > 0) ? 0x10 : 0) 188 #define ATA_CFA_MAGIC1 0x844A 189 #define ATA_CFA_MAGIC2 0x848A 190 #define ATA_CFA_MAGIC3 0x8400 191 #define ATAPI_MAGIC_LSB 0x14 192 #define ATAPI_MAGIC_MSB 0xeb 193 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 194 #define ATAPI_P_WRITE (ATA_S_DRQ) 195 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 196 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 197 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 198 #define ATAPI_P_ABORT 0 199 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 200 #define ATA_OP_CONTINUES 0 201 #define ATA_OP_FINISHED 1 202 #define ATA_MAX_28BIT_LBA 268435455UL 203 204 /* structure used for composite atomic operations */ 205 #define MAX_COMPOSITES 32 /* u_int32_t bits */ 206 struct ata_composite { 207 struct mtx lock; /* control lock */ 208 u_int32_t rd_needed; /* needed read subdisks */ 209 u_int32_t rd_done; /* done read subdisks */ 210 u_int32_t wr_needed; /* needed write subdisks */ 211 u_int32_t wr_depend; /* write depends on subdisks */ 212 u_int32_t wr_done; /* done write subdisks */ 213 struct ata_request *request[MAX_COMPOSITES]; 214 u_int32_t residual; /* bytes still to transfer */ 215 caddr_t data_1; 216 caddr_t data_2; 217 }; 218 219 /* structure used to queue an ATA/ATAPI request */ 220 struct ata_request { 221 device_t dev; /* device handle */ 222 device_t parent; /* channel handle */ 223 int unit; /* physical unit */ 224 union { 225 struct { 226 u_int8_t command; /* command reg */ 227 u_int16_t feature; /* feature reg */ 228 u_int16_t count; /* count reg */ 229 u_int64_t lba; /* lba reg */ 230 } ata; 231 struct { 232 u_int8_t ccb[16]; /* ATAPI command block */ 233 struct atapi_sense sense; /* ATAPI request sense data */ 234 u_int8_t saved_cmd; /* ATAPI saved command */ 235 } atapi; 236 } u; 237 u_int32_t bytecount; /* bytes to transfer */ 238 u_int32_t transfersize; /* bytes pr transfer */ 239 caddr_t data; /* pointer to data buf */ 240 u_int32_t tag; /* HW tag of this request */ 241 int flags; 242 #define ATA_R_CONTROL 0x00000001 243 #define ATA_R_READ 0x00000002 244 #define ATA_R_WRITE 0x00000004 245 #define ATA_R_ATAPI 0x00000008 246 #define ATA_R_DMA 0x00000010 247 #define ATA_R_QUIET 0x00000020 248 #define ATA_R_TIMEOUT 0x00000040 249 #define ATA_R_48BIT 0x00000080 250 251 #define ATA_R_ORDERED 0x00000100 252 #define ATA_R_AT_HEAD 0x00000200 253 #define ATA_R_REQUEUE 0x00000400 254 #define ATA_R_THREAD 0x00000800 255 #define ATA_R_DIRECT 0x00001000 256 #define ATA_R_NEEDRESULT 0x00002000 257 #define ATA_R_DATA_IN_CCB 0x00004000 258 259 #define ATA_R_ATAPI16 0x00010000 260 #define ATA_R_ATAPI_INTR 0x00020000 261 262 #define ATA_R_DEBUG 0x10000000 263 #define ATA_R_DANGER1 0x20000000 264 #define ATA_R_DANGER2 0x40000000 265 266 struct ata_dmaslot *dma; /* DMA slot of this request */ 267 u_int8_t status; /* ATA status */ 268 u_int8_t error; /* ATA error */ 269 u_int32_t donecount; /* bytes transferred */ 270 int result; /* result error code */ 271 void (*callback)(struct ata_request *request); 272 struct sema done; /* request done sema */ 273 int retries; /* retry count */ 274 int timeout; /* timeout for this cmd */ 275 struct callout callout; /* callout management */ 276 struct task task; /* task management */ 277 struct bio *bio; /* bio for this request */ 278 int this; /* this request ID */ 279 struct ata_composite *composite; /* for composite atomic ops */ 280 void *driver; /* driver specific */ 281 TAILQ_ENTRY(ata_request) chain; /* list management */ 282 union ccb *ccb; 283 }; 284 285 /* define this for debugging request processing */ 286 #if 0 287 #define ATA_DEBUG_RQ(request, string) \ 288 { \ 289 if (request->flags & ATA_R_DEBUG) \ 290 device_printf(request->parent, "req=%p %s " string "\n", \ 291 request, ata_cmd2str(request)); \ 292 } 293 #else 294 #define ATA_DEBUG_RQ(request, string) 295 #endif 296 297 /* structure describing an ATA/ATAPI device */ 298 struct ata_device { 299 device_t dev; /* device handle */ 300 int unit; /* physical unit */ 301 #define ATA_MASTER 0x00 302 #define ATA_SLAVE 0x01 303 #define ATA_PM 0x0f 304 305 struct ata_params param; /* ata param structure */ 306 int mode; /* current transfermode */ 307 u_int32_t max_iosize; /* max IO size */ 308 int spindown; /* idle spindown timeout */ 309 struct callout spindown_timer; 310 int spindown_state; 311 int flags; 312 #define ATA_D_USE_CHS 0x0001 313 #define ATA_D_MEDIA_CHANGED 0x0002 314 #define ATA_D_ENC_PRESENT 0x0004 315 }; 316 317 /* structure for holding DMA Physical Region Descriptors (PRD) entries */ 318 struct ata_dma_prdentry { 319 u_int32_t addr; 320 u_int32_t count; 321 }; 322 323 /* structure used by the setprd function */ 324 struct ata_dmasetprd_args { 325 void *dmatab; 326 int nsegs; 327 int error; 328 }; 329 330 struct ata_dmaslot { 331 u_int8_t status; /* DMA status */ 332 bus_dma_tag_t sg_tag; /* SG list DMA tag */ 333 bus_dmamap_t sg_map; /* SG list DMA map */ 334 void *sg; /* DMA transfer table */ 335 bus_addr_t sg_bus; /* bus address of dmatab */ 336 bus_dma_tag_t data_tag; /* data DMA tag */ 337 bus_dmamap_t data_map; /* data DMA map */ 338 }; 339 340 /* structure holding DMA related information */ 341 struct ata_dma { 342 bus_dma_tag_t dmatag; /* parent DMA tag */ 343 bus_dma_tag_t work_tag; /* workspace DMA tag */ 344 bus_dmamap_t work_map; /* workspace DMA map */ 345 u_int8_t *work; /* workspace */ 346 bus_addr_t work_bus; /* bus address of dmatab */ 347 348 #define ATA_DMA_SLOTS 1 349 int dma_slots; /* DMA slots allocated */ 350 struct ata_dmaslot slot[ATA_DMA_SLOTS]; 351 u_int32_t alignment; /* DMA SG list alignment */ 352 u_int32_t boundary; /* DMA SG list boundary */ 353 u_int32_t segsize; /* DMA SG list segment size */ 354 u_int32_t max_iosize; /* DMA data max IO size */ 355 u_int64_t max_address; /* highest DMA'able address */ 356 int flags; 357 #define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress */ 358 359 void (*alloc)(device_t dev); 360 void (*free)(device_t dev); 361 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 362 int (*load)(struct ata_request *request, void *addr, int *nsegs); 363 int (*unload)(struct ata_request *request); 364 int (*start)(struct ata_request *request); 365 int (*stop)(struct ata_request *request); 366 void (*reset)(device_t dev); 367 }; 368 369 /* structure holding lowlevel functions */ 370 struct ata_lowlevel { 371 u_int32_t (*softreset)(device_t dev, int pmport); 372 int (*pm_read)(device_t dev, int port, int reg, u_int32_t *result); 373 int (*pm_write)(device_t dev, int port, int reg, u_int32_t value); 374 int (*status)(device_t dev); 375 int (*begin_transaction)(struct ata_request *request); 376 int (*end_transaction)(struct ata_request *request); 377 int (*command)(struct ata_request *request); 378 void (*tf_read)(struct ata_request *request); 379 void (*tf_write)(struct ata_request *request); 380 }; 381 382 /* structure holding resources for an ATA channel */ 383 struct ata_resource { 384 struct resource *res; 385 int offset; 386 }; 387 388 struct ata_cam_device { 389 u_int revision; 390 int mode; 391 u_int bytecount; 392 u_int atapi; 393 u_int caps; 394 }; 395 396 /* structure describing an ATA channel */ 397 struct ata_channel { 398 device_t dev; /* device handle */ 399 int unit; /* physical channel */ 400 int attached; /* channel is attached */ 401 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ 402 struct resource *r_irq; /* interrupt of this channel */ 403 void *ih; /* interrupt handle */ 404 struct ata_lowlevel hw; /* lowlevel HW functions */ 405 struct ata_dma dma; /* DMA data / functions */ 406 int flags; /* channel flags */ 407 #define ATA_NO_SLAVE 0x01 408 #define ATA_USE_16BIT 0x02 409 #define ATA_ATAPI_DMA_RO 0x04 410 #define ATA_NO_48BIT_DMA 0x08 411 #define ATA_ALWAYS_DMASTAT 0x10 412 #define ATA_CHECKS_CABLE 0x20 413 #define ATA_NO_ATAPI_DMA 0x40 414 #define ATA_SATA 0x80 415 #define ATA_DMA_BEFORE_CMD 0x100 416 #define ATA_KNOWN_PRESENCE 0x200 417 #define ATA_STATUS_IS_LONG 0x400 418 #define ATA_PERIODIC_POLL 0x800 419 420 int pm_level; /* power management level */ 421 int devices; /* what is present */ 422 #define ATA_ATA_MASTER 0x00000001 423 #define ATA_ATA_SLAVE 0x00000002 424 #define ATA_PORTMULTIPLIER 0x00008000 425 #define ATA_ATAPI_MASTER 0x00010000 426 #define ATA_ATAPI_SLAVE 0x00020000 427 428 struct mtx state_mtx; /* state lock */ 429 int state; /* ATA channel state */ 430 #define ATA_IDLE 0x0000 431 #define ATA_ACTIVE 0x0001 432 #define ATA_STALL_QUEUE 0x0002 433 434 struct ata_request *running; /* currently running request */ 435 struct task conntask; /* PHY events handling task */ 436 struct cam_sim *sim; 437 struct cam_path *path; 438 struct ata_cam_device user[16]; /* User-specified settings */ 439 struct ata_cam_device curr[16]; /* Current settings */ 440 int requestsense; /* CCB waiting for SENSE. */ 441 struct callout poll_callout; /* Periodic status poll. */ 442 struct ata_request request; 443 }; 444 445 /* disk bay/enclosure related */ 446 #define ATA_LED_OFF 0x00 447 #define ATA_LED_RED 0x01 448 #define ATA_LED_GREEN 0x02 449 #define ATA_LED_ORANGE 0x03 450 #define ATA_LED_MASK 0x03 451 452 /* externs */ 453 extern devclass_t ata_devclass; 454 extern int ata_dma_check_80pin; 455 456 /* public prototypes */ 457 /* ata-all.c: */ 458 int ata_probe(device_t dev); 459 int ata_attach(device_t dev); 460 int ata_detach(device_t dev); 461 int ata_reinit(device_t dev); 462 int ata_suspend(device_t dev); 463 int ata_resume(device_t dev); 464 void ata_interrupt(void *data); 465 int ata_getparam(struct ata_device *atadev, int init); 466 void ata_default_registers(device_t dev); 467 void ata_udelay(int interval); 468 const char *ata_cmd2str(struct ata_request *request); 469 const char *ata_mode2str(int mode); 470 void ata_setmode(device_t dev); 471 void ata_print_cable(device_t dev, u_int8_t *who); 472 int ata_atapi(device_t dev, int target); 473 void ata_timeout(void *); 474 475 /* ata-lowlevel.c: */ 476 void ata_generic_hw(device_t dev); 477 int ata_begin_transaction(struct ata_request *); 478 int ata_end_transaction(struct ata_request *); 479 void ata_generic_reset(device_t dev); 480 int ata_generic_command(struct ata_request *request); 481 482 /* ata-dma.c: */ 483 void ata_dmainit(device_t); 484 void ata_dmafini(device_t dev); 485 486 /* ata-sata.c: */ 487 void ata_sata_phy_check_events(device_t dev, int port); 488 int ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val); 489 int ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val); 490 int ata_sata_phy_reset(device_t dev, int port, int quick); 491 int ata_sata_setmode(device_t dev, int target, int mode); 492 int ata_sata_getrev(device_t dev, int target); 493 int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis); 494 void ata_pm_identify(device_t dev); 495 496 MALLOC_DECLARE(M_ATA); 497 498 /* misc newbus defines */ 499 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 500 501 /* macros to hide busspace uglyness */ 502 #define ATA_INB(res, offset) \ 503 bus_read_1((res), (offset)) 504 505 #define ATA_INW(res, offset) \ 506 bus_read_2((res), (offset)) 507 #define ATA_INW_STRM(res, offset) \ 508 bus_read_stream_2((res), (offset)) 509 #define ATA_INL(res, offset) \ 510 bus_read_4((res), (offset)) 511 #define ATA_INSW(res, offset, addr, count) \ 512 bus_read_multi_2((res), (offset), (addr), (count)) 513 #define ATA_INSW_STRM(res, offset, addr, count) \ 514 bus_read_multi_stream_2((res), (offset), (addr), (count)) 515 #define ATA_INSL(res, offset, addr, count) \ 516 bus_read_multi_4((res), (offset), (addr), (count)) 517 #define ATA_INSL_STRM(res, offset, addr, count) \ 518 bus_read_multi_stream_4((res), (offset), (addr), (count)) 519 #define ATA_OUTB(res, offset, value) \ 520 bus_write_1((res), (offset), (value)) 521 #define ATA_OUTW(res, offset, value) \ 522 bus_write_2((res), (offset), (value)) 523 #define ATA_OUTW_STRM(res, offset, value) \ 524 bus_write_stream_2((res), (offset), (value)) 525 #define ATA_OUTL(res, offset, value) \ 526 bus_write_4((res), (offset), (value)) 527 #define ATA_OUTSW(res, offset, addr, count) \ 528 bus_write_multi_2((res), (offset), (addr), (count)) 529 #define ATA_OUTSW_STRM(res, offset, addr, count) \ 530 bus_write_multi_stream_2((res), (offset), (addr), (count)) 531 #define ATA_OUTSL(res, offset, addr, count) \ 532 bus_write_multi_4((res), (offset), (addr), (count)) 533 #define ATA_OUTSL_STRM(res, offset, addr, count) \ 534 bus_write_multi_stream_4((res), (offset), (addr), (count)) 535 536 #define ATA_IDX_INB(ch, idx) \ 537 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) 538 539 #define ATA_IDX_INW(ch, idx) \ 540 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) 541 542 #define ATA_IDX_INW_STRM(ch, idx) \ 543 ATA_INW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset) 544 545 #define ATA_IDX_INL(ch, idx) \ 546 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) 547 548 #define ATA_IDX_INSW(ch, idx, addr, count) \ 549 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 550 551 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 552 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 553 554 #define ATA_IDX_INSL(ch, idx, addr, count) \ 555 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 556 557 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 558 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 559 560 #define ATA_IDX_OUTB(ch, idx, value) \ 561 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) 562 563 #define ATA_IDX_OUTW(ch, idx, value) \ 564 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) 565 566 #define ATA_IDX_OUTW_STRM(ch, idx, value) \ 567 ATA_OUTW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, value) 568 569 #define ATA_IDX_OUTL(ch, idx, value) \ 570 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) 571 572 #define ATA_IDX_OUTSW(ch, idx, addr, count) \ 573 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 574 575 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 576 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 577 578 #define ATA_IDX_OUTSL(ch, idx, addr, count) \ 579 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 580 581 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 582 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 583