1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* ATA register defines */ 30 #define ATA_DATA 0 /* (RW) data */ 31 32 #define ATA_FEATURE 1 /* (W) feature */ 33 #define ATA_F_DMA 0x01 /* enable DMA */ 34 #define ATA_F_OVL 0x02 /* enable overlap */ 35 36 #define ATA_COUNT 2 /* (W) sector count */ 37 38 #define ATA_SECTOR 3 /* (RW) sector # */ 39 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 40 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 41 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 42 #define ATA_D_LBA 0x40 /* use LBA addressing */ 43 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 44 45 #define ATA_COMMAND 7 /* (W) command */ 46 47 #define ATA_ERROR 8 /* (R) error */ 48 #define ATA_E_ILI 0x01 /* illegal length */ 49 #define ATA_E_NM 0x02 /* no media */ 50 #define ATA_E_ABORT 0x04 /* command aborted */ 51 #define ATA_E_MCR 0x08 /* media change request */ 52 #define ATA_E_IDNF 0x10 /* ID not found */ 53 #define ATA_E_MC 0x20 /* media changed */ 54 #define ATA_E_UNC 0x40 /* uncorrectable data */ 55 #define ATA_E_ICRC 0x80 /* UDMA crc error */ 56 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 57 58 #define ATA_IREASON 9 /* (R) interrupt reason */ 59 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 60 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 61 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 62 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 63 64 #define ATA_STATUS 10 /* (R) status */ 65 #define ATA_ALTSTAT 11 /* (R) alternate status */ 66 #define ATA_S_ERROR 0x01 /* error */ 67 #define ATA_S_INDEX 0x02 /* index */ 68 #define ATA_S_CORR 0x04 /* data corrected */ 69 #define ATA_S_DRQ 0x08 /* data request */ 70 #define ATA_S_DSC 0x10 /* drive seek completed */ 71 #define ATA_S_SERVICE 0x10 /* drive needs service */ 72 #define ATA_S_DWF 0x20 /* drive write fault */ 73 #define ATA_S_DMA 0x20 /* DMA ready */ 74 #define ATA_S_READY 0x40 /* drive ready */ 75 #define ATA_S_BUSY 0x80 /* busy */ 76 77 #define ATA_CONTROL 12 /* (W) control */ 78 79 #define ATA_CTLOFFSET 0x206 /* control register offset */ 80 #define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */ 81 #define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */ 82 #define ATA_A_IDS 0x02 /* disable interrupts */ 83 #define ATA_A_RESET 0x04 /* RESET controller */ 84 #define ATA_A_4BIT 0x08 /* 4 head bits */ 85 #define ATA_A_HOB 0x80 /* High Order Byte enable */ 86 87 /* SATA register defines */ 88 #define ATA_SSTATUS 13 89 #define ATA_SS_DET_MASK 0x0000000f 90 #define ATA_SS_DET_NO_DEVICE 0x00000000 91 #define ATA_SS_DET_DEV_PRESENT 0x00000001 92 #define ATA_SS_DET_PHY_ONLINE 0x00000003 93 #define ATA_SS_DET_PHY_OFFLINE 0x00000004 94 95 #define ATA_SS_SPD_MASK 0x000000f0 96 #define ATA_SS_SPD_NO_SPEED 0x00000000 97 #define ATA_SS_SPD_GEN1 0x00000010 98 #define ATA_SS_SPD_GEN2 0x00000020 99 100 #define ATA_SS_IPM_MASK 0x00000f00 101 #define ATA_SS_IPM_NO_DEVICE 0x00000000 102 #define ATA_SS_IPM_ACTIVE 0x00000100 103 #define ATA_SS_IPM_PARTIAL 0x00000200 104 #define ATA_SS_IPM_SLUMBER 0x00000600 105 106 #define ATA_SS_CONWELL_MASK \ 107 (ATA_SS_DET_MASK|ATA_SS_SPD_MASK|ATA_SS_IPM_MASK) 108 #define ATA_SS_CONWELL_GEN1 \ 109 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN1|ATA_SS_IPM_ACTIVE) 110 #define ATA_SS_CONWELL_GEN2 \ 111 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN2|ATA_SS_IPM_ACTIVE) 112 113 #define ATA_SERROR 14 114 #define ATA_SE_DATA_CORRECTED 0x00000001 115 #define ATA_SE_COMM_CORRECTED 0x00000002 116 #define ATA_SE_DATA_ERR 0x00000100 117 #define ATA_SE_COMM_ERR 0x00000200 118 #define ATA_SE_PROT_ERR 0x00000400 119 #define ATA_SE_HOST_ERR 0x00000800 120 #define ATA_SE_PHY_CHANGED 0x00010000 121 #define ATA_SE_PHY_IERROR 0x00020000 122 #define ATA_SE_COMM_WAKE 0x00040000 123 #define ATA_SE_DECODE_ERR 0x00080000 124 #define ATA_SE_PARITY_ERR 0x00100000 125 #define ATA_SE_CRC_ERR 0x00200000 126 #define ATA_SE_HANDSHAKE_ERR 0x00400000 127 #define ATA_SE_LINKSEQ_ERR 0x00800000 128 #define ATA_SE_TRANSPORT_ERR 0x01000000 129 #define ATA_SE_UNKNOWN_FIS 0x02000000 130 131 #define ATA_SCONTROL 15 132 #define ATA_SC_DET_MASK 0x0000000f 133 #define ATA_SC_DET_IDLE 0x00000000 134 #define ATA_SC_DET_RESET 0x00000001 135 #define ATA_SC_DET_DISABLE 0x00000004 136 137 #define ATA_SC_SPD_MASK 0x000000f0 138 #define ATA_SC_SPD_NO_SPEED 0x00000000 139 #define ATA_SC_SPD_SPEED_GEN1 0x00000010 140 #define ATA_SC_SPD_SPEED_GEN2 0x00000020 141 142 #define ATA_SC_IPM_MASK 0x00000f00 143 #define ATA_SC_IPM_NONE 0x00000000 144 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100 145 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200 146 147 #define ATA_SACTIVE 16 148 149 /* SATA AHCI v1.0 register defines */ 150 #define ATA_AHCI_CAP 0x00 151 #define ATA_AHCI_CAP_NPMASK 0x0000001f 152 #define ATA_AHCI_CAP_PSC 0x00002000 153 #define ATA_AHCI_CAP_SSC 0x00004000 154 #define ATA_AHCI_CAP_SPM 0x00020000 155 #define ATA_AHCI_CAP_CLO 0x01000000 156 #define ATA_AHCI_CAP_SALP 0x04000000 157 #define ATA_AHCI_CAP_64BIT 0x80000000 158 159 #define ATA_AHCI_GHC 0x04 160 #define ATA_AHCI_GHC_AE 0x80000000 161 #define ATA_AHCI_GHC_IE 0x00000002 162 #define ATA_AHCI_GHC_HR 0x00000001 163 164 #define ATA_AHCI_IS 0x08 165 #define ATA_AHCI_PI 0x0c 166 #define ATA_AHCI_VS 0x10 167 168 #define ATA_AHCI_OFFSET 0x80 169 170 #define ATA_AHCI_P_CLB 0x100 171 #define ATA_AHCI_P_CLBU 0x104 172 #define ATA_AHCI_P_FB 0x108 173 #define ATA_AHCI_P_FBU 0x10c 174 #define ATA_AHCI_P_IS 0x110 175 #define ATA_AHCI_P_IE 0x114 176 #define ATA_AHCI_P_IX_DHR 0x00000001 177 #define ATA_AHCI_P_IX_PS 0x00000002 178 #define ATA_AHCI_P_IX_DS 0x00000004 179 #define ATA_AHCI_P_IX_SDB 0x00000008 180 #define ATA_AHCI_P_IX_UF 0x00000010 181 #define ATA_AHCI_P_IX_DP 0x00000020 182 #define ATA_AHCI_P_IX_PC 0x00000040 183 #define ATA_AHCI_P_IX_DI 0x00000080 184 185 #define ATA_AHCI_P_IX_PRC 0x00400000 186 #define ATA_AHCI_P_IX_IPM 0x00800000 187 #define ATA_AHCI_P_IX_OF 0x01000000 188 #define ATA_AHCI_P_IX_INF 0x04000000 189 #define ATA_AHCI_P_IX_IF 0x08000000 190 #define ATA_AHCI_P_IX_HBD 0x10000000 191 #define ATA_AHCI_P_IX_HBF 0x20000000 192 #define ATA_AHCI_P_IX_TFE 0x40000000 193 #define ATA_AHCI_P_IX_CPD 0x80000000 194 195 #define ATA_AHCI_P_CMD 0x118 196 #define ATA_AHCI_P_CMD_ST 0x00000001 197 #define ATA_AHCI_P_CMD_SUD 0x00000002 198 #define ATA_AHCI_P_CMD_POD 0x00000004 199 #define ATA_AHCI_P_CMD_CLO 0x00000008 200 #define ATA_AHCI_P_CMD_FRE 0x00000010 201 #define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00 202 #define ATA_AHCI_P_CMD_ISS 0x00002000 203 #define ATA_AHCI_P_CMD_FR 0x00004000 204 #define ATA_AHCI_P_CMD_CR 0x00008000 205 #define ATA_AHCI_P_CMD_CPS 0x00010000 206 #define ATA_AHCI_P_CMD_PMA 0x00020000 207 #define ATA_AHCI_P_CMD_HPCP 0x00040000 208 #define ATA_AHCI_P_CMD_ISP 0x00080000 209 #define ATA_AHCI_P_CMD_CPD 0x00100000 210 #define ATA_AHCI_P_CMD_ATAPI 0x01000000 211 #define ATA_AHCI_P_CMD_DLAE 0x02000000 212 #define ATA_AHCI_P_CMD_ALPE 0x04000000 213 #define ATA_AHCI_P_CMD_ASP 0x08000000 214 #define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000 215 #define ATA_AHCI_P_CMD_NOOP 0x00000000 216 #define ATA_AHCI_P_CMD_ACTIVE 0x10000000 217 #define ATA_AHCI_P_CMD_PARTIAL 0x20000000 218 #define ATA_AHCI_P_CMD_SLUMBER 0x60000000 219 220 #define ATA_AHCI_P_TFD 0x120 221 #define ATA_AHCI_P_SIG 0x124 222 #define ATA_AHCI_P_SSTS 0x128 223 #define ATA_AHCI_P_SCTL 0x12c 224 #define ATA_AHCI_P_SERR 0x130 225 #define ATA_AHCI_P_SACT 0x134 226 #define ATA_AHCI_P_CI 0x138 227 #define ATA_AHCI_P_SNTF 0x13C 228 #define ATA_AHCI_P_FBS 0x140 229 230 #define ATA_AHCI_CL_SIZE 32 231 #define ATA_AHCI_CL_OFFSET 0 232 #define ATA_AHCI_FB_OFFSET (ATA_AHCI_CL_SIZE * 32) 233 #define ATA_AHCI_CT_OFFSET (ATA_AHCI_FB_OFFSET + 4096) 234 #define ATA_AHCI_CT_SIZE (1024 + 128) 235 236 struct ata_ahci_dma_prd { 237 u_int64_t dba; 238 u_int32_t reserved; 239 u_int32_t dbc; /* 0 based */ 240 #define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */ 241 #define ATA_AHCI_PRD_IPC (1<<31) 242 } __packed; 243 244 struct ata_ahci_cmd_tab { 245 u_int8_t cfis[64]; 246 u_int8_t acmd[32]; 247 u_int8_t reserved[32]; 248 #define ATA_AHCI_DMA_ENTRIES 64 249 struct ata_ahci_dma_prd prd_tab[ATA_AHCI_DMA_ENTRIES]; 250 } __packed; 251 252 struct ata_ahci_cmd_list { 253 u_int16_t cmd_flags; 254 #define ATA_AHCI_CMD_ATAPI 0x0020 255 #define ATA_AHCI_CMD_WRITE 0x0040 256 #define ATA_AHCI_CMD_PREFETCH 0x0080 257 #define ATA_AHCI_CMD_RESET 0x0100 258 #define ATA_AHCI_CMD_BIST 0x0200 259 #define ATA_AHCI_CMD_CLR_BUSY 0x0400 260 261 u_int16_t prd_length; /* PRD entries */ 262 u_int32_t bytecount; 263 u_int64_t cmd_table_phys; /* 128byte aligned */ 264 } __packed; 265 266 267 /* DMA register defines */ 268 #define ATA_DMA_ENTRIES 256 269 #define ATA_DMA_EOT 0x80000000 270 271 #define ATA_BMCMD_PORT 17 272 #define ATA_BMCMD_START_STOP 0x01 273 #define ATA_BMCMD_WRITE_READ 0x08 274 275 #define ATA_BMDEVSPEC_0 18 276 #define ATA_BMSTAT_PORT 19 277 #define ATA_BMSTAT_ACTIVE 0x01 278 #define ATA_BMSTAT_ERROR 0x02 279 #define ATA_BMSTAT_INTERRUPT 0x04 280 #define ATA_BMSTAT_MASK 0x07 281 #define ATA_BMSTAT_DMA_MASTER 0x20 282 #define ATA_BMSTAT_DMA_SLAVE 0x40 283 #define ATA_BMSTAT_DMA_SIMPLEX 0x80 284 285 #define ATA_BMDEVSPEC_1 20 286 #define ATA_BMDTP_PORT 21 287 288 #define ATA_IDX_ADDR 22 289 #define ATA_IDX_DATA 23 290 #define ATA_MAX_RES 24 291 292 /* misc defines */ 293 #define ATA_PRIMARY 0x1f0 294 #define ATA_SECONDARY 0x170 295 #define ATA_PC98_BANK 0x432 296 #define ATA_IOSIZE 0x08 297 #define ATA_PC98_IOSIZE 0x10 298 #define ATA_CTLIOSIZE 0x01 299 #define ATA_BMIOSIZE 0x08 300 #define ATA_PC98_BANKIOSIZE 0x01 301 #define ATA_IOADDR_RID 0 302 #define ATA_CTLADDR_RID 1 303 #define ATA_BMADDR_RID 0x20 304 #define ATA_PC98_CTLADDR_RID 8 305 #define ATA_PC98_BANKADDR_RID 9 306 #define ATA_IRQ_RID 0 307 #define ATA_DEV(unit) ((unit > 0) ? 0x10 : 0) 308 #define ATA_CFA_MAGIC1 0x844A 309 #define ATA_CFA_MAGIC2 0x848A 310 #define ATA_CFA_MAGIC3 0x8400 311 #define ATAPI_MAGIC_LSB 0x14 312 #define ATAPI_MAGIC_MSB 0xeb 313 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 314 #define ATAPI_P_WRITE (ATA_S_DRQ) 315 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 316 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 317 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 318 #define ATAPI_P_ABORT 0 319 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 320 #define ATA_OP_CONTINUES 0 321 #define ATA_OP_FINISHED 1 322 #define ATA_MAX_28BIT_LBA 268435455UL 323 324 /* structure used for composite atomic operations */ 325 #define MAX_COMPOSITES 32 /* u_int32_t bits */ 326 struct ata_composite { 327 struct mtx lock; /* control lock */ 328 u_int32_t rd_needed; /* needed read subdisks */ 329 u_int32_t rd_done; /* done read subdisks */ 330 u_int32_t wr_needed; /* needed write subdisks */ 331 u_int32_t wr_depend; /* write depends on subdisks */ 332 u_int32_t wr_done; /* done write subdisks */ 333 struct ata_request *request[MAX_COMPOSITES]; 334 u_int32_t residual; /* bytes still to transfer */ 335 caddr_t data_1; 336 caddr_t data_2; 337 }; 338 339 /* structure used to queue an ATA/ATAPI request */ 340 struct ata_request { 341 device_t dev; /* device handle */ 342 device_t parent; /* channel handle */ 343 union { 344 struct { 345 u_int8_t command; /* command reg */ 346 u_int16_t feature; /* feature reg */ 347 u_int16_t count; /* count reg */ 348 u_int64_t lba; /* lba reg */ 349 } ata; 350 struct { 351 u_int8_t ccb[16]; /* ATAPI command block */ 352 struct atapi_sense sense; /* ATAPI request sense data */ 353 u_int8_t saved_cmd; /* ATAPI saved command */ 354 } atapi; 355 } u; 356 u_int32_t bytecount; /* bytes to transfer */ 357 u_int32_t transfersize; /* bytes pr transfer */ 358 caddr_t data; /* pointer to data buf */ 359 u_int32_t tag; /* HW tag of this request */ 360 int flags; 361 #define ATA_R_CONTROL 0x00000001 362 #define ATA_R_READ 0x00000002 363 #define ATA_R_WRITE 0x00000004 364 #define ATA_R_ATAPI 0x00000008 365 #define ATA_R_DMA 0x00000010 366 #define ATA_R_QUIET 0x00000020 367 #define ATA_R_TIMEOUT 0x00000040 368 369 #define ATA_R_ORDERED 0x00000100 370 #define ATA_R_AT_HEAD 0x00000200 371 #define ATA_R_REQUEUE 0x00000400 372 #define ATA_R_THREAD 0x00000800 373 #define ATA_R_DIRECT 0x00001000 374 375 #define ATA_R_DEBUG 0x10000000 376 #define ATA_R_DANGER1 0x20000000 377 #define ATA_R_DANGER2 0x40000000 378 379 struct ata_dmaslot *dma; /* DMA slot of this request */ 380 u_int8_t status; /* ATA status */ 381 u_int8_t error; /* ATA error */ 382 u_int32_t donecount; /* bytes transferred */ 383 int result; /* result error code */ 384 void (*callback)(struct ata_request *request); 385 struct sema done; /* request done sema */ 386 int retries; /* retry count */ 387 int timeout; /* timeout for this cmd */ 388 struct callout callout; /* callout management */ 389 struct task task; /* task management */ 390 struct bio *bio; /* bio for this request */ 391 int this; /* this request ID */ 392 struct ata_composite *composite; /* for composite atomic ops */ 393 void *driver; /* driver specific */ 394 TAILQ_ENTRY(ata_request) chain; /* list management */ 395 }; 396 397 /* define this for debugging request processing */ 398 #if 0 399 #define ATA_DEBUG_RQ(request, string) \ 400 { \ 401 if (request->flags & ATA_R_DEBUG) \ 402 device_printf(request->dev, "req=%p %s " string "\n", \ 403 request, ata_cmd2str(request)); \ 404 } 405 #else 406 #define ATA_DEBUG_RQ(request, string) 407 #endif 408 409 410 /* structure describing an ATA/ATAPI device */ 411 struct ata_device { 412 device_t dev; /* device handle */ 413 int unit; /* physical unit */ 414 #define ATA_MASTER 0x00 415 #define ATA_SLAVE 0x01 416 #define ATA_PM 0x0f 417 418 struct ata_params param; /* ata param structure */ 419 int mode; /* current transfermode */ 420 u_int32_t max_iosize; /* max IO size */ 421 int spindown; /* idle spindown timeout */ 422 struct callout spindown_timer; 423 int spindown_state; 424 int flags; 425 #define ATA_D_USE_CHS 0x0001 426 #define ATA_D_MEDIA_CHANGED 0x0002 427 #define ATA_D_ENC_PRESENT 0x0004 428 #define ATA_D_48BIT_ACTIVE 0x0008 429 }; 430 431 /* structure for holding DMA Physical Region Descriptors (PRD) entries */ 432 struct ata_dma_prdentry { 433 u_int32_t addr; 434 u_int32_t count; 435 }; 436 437 /* structure used by the setprd function */ 438 struct ata_dmasetprd_args { 439 void *dmatab; 440 int nsegs; 441 int error; 442 }; 443 444 struct ata_dmaslot { 445 u_int8_t status; /* DMA status */ 446 bus_dma_tag_t sg_tag; /* SG list DMA tag */ 447 bus_dmamap_t sg_map; /* SG list DMA map */ 448 void *sg; /* DMA transfer table */ 449 bus_addr_t sg_bus; /* bus address of dmatab */ 450 bus_dma_tag_t data_tag; /* data DMA tag */ 451 bus_dmamap_t data_map; /* data DMA map */ 452 }; 453 454 /* structure holding DMA related information */ 455 struct ata_dma { 456 bus_dma_tag_t dmatag; /* parent DMA tag */ 457 bus_dma_tag_t work_tag; /* workspace DMA tag */ 458 bus_dmamap_t work_map; /* workspace DMA map */ 459 u_int8_t *work; /* workspace */ 460 bus_addr_t work_bus; /* bus address of dmatab */ 461 462 #define ATA_DMA_SLOTS 32 463 int dma_slots; /* DMA slots allocated */ 464 struct ata_dmaslot slot[ATA_DMA_SLOTS]; 465 u_int32_t alignment; /* DMA SG list alignment */ 466 u_int32_t boundary; /* DMA SG list boundary */ 467 u_int32_t segsize; /* DMA SG list segment size */ 468 u_int32_t max_iosize; /* DMA data max IO size */ 469 u_int64_t max_address; /* highest DMA'able address */ 470 int flags; 471 #define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress */ 472 473 void (*alloc)(device_t dev); 474 void (*free)(device_t dev); 475 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 476 int (*load)(struct ata_request *request, void *addr, int *nsegs); 477 int (*unload)(struct ata_request *request); 478 int (*start)(struct ata_request *request); 479 int (*stop)(struct ata_request *request); 480 void (*reset)(device_t dev); 481 }; 482 483 /* structure holding lowlevel functions */ 484 struct ata_lowlevel { 485 u_int32_t (*softreset)(device_t dev, int pmport); 486 int (*pm_read)(device_t dev, int port, int reg, u_int32_t *result); 487 int (*pm_write)(device_t dev, int port, int reg, u_int32_t value); 488 int (*status)(device_t dev); 489 int (*begin_transaction)(struct ata_request *request); 490 int (*end_transaction)(struct ata_request *request); 491 int (*command)(struct ata_request *request); 492 void (*tf_read)(struct ata_request *request); 493 void (*tf_write)(struct ata_request *request); 494 }; 495 496 /* structure holding resources for an ATA channel */ 497 struct ata_resource { 498 struct resource *res; 499 int offset; 500 }; 501 502 /* structure describing an ATA channel */ 503 struct ata_channel { 504 device_t dev; /* device handle */ 505 int unit; /* physical channel */ 506 int attached; /* channel is attached */ 507 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ 508 struct resource *r_irq; /* interrupt of this channel */ 509 void *ih; /* interrupt handle */ 510 struct ata_lowlevel hw; /* lowlevel HW functions */ 511 struct ata_dma dma; /* DMA data / functions */ 512 int flags; /* channel flags */ 513 #define ATA_NO_SLAVE 0x01 514 #define ATA_USE_16BIT 0x02 515 #define ATA_ATAPI_DMA_RO 0x04 516 #define ATA_NO_48BIT_DMA 0x08 517 #define ATA_ALWAYS_DMASTAT 0x10 518 519 int pm_level; /* power management level */ 520 int devices; /* what is present */ 521 #define ATA_ATA_MASTER 0x00000001 522 #define ATA_ATA_SLAVE 0x00000002 523 #define ATA_PORTMULTIPLIER 0x00008000 524 #define ATA_ATAPI_MASTER 0x00010000 525 #define ATA_ATAPI_SLAVE 0x00020000 526 527 struct mtx state_mtx; /* state lock */ 528 int state; /* ATA channel state */ 529 #define ATA_IDLE 0x0000 530 #define ATA_ACTIVE 0x0001 531 #define ATA_STALL_QUEUE 0x0002 532 533 struct mtx queue_mtx; /* queue lock */ 534 TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */ 535 struct ata_request *freezepoint; /* composite freezepoint */ 536 struct ata_request *running; /* currently running request */ 537 struct task conntask; /* PHY events handling task */ 538 }; 539 540 /* disk bay/enclosure related */ 541 #define ATA_LED_OFF 0x00 542 #define ATA_LED_RED 0x01 543 #define ATA_LED_GREEN 0x02 544 #define ATA_LED_ORANGE 0x03 545 #define ATA_LED_MASK 0x03 546 547 /* externs */ 548 extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data); 549 extern struct intr_config_hook *ata_delayed_attach; 550 extern devclass_t ata_devclass; 551 extern int ata_wc; 552 extern int ata_setmax; 553 extern int ata_dma_check_80pin; 554 555 /* public prototypes */ 556 /* ata-all.c: */ 557 int ata_probe(device_t dev); 558 int ata_attach(device_t dev); 559 int ata_detach(device_t dev); 560 int ata_reinit(device_t dev); 561 int ata_suspend(device_t dev); 562 int ata_resume(device_t dev); 563 void ata_interrupt(void *data); 564 int ata_device_ioctl(device_t dev, u_long cmd, caddr_t data); 565 int ata_getparam(struct ata_device *atadev, int init); 566 int ata_identify(device_t dev); 567 void ata_default_registers(device_t dev); 568 void ata_modify_if_48bit(struct ata_request *request); 569 void ata_udelay(int interval); 570 char *ata_unit2str(struct ata_device *atadev); 571 char *ata_mode2str(int mode); 572 int ata_atapi(device_t dev); 573 int ata_pmode(struct ata_params *ap); 574 int ata_wmode(struct ata_params *ap); 575 int ata_umode(struct ata_params *ap); 576 int ata_limit_mode(device_t dev, int mode, int maxmode); 577 578 /* ata-queue.c: */ 579 int ata_controlcmd(device_t dev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count); 580 int ata_atapicmd(device_t dev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout); 581 void ata_queue_request(struct ata_request *request); 582 void ata_start(device_t dev); 583 void ata_finish(struct ata_request *request); 584 void ata_timeout(struct ata_request *); 585 void ata_catch_inflight(device_t dev); 586 void ata_fail_requests(device_t dev); 587 void ata_drop_requests(device_t dev); 588 char *ata_cmd2str(struct ata_request *request); 589 590 /* ata-lowlevel.c: */ 591 void ata_generic_hw(device_t dev); 592 int ata_begin_transaction(struct ata_request *); 593 int ata_end_transaction(struct ata_request *); 594 void ata_generic_reset(device_t dev); 595 int ata_generic_command(struct ata_request *request); 596 597 /* macros for alloc/free of struct ata_request */ 598 extern uma_zone_t ata_request_zone; 599 #define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT | M_ZERO) 600 #define ata_free_request(request) { \ 601 if (!(request->flags & ATA_R_DANGER2)) \ 602 uma_zfree(ata_request_zone, request); \ 603 } 604 605 /* macros for alloc/free of struct ata_composite */ 606 extern uma_zone_t ata_composite_zone; 607 #define ata_alloc_composite() uma_zalloc(ata_composite_zone, M_NOWAIT | M_ZERO) 608 #define ata_free_composite(composite) uma_zfree(ata_composite_zone, composite) 609 610 MALLOC_DECLARE(M_ATA); 611 612 /* misc newbus defines */ 613 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 614 615 /* macros to hide busspace uglyness */ 616 #define ATA_INB(res, offset) \ 617 bus_read_1((res), (offset)) 618 619 #define ATA_INW(res, offset) \ 620 bus_read_2((res), (offset)) 621 #define ATA_INL(res, offset) \ 622 bus_read_4((res), (offset)) 623 #define ATA_INSW(res, offset, addr, count) \ 624 bus_read_multi_2((res), (offset), (addr), (count)) 625 #define ATA_INSW_STRM(res, offset, addr, count) \ 626 bus_read_multi_stream_2((res), (offset), (addr), (count)) 627 #define ATA_INSL(res, offset, addr, count) \ 628 bus_read_multi_4((res), (offset), (addr), (count)) 629 #define ATA_INSL_STRM(res, offset, addr, count) \ 630 bus_read_multi_stream_4((res), (offset), (addr), (count)) 631 #define ATA_OUTB(res, offset, value) \ 632 bus_write_1((res), (offset), (value)) 633 #define ATA_OUTW(res, offset, value) \ 634 bus_write_2((res), (offset), (value)) 635 #define ATA_OUTL(res, offset, value) \ 636 bus_write_4((res), (offset), (value)) 637 #define ATA_OUTSW(res, offset, addr, count) \ 638 bus_write_multi_2((res), (offset), (addr), (count)) 639 #define ATA_OUTSW_STRM(res, offset, addr, count) \ 640 bus_write_multi_stream_2((res), (offset), (addr), (count)) 641 #define ATA_OUTSL(res, offset, addr, count) \ 642 bus_write_multi_4((res), (offset), (addr), (count)) 643 #define ATA_OUTSL_STRM(res, offset, addr, count) \ 644 bus_write_multi_stream_4((res), (offset), (addr), (count)) 645 646 #define ATA_IDX_INB(ch, idx) \ 647 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) 648 649 #define ATA_IDX_INW(ch, idx) \ 650 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) 651 652 #define ATA_IDX_INL(ch, idx) \ 653 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) 654 655 #define ATA_IDX_INSW(ch, idx, addr, count) \ 656 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 657 658 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 659 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 660 661 #define ATA_IDX_INSL(ch, idx, addr, count) \ 662 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 663 664 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 665 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 666 667 #define ATA_IDX_OUTB(ch, idx, value) \ 668 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) 669 670 #define ATA_IDX_OUTW(ch, idx, value) \ 671 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) 672 673 #define ATA_IDX_OUTL(ch, idx, value) \ 674 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) 675 676 #define ATA_IDX_OUTSW(ch, idx, addr, count) \ 677 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 678 679 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 680 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 681 682 #define ATA_IDX_OUTSL(ch, idx, addr, count) \ 683 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 684 685 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 686 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 687