1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/ata.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/endian.h> 36 #include <sys/ctype.h> 37 #include <sys/conf.h> 38 #include <sys/bus.h> 39 #include <sys/bio.h> 40 #include <sys/malloc.h> 41 #include <sys/sysctl.h> 42 #include <sys/sema.h> 43 #include <sys/taskqueue.h> 44 #include <vm/uma.h> 45 #include <machine/stdarg.h> 46 #include <machine/resource.h> 47 #include <machine/bus.h> 48 #include <sys/rman.h> 49 #include <dev/ata/ata-all.h> 50 #include <dev/pci/pcivar.h> 51 #include <ata_if.h> 52 53 #include <cam/cam.h> 54 #include <cam/cam_ccb.h> 55 #include <cam/cam_sim.h> 56 #include <cam/cam_xpt_sim.h> 57 #include <cam/cam_debug.h> 58 59 /* prototypes */ 60 static void ataaction(struct cam_sim *sim, union ccb *ccb); 61 static void atapoll(struct cam_sim *sim); 62 static void ata_cam_begin_transaction(device_t dev, union ccb *ccb); 63 static void ata_cam_end_transaction(device_t dev, struct ata_request *request); 64 static void ata_cam_request_sense(device_t dev, struct ata_request *request); 65 static int ata_check_ids(device_t dev, union ccb *ccb); 66 static void ata_conn_event(void *context, int dummy); 67 static void ata_init(void); 68 static void ata_interrupt_locked(void *data); 69 static int ata_module_event_handler(module_t mod, int what, void *arg); 70 static void ata_periodic_poll(void *data); 71 static int ata_str2mode(const char *str); 72 static void ata_uninit(void); 73 74 /* global vars */ 75 MALLOC_DEFINE(M_ATA, "ata_generic", "ATA driver generic layer"); 76 int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data) = NULL; 77 devclass_t ata_devclass; 78 uma_zone_t ata_request_zone; 79 int ata_dma_check_80pin = 1; 80 81 /* sysctl vars */ 82 static SYSCTL_NODE(_hw, OID_AUTO, ata, CTLFLAG_RD, 0, "ATA driver parameters"); 83 SYSCTL_INT(_hw_ata, OID_AUTO, ata_dma_check_80pin, 84 CTLFLAG_RWTUN, &ata_dma_check_80pin, 0, 85 "Check for 80pin cable before setting ATA DMA mode"); 86 FEATURE(ata_cam, "ATA devices are accessed through the cam(4) driver"); 87 88 /* 89 * newbus device interface related functions 90 */ 91 int 92 ata_probe(device_t dev) 93 { 94 return (BUS_PROBE_DEFAULT); 95 } 96 97 int 98 ata_attach(device_t dev) 99 { 100 struct ata_channel *ch = device_get_softc(dev); 101 int error, rid; 102 struct cam_devq *devq; 103 const char *res; 104 char buf[64]; 105 int i, mode; 106 107 /* check that we have a virgin channel to attach */ 108 if (ch->r_irq) 109 return EEXIST; 110 111 /* initialize the softc basics */ 112 ch->dev = dev; 113 ch->state = ATA_IDLE; 114 bzero(&ch->state_mtx, sizeof(struct mtx)); 115 mtx_init(&ch->state_mtx, "ATA state lock", NULL, MTX_DEF); 116 TASK_INIT(&ch->conntask, 0, ata_conn_event, dev); 117 for (i = 0; i < 16; i++) { 118 ch->user[i].revision = 0; 119 snprintf(buf, sizeof(buf), "dev%d.sata_rev", i); 120 if (resource_int_value(device_get_name(dev), 121 device_get_unit(dev), buf, &mode) != 0 && 122 resource_int_value(device_get_name(dev), 123 device_get_unit(dev), "sata_rev", &mode) != 0) 124 mode = -1; 125 if (mode >= 0) 126 ch->user[i].revision = mode; 127 ch->user[i].mode = 0; 128 snprintf(buf, sizeof(buf), "dev%d.mode", i); 129 if (resource_string_value(device_get_name(dev), 130 device_get_unit(dev), buf, &res) == 0) 131 mode = ata_str2mode(res); 132 else if (resource_string_value(device_get_name(dev), 133 device_get_unit(dev), "mode", &res) == 0) 134 mode = ata_str2mode(res); 135 else 136 mode = -1; 137 if (mode >= 0) 138 ch->user[i].mode = mode; 139 if (ch->flags & ATA_SATA) 140 ch->user[i].bytecount = 8192; 141 else 142 ch->user[i].bytecount = MAXPHYS; 143 ch->user[i].caps = 0; 144 ch->curr[i] = ch->user[i]; 145 if (ch->flags & ATA_SATA) { 146 if (ch->pm_level > 0) 147 ch->user[i].caps |= CTS_SATA_CAPS_H_PMREQ; 148 if (ch->pm_level > 1) 149 ch->user[i].caps |= CTS_SATA_CAPS_D_PMREQ; 150 } else { 151 if (!(ch->flags & ATA_NO_48BIT_DMA)) 152 ch->user[i].caps |= CTS_ATA_CAPS_H_DMA48; 153 } 154 } 155 callout_init(&ch->poll_callout, 1); 156 157 /* allocate DMA resources if DMA HW present*/ 158 if (ch->dma.alloc) 159 ch->dma.alloc(dev); 160 161 /* setup interrupt delivery */ 162 rid = ATA_IRQ_RID; 163 ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 164 RF_SHAREABLE | RF_ACTIVE); 165 if (!ch->r_irq) { 166 device_printf(dev, "unable to allocate interrupt\n"); 167 return ENXIO; 168 } 169 if ((error = bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 170 ata_interrupt, ch, &ch->ih))) { 171 bus_release_resource(dev, SYS_RES_IRQ, rid, ch->r_irq); 172 device_printf(dev, "unable to setup interrupt\n"); 173 return error; 174 } 175 176 if (ch->flags & ATA_PERIODIC_POLL) 177 callout_reset(&ch->poll_callout, hz, ata_periodic_poll, ch); 178 mtx_lock(&ch->state_mtx); 179 /* Create the device queue for our SIM. */ 180 devq = cam_simq_alloc(1); 181 if (devq == NULL) { 182 device_printf(dev, "Unable to allocate simq\n"); 183 error = ENOMEM; 184 goto err1; 185 } 186 /* Construct SIM entry */ 187 ch->sim = cam_sim_alloc(ataaction, atapoll, "ata", ch, 188 device_get_unit(dev), &ch->state_mtx, 1, 0, devq); 189 if (ch->sim == NULL) { 190 device_printf(dev, "unable to allocate sim\n"); 191 cam_simq_free(devq); 192 error = ENOMEM; 193 goto err1; 194 } 195 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 196 device_printf(dev, "unable to register xpt bus\n"); 197 error = ENXIO; 198 goto err2; 199 } 200 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 201 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 202 device_printf(dev, "unable to create path\n"); 203 error = ENXIO; 204 goto err3; 205 } 206 mtx_unlock(&ch->state_mtx); 207 return (0); 208 209 err3: 210 xpt_bus_deregister(cam_sim_path(ch->sim)); 211 err2: 212 cam_sim_free(ch->sim, /*free_devq*/TRUE); 213 ch->sim = NULL; 214 err1: 215 bus_release_resource(dev, SYS_RES_IRQ, rid, ch->r_irq); 216 mtx_unlock(&ch->state_mtx); 217 if (ch->flags & ATA_PERIODIC_POLL) 218 callout_drain(&ch->poll_callout); 219 return (error); 220 } 221 222 int 223 ata_detach(device_t dev) 224 { 225 struct ata_channel *ch = device_get_softc(dev); 226 227 /* check that we have a valid channel to detach */ 228 if (!ch->r_irq) 229 return ENXIO; 230 231 /* grap the channel lock so no new requests gets launched */ 232 mtx_lock(&ch->state_mtx); 233 ch->state |= ATA_STALL_QUEUE; 234 mtx_unlock(&ch->state_mtx); 235 if (ch->flags & ATA_PERIODIC_POLL) 236 callout_drain(&ch->poll_callout); 237 238 taskqueue_drain(taskqueue_thread, &ch->conntask); 239 240 mtx_lock(&ch->state_mtx); 241 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 242 xpt_free_path(ch->path); 243 xpt_bus_deregister(cam_sim_path(ch->sim)); 244 cam_sim_free(ch->sim, /*free_devq*/TRUE); 245 ch->sim = NULL; 246 mtx_unlock(&ch->state_mtx); 247 248 /* release resources */ 249 bus_teardown_intr(dev, ch->r_irq, ch->ih); 250 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 251 ch->r_irq = NULL; 252 253 /* free DMA resources if DMA HW present*/ 254 if (ch->dma.free) 255 ch->dma.free(dev); 256 257 mtx_destroy(&ch->state_mtx); 258 return 0; 259 } 260 261 static void 262 ata_conn_event(void *context, int dummy) 263 { 264 device_t dev = (device_t)context; 265 struct ata_channel *ch = device_get_softc(dev); 266 union ccb *ccb; 267 268 mtx_lock(&ch->state_mtx); 269 if (ch->sim == NULL) { 270 mtx_unlock(&ch->state_mtx); 271 return; 272 } 273 ata_reinit(dev); 274 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 275 return; 276 if (xpt_create_path(&ccb->ccb_h.path, NULL, 277 cam_sim_path(ch->sim), 278 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 279 xpt_free_ccb(ccb); 280 return; 281 } 282 xpt_rescan(ccb); 283 mtx_unlock(&ch->state_mtx); 284 } 285 286 int 287 ata_reinit(device_t dev) 288 { 289 struct ata_channel *ch = device_get_softc(dev); 290 struct ata_request *request; 291 292 xpt_freeze_simq(ch->sim, 1); 293 if ((request = ch->running)) { 294 ch->running = NULL; 295 if (ch->state == ATA_ACTIVE) 296 ch->state = ATA_IDLE; 297 callout_stop(&request->callout); 298 if (ch->dma.unload) 299 ch->dma.unload(request); 300 request->result = ERESTART; 301 ata_cam_end_transaction(dev, request); 302 } 303 /* reset the controller HW, the channel and device(s) */ 304 ATA_RESET(dev); 305 /* Tell the XPT about the event */ 306 xpt_async(AC_BUS_RESET, ch->path, NULL); 307 xpt_release_simq(ch->sim, TRUE); 308 return(0); 309 } 310 311 int 312 ata_suspend(device_t dev) 313 { 314 struct ata_channel *ch; 315 316 /* check for valid device */ 317 if (!dev || !(ch = device_get_softc(dev))) 318 return ENXIO; 319 320 if (ch->flags & ATA_PERIODIC_POLL) 321 callout_drain(&ch->poll_callout); 322 mtx_lock(&ch->state_mtx); 323 xpt_freeze_simq(ch->sim, 1); 324 while (ch->state != ATA_IDLE) 325 msleep(ch, &ch->state_mtx, PRIBIO, "atasusp", hz/100); 326 mtx_unlock(&ch->state_mtx); 327 return(0); 328 } 329 330 int 331 ata_resume(device_t dev) 332 { 333 struct ata_channel *ch; 334 int error; 335 336 /* check for valid device */ 337 if (!dev || !(ch = device_get_softc(dev))) 338 return ENXIO; 339 340 mtx_lock(&ch->state_mtx); 341 error = ata_reinit(dev); 342 xpt_release_simq(ch->sim, TRUE); 343 mtx_unlock(&ch->state_mtx); 344 if (ch->flags & ATA_PERIODIC_POLL) 345 callout_reset(&ch->poll_callout, hz, ata_periodic_poll, ch); 346 return error; 347 } 348 349 void 350 ata_interrupt(void *data) 351 { 352 struct ata_channel *ch = (struct ata_channel *)data; 353 354 mtx_lock(&ch->state_mtx); 355 ata_interrupt_locked(data); 356 mtx_unlock(&ch->state_mtx); 357 } 358 359 static void 360 ata_interrupt_locked(void *data) 361 { 362 struct ata_channel *ch = (struct ata_channel *)data; 363 struct ata_request *request; 364 365 /* ignore interrupt if its not for us */ 366 if (ch->hw.status && !ch->hw.status(ch->dev)) 367 return; 368 369 /* do we have a running request */ 370 if (!(request = ch->running)) 371 return; 372 373 ATA_DEBUG_RQ(request, "interrupt"); 374 375 /* safetycheck for the right state */ 376 if (ch->state == ATA_IDLE) { 377 device_printf(request->dev, "interrupt on idle channel ignored\n"); 378 return; 379 } 380 381 /* 382 * we have the HW locks, so end the transaction for this request 383 * if it finishes immediately otherwise wait for next interrupt 384 */ 385 if (ch->hw.end_transaction(request) == ATA_OP_FINISHED) { 386 ch->running = NULL; 387 if (ch->state == ATA_ACTIVE) 388 ch->state = ATA_IDLE; 389 ata_cam_end_transaction(ch->dev, request); 390 return; 391 } 392 } 393 394 static void 395 ata_periodic_poll(void *data) 396 { 397 struct ata_channel *ch = (struct ata_channel *)data; 398 399 callout_reset(&ch->poll_callout, hz, ata_periodic_poll, ch); 400 ata_interrupt(ch); 401 } 402 403 void 404 ata_print_cable(device_t dev, u_int8_t *who) 405 { 406 device_printf(dev, 407 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who); 408 } 409 410 /* 411 * misc support functions 412 */ 413 void 414 ata_default_registers(device_t dev) 415 { 416 struct ata_channel *ch = device_get_softc(dev); 417 418 /* fill in the defaults from whats setup already */ 419 ch->r_io[ATA_ERROR].res = ch->r_io[ATA_FEATURE].res; 420 ch->r_io[ATA_ERROR].offset = ch->r_io[ATA_FEATURE].offset; 421 ch->r_io[ATA_IREASON].res = ch->r_io[ATA_COUNT].res; 422 ch->r_io[ATA_IREASON].offset = ch->r_io[ATA_COUNT].offset; 423 ch->r_io[ATA_STATUS].res = ch->r_io[ATA_COMMAND].res; 424 ch->r_io[ATA_STATUS].offset = ch->r_io[ATA_COMMAND].offset; 425 ch->r_io[ATA_ALTSTAT].res = ch->r_io[ATA_CONTROL].res; 426 ch->r_io[ATA_ALTSTAT].offset = ch->r_io[ATA_CONTROL].offset; 427 } 428 429 void 430 ata_udelay(int interval) 431 { 432 /* for now just use DELAY, the timer/sleep subsytems are not there yet */ 433 if (1 || interval < (1000000/hz) || ata_delayed_attach) 434 DELAY(interval); 435 else 436 pause("ataslp", interval/(1000000/hz)); 437 } 438 439 const char * 440 ata_cmd2str(struct ata_request *request) 441 { 442 static char buffer[20]; 443 444 if (request->flags & ATA_R_ATAPI) { 445 switch (request->u.atapi.sense.key ? 446 request->u.atapi.saved_cmd : request->u.atapi.ccb[0]) { 447 case 0x00: return ("TEST_UNIT_READY"); 448 case 0x01: return ("REZERO"); 449 case 0x03: return ("REQUEST_SENSE"); 450 case 0x04: return ("FORMAT"); 451 case 0x08: return ("READ"); 452 case 0x0a: return ("WRITE"); 453 case 0x10: return ("WEOF"); 454 case 0x11: return ("SPACE"); 455 case 0x12: return ("INQUIRY"); 456 case 0x15: return ("MODE_SELECT"); 457 case 0x19: return ("ERASE"); 458 case 0x1a: return ("MODE_SENSE"); 459 case 0x1b: return ("START_STOP"); 460 case 0x1e: return ("PREVENT_ALLOW"); 461 case 0x23: return ("ATAPI_READ_FORMAT_CAPACITIES"); 462 case 0x25: return ("READ_CAPACITY"); 463 case 0x28: return ("READ_BIG"); 464 case 0x2a: return ("WRITE_BIG"); 465 case 0x2b: return ("LOCATE"); 466 case 0x34: return ("READ_POSITION"); 467 case 0x35: return ("SYNCHRONIZE_CACHE"); 468 case 0x3b: return ("WRITE_BUFFER"); 469 case 0x3c: return ("READ_BUFFER"); 470 case 0x42: return ("READ_SUBCHANNEL"); 471 case 0x43: return ("READ_TOC"); 472 case 0x45: return ("PLAY_10"); 473 case 0x47: return ("PLAY_MSF"); 474 case 0x48: return ("PLAY_TRACK"); 475 case 0x4b: return ("PAUSE"); 476 case 0x51: return ("READ_DISK_INFO"); 477 case 0x52: return ("READ_TRACK_INFO"); 478 case 0x53: return ("RESERVE_TRACK"); 479 case 0x54: return ("SEND_OPC_INFO"); 480 case 0x55: return ("MODE_SELECT_BIG"); 481 case 0x58: return ("REPAIR_TRACK"); 482 case 0x59: return ("READ_MASTER_CUE"); 483 case 0x5a: return ("MODE_SENSE_BIG"); 484 case 0x5b: return ("CLOSE_TRACK/SESSION"); 485 case 0x5c: return ("READ_BUFFER_CAPACITY"); 486 case 0x5d: return ("SEND_CUE_SHEET"); 487 case 0x96: return ("SERVICE_ACTION_IN"); 488 case 0xa1: return ("BLANK_CMD"); 489 case 0xa3: return ("SEND_KEY"); 490 case 0xa4: return ("REPORT_KEY"); 491 case 0xa5: return ("PLAY_12"); 492 case 0xa6: return ("LOAD_UNLOAD"); 493 case 0xad: return ("READ_DVD_STRUCTURE"); 494 case 0xb4: return ("PLAY_CD"); 495 case 0xbb: return ("SET_SPEED"); 496 case 0xbd: return ("MECH_STATUS"); 497 case 0xbe: return ("READ_CD"); 498 case 0xff: return ("POLL_DSC"); 499 } 500 } else { 501 switch (request->u.ata.command) { 502 case 0x00: return ("NOP"); 503 case 0x08: return ("DEVICE_RESET"); 504 case 0x20: return ("READ"); 505 case 0x24: return ("READ48"); 506 case 0x25: return ("READ_DMA48"); 507 case 0x26: return ("READ_DMA_QUEUED48"); 508 case 0x27: return ("READ_NATIVE_MAX_ADDRESS48"); 509 case 0x29: return ("READ_MUL48"); 510 case 0x30: return ("WRITE"); 511 case 0x34: return ("WRITE48"); 512 case 0x35: return ("WRITE_DMA48"); 513 case 0x36: return ("WRITE_DMA_QUEUED48"); 514 case 0x37: return ("SET_MAX_ADDRESS48"); 515 case 0x39: return ("WRITE_MUL48"); 516 case 0x70: return ("SEEK"); 517 case 0xa0: return ("PACKET_CMD"); 518 case 0xa1: return ("ATAPI_IDENTIFY"); 519 case 0xa2: return ("SERVICE"); 520 case 0xb0: return ("SMART"); 521 case 0xc0: return ("CFA ERASE"); 522 case 0xc4: return ("READ_MUL"); 523 case 0xc5: return ("WRITE_MUL"); 524 case 0xc6: return ("SET_MULTI"); 525 case 0xc7: return ("READ_DMA_QUEUED"); 526 case 0xc8: return ("READ_DMA"); 527 case 0xca: return ("WRITE_DMA"); 528 case 0xcc: return ("WRITE_DMA_QUEUED"); 529 case 0xe6: return ("SLEEP"); 530 case 0xe7: return ("FLUSHCACHE"); 531 case 0xea: return ("FLUSHCACHE48"); 532 case 0xec: return ("ATA_IDENTIFY"); 533 case 0xef: 534 switch (request->u.ata.feature) { 535 case 0x03: return ("SETFEATURES SET TRANSFER MODE"); 536 case 0x02: return ("SETFEATURES ENABLE WCACHE"); 537 case 0x82: return ("SETFEATURES DISABLE WCACHE"); 538 case 0xaa: return ("SETFEATURES ENABLE RCACHE"); 539 case 0x55: return ("SETFEATURES DISABLE RCACHE"); 540 } 541 sprintf(buffer, "SETFEATURES 0x%02x", 542 request->u.ata.feature); 543 return (buffer); 544 case 0xf5: return ("SECURITY_FREE_LOCK"); 545 case 0xf8: return ("READ_NATIVE_MAX_ADDRESS"); 546 case 0xf9: return ("SET_MAX_ADDRESS"); 547 } 548 } 549 sprintf(buffer, "unknown CMD (0x%02x)", request->u.ata.command); 550 return (buffer); 551 } 552 553 const char * 554 ata_mode2str(int mode) 555 { 556 switch (mode) { 557 case -1: return "UNSUPPORTED"; 558 case ATA_PIO0: return "PIO0"; 559 case ATA_PIO1: return "PIO1"; 560 case ATA_PIO2: return "PIO2"; 561 case ATA_PIO3: return "PIO3"; 562 case ATA_PIO4: return "PIO4"; 563 case ATA_WDMA0: return "WDMA0"; 564 case ATA_WDMA1: return "WDMA1"; 565 case ATA_WDMA2: return "WDMA2"; 566 case ATA_UDMA0: return "UDMA16"; 567 case ATA_UDMA1: return "UDMA25"; 568 case ATA_UDMA2: return "UDMA33"; 569 case ATA_UDMA3: return "UDMA40"; 570 case ATA_UDMA4: return "UDMA66"; 571 case ATA_UDMA5: return "UDMA100"; 572 case ATA_UDMA6: return "UDMA133"; 573 case ATA_SA150: return "SATA150"; 574 case ATA_SA300: return "SATA300"; 575 default: 576 if (mode & ATA_DMA_MASK) 577 return "BIOSDMA"; 578 else 579 return "BIOSPIO"; 580 } 581 } 582 583 static int 584 ata_str2mode(const char *str) 585 { 586 587 if (!strcasecmp(str, "PIO0")) return (ATA_PIO0); 588 if (!strcasecmp(str, "PIO1")) return (ATA_PIO1); 589 if (!strcasecmp(str, "PIO2")) return (ATA_PIO2); 590 if (!strcasecmp(str, "PIO3")) return (ATA_PIO3); 591 if (!strcasecmp(str, "PIO4")) return (ATA_PIO4); 592 if (!strcasecmp(str, "WDMA0")) return (ATA_WDMA0); 593 if (!strcasecmp(str, "WDMA1")) return (ATA_WDMA1); 594 if (!strcasecmp(str, "WDMA2")) return (ATA_WDMA2); 595 if (!strcasecmp(str, "UDMA0")) return (ATA_UDMA0); 596 if (!strcasecmp(str, "UDMA16")) return (ATA_UDMA0); 597 if (!strcasecmp(str, "UDMA1")) return (ATA_UDMA1); 598 if (!strcasecmp(str, "UDMA25")) return (ATA_UDMA1); 599 if (!strcasecmp(str, "UDMA2")) return (ATA_UDMA2); 600 if (!strcasecmp(str, "UDMA33")) return (ATA_UDMA2); 601 if (!strcasecmp(str, "UDMA3")) return (ATA_UDMA3); 602 if (!strcasecmp(str, "UDMA44")) return (ATA_UDMA3); 603 if (!strcasecmp(str, "UDMA4")) return (ATA_UDMA4); 604 if (!strcasecmp(str, "UDMA66")) return (ATA_UDMA4); 605 if (!strcasecmp(str, "UDMA5")) return (ATA_UDMA5); 606 if (!strcasecmp(str, "UDMA100")) return (ATA_UDMA5); 607 if (!strcasecmp(str, "UDMA6")) return (ATA_UDMA6); 608 if (!strcasecmp(str, "UDMA133")) return (ATA_UDMA6); 609 return (-1); 610 } 611 612 int 613 ata_atapi(device_t dev, int target) 614 { 615 struct ata_channel *ch = device_get_softc(dev); 616 617 return (ch->devices & (ATA_ATAPI_MASTER << target)); 618 } 619 620 void 621 ata_timeout(struct ata_request *request) 622 { 623 struct ata_channel *ch; 624 625 ch = device_get_softc(request->parent); 626 //request->flags |= ATA_R_DEBUG; 627 ATA_DEBUG_RQ(request, "timeout"); 628 629 /* 630 * If we have an ATA_ACTIVE request running, we flag the request 631 * ATA_R_TIMEOUT so ata_cam_end_transaction() will handle it correctly. 632 * Also, NULL out the running request so we wont loose the race with 633 * an eventual interrupt arriving late. 634 */ 635 if (ch->state == ATA_ACTIVE) { 636 request->flags |= ATA_R_TIMEOUT; 637 if (ch->dma.unload) 638 ch->dma.unload(request); 639 ch->running = NULL; 640 ch->state = ATA_IDLE; 641 ata_cam_end_transaction(ch->dev, request); 642 } 643 mtx_unlock(&ch->state_mtx); 644 } 645 646 static void 647 ata_cam_begin_transaction(device_t dev, union ccb *ccb) 648 { 649 struct ata_channel *ch = device_get_softc(dev); 650 struct ata_request *request; 651 652 if (!(request = ata_alloc_request())) { 653 device_printf(dev, "FAILURE - out of memory in start\n"); 654 ccb->ccb_h.status = CAM_REQ_INVALID; 655 xpt_done(ccb); 656 return; 657 } 658 bzero(request, sizeof(*request)); 659 660 /* setup request */ 661 request->dev = NULL; 662 request->parent = dev; 663 request->unit = ccb->ccb_h.target_id; 664 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 665 request->data = ccb->ataio.data_ptr; 666 request->bytecount = ccb->ataio.dxfer_len; 667 request->u.ata.command = ccb->ataio.cmd.command; 668 request->u.ata.feature = ((uint16_t)ccb->ataio.cmd.features_exp << 8) | 669 (uint16_t)ccb->ataio.cmd.features; 670 request->u.ata.count = ((uint16_t)ccb->ataio.cmd.sector_count_exp << 8) | 671 (uint16_t)ccb->ataio.cmd.sector_count; 672 if (ccb->ataio.cmd.flags & CAM_ATAIO_48BIT) { 673 request->flags |= ATA_R_48BIT; 674 request->u.ata.lba = 675 ((uint64_t)ccb->ataio.cmd.lba_high_exp << 40) | 676 ((uint64_t)ccb->ataio.cmd.lba_mid_exp << 32) | 677 ((uint64_t)ccb->ataio.cmd.lba_low_exp << 24); 678 } else { 679 request->u.ata.lba = 680 ((uint64_t)(ccb->ataio.cmd.device & 0x0f) << 24); 681 } 682 request->u.ata.lba |= ((uint64_t)ccb->ataio.cmd.lba_high << 16) | 683 ((uint64_t)ccb->ataio.cmd.lba_mid << 8) | 684 (uint64_t)ccb->ataio.cmd.lba_low; 685 if (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT) 686 request->flags |= ATA_R_NEEDRESULT; 687 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 688 ccb->ataio.cmd.flags & CAM_ATAIO_DMA) 689 request->flags |= ATA_R_DMA; 690 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 691 request->flags |= ATA_R_READ; 692 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) 693 request->flags |= ATA_R_WRITE; 694 if (ccb->ataio.cmd.command == ATA_READ_MUL || 695 ccb->ataio.cmd.command == ATA_READ_MUL48 || 696 ccb->ataio.cmd.command == ATA_WRITE_MUL || 697 ccb->ataio.cmd.command == ATA_WRITE_MUL48) { 698 request->transfersize = min(request->bytecount, 699 ch->curr[ccb->ccb_h.target_id].bytecount); 700 } else 701 request->transfersize = min(request->bytecount, 512); 702 } else { 703 request->data = ccb->csio.data_ptr; 704 request->bytecount = ccb->csio.dxfer_len; 705 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 706 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 707 request->u.atapi.ccb, ccb->csio.cdb_len); 708 request->flags |= ATA_R_ATAPI; 709 if (ch->curr[ccb->ccb_h.target_id].atapi == 16) 710 request->flags |= ATA_R_ATAPI16; 711 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 712 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 713 request->flags |= ATA_R_DMA; 714 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 715 request->flags |= ATA_R_READ; 716 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) 717 request->flags |= ATA_R_WRITE; 718 request->transfersize = min(request->bytecount, 719 ch->curr[ccb->ccb_h.target_id].bytecount); 720 } 721 request->retries = 0; 722 request->timeout = (ccb->ccb_h.timeout + 999) / 1000; 723 callout_init_mtx(&request->callout, &ch->state_mtx, CALLOUT_RETURNUNLOCKED); 724 request->ccb = ccb; 725 request->flags |= ATA_R_DATA_IN_CCB; 726 727 ch->running = request; 728 ch->state = ATA_ACTIVE; 729 if (ch->hw.begin_transaction(request) == ATA_OP_FINISHED) { 730 ch->running = NULL; 731 ch->state = ATA_IDLE; 732 ata_cam_end_transaction(dev, request); 733 return; 734 } 735 } 736 737 static void 738 ata_cam_request_sense(device_t dev, struct ata_request *request) 739 { 740 struct ata_channel *ch = device_get_softc(dev); 741 union ccb *ccb = request->ccb; 742 743 ch->requestsense = 1; 744 745 bzero(request, sizeof(*request)); 746 request->dev = NULL; 747 request->parent = dev; 748 request->unit = ccb->ccb_h.target_id; 749 request->data = (void *)&ccb->csio.sense_data; 750 request->bytecount = ccb->csio.sense_len; 751 request->u.atapi.ccb[0] = ATAPI_REQUEST_SENSE; 752 request->u.atapi.ccb[4] = ccb->csio.sense_len; 753 request->flags |= ATA_R_ATAPI; 754 if (ch->curr[ccb->ccb_h.target_id].atapi == 16) 755 request->flags |= ATA_R_ATAPI16; 756 if (ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 757 request->flags |= ATA_R_DMA; 758 request->flags |= ATA_R_READ; 759 request->transfersize = min(request->bytecount, 760 ch->curr[ccb->ccb_h.target_id].bytecount); 761 request->retries = 0; 762 request->timeout = (ccb->ccb_h.timeout + 999) / 1000; 763 callout_init_mtx(&request->callout, &ch->state_mtx, CALLOUT_RETURNUNLOCKED); 764 request->ccb = ccb; 765 766 ch->running = request; 767 ch->state = ATA_ACTIVE; 768 if (ch->hw.begin_transaction(request) == ATA_OP_FINISHED) { 769 ch->running = NULL; 770 ch->state = ATA_IDLE; 771 ata_cam_end_transaction(dev, request); 772 return; 773 } 774 } 775 776 static void 777 ata_cam_process_sense(device_t dev, struct ata_request *request) 778 { 779 struct ata_channel *ch = device_get_softc(dev); 780 union ccb *ccb = request->ccb; 781 int fatalerr = 0; 782 783 ch->requestsense = 0; 784 785 if (request->flags & ATA_R_TIMEOUT) 786 fatalerr = 1; 787 if ((request->flags & ATA_R_TIMEOUT) == 0 && 788 (request->status & ATA_S_ERROR) == 0 && 789 request->result == 0) { 790 ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 791 } else { 792 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 793 ccb->ccb_h.status |= CAM_AUTOSENSE_FAIL; 794 } 795 796 ata_free_request(request); 797 xpt_done(ccb); 798 /* Do error recovery if needed. */ 799 if (fatalerr) 800 ata_reinit(dev); 801 } 802 803 static void 804 ata_cam_end_transaction(device_t dev, struct ata_request *request) 805 { 806 struct ata_channel *ch = device_get_softc(dev); 807 union ccb *ccb = request->ccb; 808 int fatalerr = 0; 809 810 if (ch->requestsense) { 811 ata_cam_process_sense(dev, request); 812 return; 813 } 814 815 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 816 if (request->flags & ATA_R_TIMEOUT) { 817 xpt_freeze_simq(ch->sim, 1); 818 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 819 ccb->ccb_h.status |= CAM_CMD_TIMEOUT | CAM_RELEASE_SIMQ; 820 fatalerr = 1; 821 } else if (request->status & ATA_S_ERROR) { 822 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 823 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 824 } else { 825 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 826 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 827 } 828 } else if (request->result == ERESTART) 829 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 830 else if (request->result != 0) 831 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 832 else 833 ccb->ccb_h.status |= CAM_REQ_CMP; 834 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP && 835 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 836 xpt_freeze_devq(ccb->ccb_h.path, 1); 837 ccb->ccb_h.status |= CAM_DEV_QFRZN; 838 } 839 if (ccb->ccb_h.func_code == XPT_ATA_IO && 840 ((request->status & ATA_S_ERROR) || 841 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT))) { 842 struct ata_res *res = &ccb->ataio.res; 843 res->status = request->status; 844 res->error = request->error; 845 res->lba_low = request->u.ata.lba; 846 res->lba_mid = request->u.ata.lba >> 8; 847 res->lba_high = request->u.ata.lba >> 16; 848 res->device = request->u.ata.lba >> 24; 849 res->lba_low_exp = request->u.ata.lba >> 24; 850 res->lba_mid_exp = request->u.ata.lba >> 32; 851 res->lba_high_exp = request->u.ata.lba >> 40; 852 res->sector_count = request->u.ata.count; 853 res->sector_count_exp = request->u.ata.count >> 8; 854 } 855 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 856 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 857 ccb->ataio.resid = 858 ccb->ataio.dxfer_len - request->donecount; 859 } else { 860 ccb->csio.resid = 861 ccb->csio.dxfer_len - request->donecount; 862 } 863 } 864 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 865 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) 866 ata_cam_request_sense(dev, request); 867 else { 868 ata_free_request(request); 869 xpt_done(ccb); 870 } 871 /* Do error recovery if needed. */ 872 if (fatalerr) 873 ata_reinit(dev); 874 } 875 876 static int 877 ata_check_ids(device_t dev, union ccb *ccb) 878 { 879 struct ata_channel *ch = device_get_softc(dev); 880 881 if (ccb->ccb_h.target_id > ((ch->flags & ATA_NO_SLAVE) ? 0 : 1)) { 882 ccb->ccb_h.status = CAM_TID_INVALID; 883 xpt_done(ccb); 884 return (-1); 885 } 886 if (ccb->ccb_h.target_lun != 0) { 887 ccb->ccb_h.status = CAM_LUN_INVALID; 888 xpt_done(ccb); 889 return (-1); 890 } 891 return (0); 892 } 893 894 static void 895 ataaction(struct cam_sim *sim, union ccb *ccb) 896 { 897 device_t dev, parent; 898 struct ata_channel *ch; 899 900 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ataaction func_code=%x\n", 901 ccb->ccb_h.func_code)); 902 903 ch = (struct ata_channel *)cam_sim_softc(sim); 904 dev = ch->dev; 905 switch (ccb->ccb_h.func_code) { 906 /* Common cases first */ 907 case XPT_ATA_IO: /* Execute the requested I/O operation */ 908 case XPT_SCSI_IO: 909 if (ata_check_ids(dev, ccb)) 910 return; 911 if ((ch->devices & ((ATA_ATA_MASTER | ATA_ATAPI_MASTER) 912 << ccb->ccb_h.target_id)) == 0) { 913 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 914 break; 915 } 916 if (ch->running) 917 device_printf(dev, "already running!\n"); 918 if (ccb->ccb_h.func_code == XPT_ATA_IO && 919 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 920 (ccb->ataio.cmd.control & ATA_A_RESET)) { 921 struct ata_res *res = &ccb->ataio.res; 922 923 bzero(res, sizeof(*res)); 924 if (ch->devices & (ATA_ATA_MASTER << ccb->ccb_h.target_id)) { 925 res->lba_high = 0; 926 res->lba_mid = 0; 927 } else { 928 res->lba_high = 0xeb; 929 res->lba_mid = 0x14; 930 } 931 ccb->ccb_h.status = CAM_REQ_CMP; 932 break; 933 } 934 ata_cam_begin_transaction(dev, ccb); 935 return; 936 case XPT_EN_LUN: /* Enable LUN as a target */ 937 case XPT_TARGET_IO: /* Execute target I/O request */ 938 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 939 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 940 case XPT_ABORT: /* Abort the specified CCB */ 941 /* XXX Implement */ 942 ccb->ccb_h.status = CAM_REQ_INVALID; 943 break; 944 case XPT_SET_TRAN_SETTINGS: 945 { 946 struct ccb_trans_settings *cts = &ccb->cts; 947 struct ata_cam_device *d; 948 949 if (ata_check_ids(dev, ccb)) 950 return; 951 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 952 d = &ch->curr[ccb->ccb_h.target_id]; 953 else 954 d = &ch->user[ccb->ccb_h.target_id]; 955 if (ch->flags & ATA_SATA) { 956 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 957 d->revision = cts->xport_specific.sata.revision; 958 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) { 959 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 960 d->mode = ATA_SETMODE(ch->dev, 961 ccb->ccb_h.target_id, 962 cts->xport_specific.sata.mode); 963 } else 964 d->mode = cts->xport_specific.sata.mode; 965 } 966 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 967 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 968 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 969 d->atapi = cts->xport_specific.sata.atapi; 970 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 971 d->caps = cts->xport_specific.sata.caps; 972 } else { 973 if (cts->xport_specific.ata.valid & CTS_ATA_VALID_MODE) { 974 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 975 d->mode = ATA_SETMODE(ch->dev, 976 ccb->ccb_h.target_id, 977 cts->xport_specific.ata.mode); 978 } else 979 d->mode = cts->xport_specific.ata.mode; 980 } 981 if (cts->xport_specific.ata.valid & CTS_ATA_VALID_BYTECOUNT) 982 d->bytecount = cts->xport_specific.ata.bytecount; 983 if (cts->xport_specific.ata.valid & CTS_ATA_VALID_ATAPI) 984 d->atapi = cts->xport_specific.ata.atapi; 985 if (cts->xport_specific.ata.valid & CTS_ATA_VALID_CAPS) 986 d->caps = cts->xport_specific.ata.caps; 987 } 988 ccb->ccb_h.status = CAM_REQ_CMP; 989 break; 990 } 991 case XPT_GET_TRAN_SETTINGS: 992 { 993 struct ccb_trans_settings *cts = &ccb->cts; 994 struct ata_cam_device *d; 995 996 if (ata_check_ids(dev, ccb)) 997 return; 998 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 999 d = &ch->curr[ccb->ccb_h.target_id]; 1000 else 1001 d = &ch->user[ccb->ccb_h.target_id]; 1002 cts->protocol = PROTO_UNSPECIFIED; 1003 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 1004 if (ch->flags & ATA_SATA) { 1005 cts->transport = XPORT_SATA; 1006 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 1007 cts->xport_specific.sata.valid = 0; 1008 cts->xport_specific.sata.mode = d->mode; 1009 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 1010 cts->xport_specific.sata.bytecount = d->bytecount; 1011 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 1012 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 1013 cts->xport_specific.sata.revision = 1014 ATA_GETREV(dev, ccb->ccb_h.target_id); 1015 if (cts->xport_specific.sata.revision != 0xff) { 1016 cts->xport_specific.sata.valid |= 1017 CTS_SATA_VALID_REVISION; 1018 } 1019 cts->xport_specific.sata.caps = 1020 d->caps & CTS_SATA_CAPS_D; 1021 if (ch->pm_level) { 1022 cts->xport_specific.sata.caps |= 1023 CTS_SATA_CAPS_H_PMREQ; 1024 } 1025 cts->xport_specific.sata.caps &= 1026 ch->user[ccb->ccb_h.target_id].caps; 1027 } else { 1028 cts->xport_specific.sata.revision = d->revision; 1029 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 1030 cts->xport_specific.sata.caps = d->caps; 1031 } 1032 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 1033 cts->xport_specific.sata.atapi = d->atapi; 1034 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 1035 } else { 1036 cts->transport = XPORT_ATA; 1037 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 1038 cts->xport_specific.ata.valid = 0; 1039 cts->xport_specific.ata.mode = d->mode; 1040 cts->xport_specific.ata.valid |= CTS_ATA_VALID_MODE; 1041 cts->xport_specific.ata.bytecount = d->bytecount; 1042 cts->xport_specific.ata.valid |= CTS_ATA_VALID_BYTECOUNT; 1043 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 1044 cts->xport_specific.ata.caps = 1045 d->caps & CTS_ATA_CAPS_D; 1046 if (!(ch->flags & ATA_NO_48BIT_DMA)) 1047 cts->xport_specific.ata.caps |= 1048 CTS_ATA_CAPS_H_DMA48; 1049 cts->xport_specific.ata.caps &= 1050 ch->user[ccb->ccb_h.target_id].caps; 1051 } else 1052 cts->xport_specific.ata.caps = d->caps; 1053 cts->xport_specific.ata.valid |= CTS_ATA_VALID_CAPS; 1054 cts->xport_specific.ata.atapi = d->atapi; 1055 cts->xport_specific.ata.valid |= CTS_ATA_VALID_ATAPI; 1056 } 1057 ccb->ccb_h.status = CAM_REQ_CMP; 1058 break; 1059 } 1060 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 1061 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 1062 ata_reinit(dev); 1063 ccb->ccb_h.status = CAM_REQ_CMP; 1064 break; 1065 case XPT_TERM_IO: /* Terminate the I/O process */ 1066 /* XXX Implement */ 1067 ccb->ccb_h.status = CAM_REQ_INVALID; 1068 break; 1069 case XPT_PATH_INQ: /* Path routing inquiry */ 1070 { 1071 struct ccb_pathinq *cpi = &ccb->cpi; 1072 1073 parent = device_get_parent(dev); 1074 cpi->version_num = 1; /* XXX??? */ 1075 cpi->hba_inquiry = PI_SDTR_ABLE; 1076 cpi->target_sprt = 0; 1077 cpi->hba_misc = PIM_SEQSCAN; 1078 cpi->hba_eng_cnt = 0; 1079 if (ch->flags & ATA_NO_SLAVE) 1080 cpi->max_target = 0; 1081 else 1082 cpi->max_target = 1; 1083 cpi->max_lun = 0; 1084 cpi->initiator_id = 0; 1085 cpi->bus_id = cam_sim_bus(sim); 1086 if (ch->flags & ATA_SATA) 1087 cpi->base_transfer_speed = 150000; 1088 else 1089 cpi->base_transfer_speed = 3300; 1090 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 1091 strncpy(cpi->hba_vid, "ATA", HBA_IDLEN); 1092 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 1093 cpi->unit_number = cam_sim_unit(sim); 1094 if (ch->flags & ATA_SATA) 1095 cpi->transport = XPORT_SATA; 1096 else 1097 cpi->transport = XPORT_ATA; 1098 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 1099 cpi->protocol = PROTO_ATA; 1100 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 1101 cpi->maxio = ch->dma.max_iosize ? ch->dma.max_iosize : DFLTPHYS; 1102 if (device_get_devclass(device_get_parent(parent)) == 1103 devclass_find("pci")) { 1104 cpi->hba_vendor = pci_get_vendor(parent); 1105 cpi->hba_device = pci_get_device(parent); 1106 cpi->hba_subvendor = pci_get_subvendor(parent); 1107 cpi->hba_subdevice = pci_get_subdevice(parent); 1108 } 1109 cpi->ccb_h.status = CAM_REQ_CMP; 1110 break; 1111 } 1112 default: 1113 ccb->ccb_h.status = CAM_REQ_INVALID; 1114 break; 1115 } 1116 xpt_done(ccb); 1117 } 1118 1119 static void 1120 atapoll(struct cam_sim *sim) 1121 { 1122 struct ata_channel *ch = (struct ata_channel *)cam_sim_softc(sim); 1123 1124 ata_interrupt_locked(ch); 1125 } 1126 1127 /* 1128 * module handeling 1129 */ 1130 static int 1131 ata_module_event_handler(module_t mod, int what, void *arg) 1132 { 1133 1134 switch (what) { 1135 case MOD_LOAD: 1136 return 0; 1137 1138 case MOD_UNLOAD: 1139 return 0; 1140 1141 default: 1142 return EOPNOTSUPP; 1143 } 1144 } 1145 1146 static moduledata_t ata_moduledata = { "ata", ata_module_event_handler, NULL }; 1147 DECLARE_MODULE(ata, ata_moduledata, SI_SUB_CONFIGURE, SI_ORDER_SECOND); 1148 MODULE_VERSION(ata, 1); 1149 MODULE_DEPEND(ata, cam, 1, 1, 1); 1150 1151 static void 1152 ata_init(void) 1153 { 1154 ata_request_zone = uma_zcreate("ata_request", sizeof(struct ata_request), 1155 NULL, NULL, NULL, NULL, 0, 0); 1156 } 1157 SYSINIT(ata_register, SI_SUB_DRIVERS, SI_ORDER_SECOND, ata_init, NULL); 1158 1159 static void 1160 ata_uninit(void) 1161 { 1162 uma_zdestroy(ata_request_zone); 1163 } 1164 SYSUNINIT(ata_unregister, SI_SUB_DRIVERS, SI_ORDER_SECOND, ata_uninit, NULL); 1165