1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/ata.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/endian.h> 35 #include <sys/ctype.h> 36 #include <sys/conf.h> 37 #include <sys/bus.h> 38 #include <sys/bio.h> 39 #include <sys/malloc.h> 40 #include <sys/sysctl.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/ata/ata-all.h> 49 #include <dev/pci/pcivar.h> 50 #include <ata_if.h> 51 52 #include <cam/cam.h> 53 #include <cam/cam_ccb.h> 54 #include <cam/cam_sim.h> 55 #include <cam/cam_xpt_sim.h> 56 #include <cam/cam_debug.h> 57 58 /* prototypes */ 59 static void ataaction(struct cam_sim *sim, union ccb *ccb); 60 static void atapoll(struct cam_sim *sim); 61 static void ata_cam_begin_transaction(device_t dev, union ccb *ccb); 62 static void ata_cam_end_transaction(device_t dev, struct ata_request *request); 63 static void ata_cam_request_sense(device_t dev, struct ata_request *request); 64 static int ata_check_ids(device_t dev, union ccb *ccb); 65 static void ata_conn_event(void *context, int dummy); 66 static void ata_interrupt_locked(void *data); 67 static int ata_module_event_handler(module_t mod, int what, void *arg); 68 static void ata_periodic_poll(void *data); 69 static int ata_str2mode(const char *str); 70 71 /* global vars */ 72 MALLOC_DEFINE(M_ATA, "ata_generic", "ATA driver generic layer"); 73 devclass_t ata_devclass; 74 int ata_dma_check_80pin = 1; 75 76 /* sysctl vars */ 77 static SYSCTL_NODE(_hw, OID_AUTO, ata, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 78 "ATA driver parameters"); 79 SYSCTL_INT(_hw_ata, OID_AUTO, ata_dma_check_80pin, 80 CTLFLAG_RWTUN, &ata_dma_check_80pin, 0, 81 "Check for 80pin cable before setting ATA DMA mode"); 82 FEATURE(ata_cam, "ATA devices are accessed through the cam(4) driver"); 83 84 /* 85 * newbus device interface related functions 86 */ 87 int 88 ata_probe(device_t dev) 89 { 90 return (BUS_PROBE_LOW_PRIORITY); 91 } 92 93 int 94 ata_attach(device_t dev) 95 { 96 struct ata_channel *ch = device_get_softc(dev); 97 int error, rid; 98 struct cam_devq *devq; 99 const char *res; 100 char buf[64]; 101 int i, mode; 102 103 /* check that we have a virgin channel to attach */ 104 if (ch->r_irq) 105 return EEXIST; 106 107 /* initialize the softc basics */ 108 ch->dev = dev; 109 ch->state = ATA_IDLE; 110 bzero(&ch->state_mtx, sizeof(struct mtx)); 111 mtx_init(&ch->state_mtx, "ATA state lock", NULL, MTX_DEF); 112 TASK_INIT(&ch->conntask, 0, ata_conn_event, dev); 113 for (i = 0; i < 16; i++) { 114 ch->user[i].revision = 0; 115 snprintf(buf, sizeof(buf), "dev%d.sata_rev", i); 116 if (resource_int_value(device_get_name(dev), 117 device_get_unit(dev), buf, &mode) != 0 && 118 resource_int_value(device_get_name(dev), 119 device_get_unit(dev), "sata_rev", &mode) != 0) 120 mode = -1; 121 if (mode >= 0) 122 ch->user[i].revision = mode; 123 ch->user[i].mode = 0; 124 snprintf(buf, sizeof(buf), "dev%d.mode", i); 125 if (resource_string_value(device_get_name(dev), 126 device_get_unit(dev), buf, &res) == 0) 127 mode = ata_str2mode(res); 128 else if (resource_string_value(device_get_name(dev), 129 device_get_unit(dev), "mode", &res) == 0) 130 mode = ata_str2mode(res); 131 else 132 mode = -1; 133 if (mode >= 0) 134 ch->user[i].mode = mode; 135 if (ch->flags & ATA_SATA) 136 ch->user[i].bytecount = 8192; 137 else 138 ch->user[i].bytecount = 65536; 139 ch->user[i].caps = 0; 140 ch->curr[i] = ch->user[i]; 141 if (ch->flags & ATA_SATA) { 142 if (ch->pm_level > 0) 143 ch->user[i].caps |= CTS_SATA_CAPS_H_PMREQ; 144 if (ch->pm_level > 1) 145 ch->user[i].caps |= CTS_SATA_CAPS_D_PMREQ; 146 } else { 147 if (!(ch->flags & ATA_NO_48BIT_DMA)) 148 ch->user[i].caps |= CTS_ATA_CAPS_H_DMA48; 149 } 150 } 151 callout_init(&ch->poll_callout, 1); 152 153 /* allocate DMA resources if DMA HW present*/ 154 if (ch->dma.alloc) 155 ch->dma.alloc(dev); 156 157 /* setup interrupt delivery */ 158 rid = ATA_IRQ_RID; 159 ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 160 RF_SHAREABLE | RF_ACTIVE); 161 if (!ch->r_irq) { 162 device_printf(dev, "unable to allocate interrupt\n"); 163 return ENXIO; 164 } 165 if ((error = bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 166 ata_interrupt, ch, &ch->ih))) { 167 bus_release_resource(dev, SYS_RES_IRQ, rid, ch->r_irq); 168 device_printf(dev, "unable to setup interrupt\n"); 169 return error; 170 } 171 172 if (ch->flags & ATA_PERIODIC_POLL) 173 callout_reset(&ch->poll_callout, hz, ata_periodic_poll, ch); 174 mtx_lock(&ch->state_mtx); 175 /* Create the device queue for our SIM. */ 176 devq = cam_simq_alloc(1); 177 if (devq == NULL) { 178 device_printf(dev, "Unable to allocate simq\n"); 179 error = ENOMEM; 180 goto err1; 181 } 182 /* Construct SIM entry */ 183 ch->sim = cam_sim_alloc(ataaction, atapoll, "ata", ch, 184 device_get_unit(dev), &ch->state_mtx, 1, 0, devq); 185 if (ch->sim == NULL) { 186 device_printf(dev, "unable to allocate sim\n"); 187 cam_simq_free(devq); 188 error = ENOMEM; 189 goto err1; 190 } 191 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 192 device_printf(dev, "unable to register xpt bus\n"); 193 error = ENXIO; 194 goto err2; 195 } 196 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 197 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 198 device_printf(dev, "unable to create path\n"); 199 error = ENXIO; 200 goto err3; 201 } 202 mtx_unlock(&ch->state_mtx); 203 return (0); 204 205 err3: 206 xpt_bus_deregister(cam_sim_path(ch->sim)); 207 err2: 208 cam_sim_free(ch->sim, /*free_devq*/TRUE); 209 ch->sim = NULL; 210 err1: 211 bus_release_resource(dev, SYS_RES_IRQ, rid, ch->r_irq); 212 mtx_unlock(&ch->state_mtx); 213 if (ch->flags & ATA_PERIODIC_POLL) 214 callout_drain(&ch->poll_callout); 215 return (error); 216 } 217 218 int 219 ata_detach(device_t dev) 220 { 221 struct ata_channel *ch = device_get_softc(dev); 222 223 /* check that we have a valid channel to detach */ 224 if (!ch->r_irq) 225 return ENXIO; 226 227 /* grap the channel lock so no new requests gets launched */ 228 mtx_lock(&ch->state_mtx); 229 ch->state |= ATA_STALL_QUEUE; 230 mtx_unlock(&ch->state_mtx); 231 if (ch->flags & ATA_PERIODIC_POLL) 232 callout_drain(&ch->poll_callout); 233 234 taskqueue_drain(taskqueue_thread, &ch->conntask); 235 236 mtx_lock(&ch->state_mtx); 237 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 238 xpt_free_path(ch->path); 239 xpt_bus_deregister(cam_sim_path(ch->sim)); 240 cam_sim_free(ch->sim, /*free_devq*/TRUE); 241 ch->sim = NULL; 242 mtx_unlock(&ch->state_mtx); 243 244 /* release resources */ 245 bus_teardown_intr(dev, ch->r_irq, ch->ih); 246 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 247 ch->r_irq = NULL; 248 249 /* free DMA resources if DMA HW present*/ 250 if (ch->dma.free) 251 ch->dma.free(dev); 252 253 mtx_destroy(&ch->state_mtx); 254 return 0; 255 } 256 257 static void 258 ata_conn_event(void *context, int dummy) 259 { 260 device_t dev = (device_t)context; 261 struct ata_channel *ch = device_get_softc(dev); 262 union ccb *ccb; 263 264 mtx_lock(&ch->state_mtx); 265 if (ch->sim == NULL) { 266 mtx_unlock(&ch->state_mtx); 267 return; 268 } 269 ata_reinit(dev); 270 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 271 return; 272 if (xpt_create_path(&ccb->ccb_h.path, NULL, 273 cam_sim_path(ch->sim), 274 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 275 xpt_free_ccb(ccb); 276 return; 277 } 278 xpt_rescan(ccb); 279 mtx_unlock(&ch->state_mtx); 280 } 281 282 int 283 ata_reinit(device_t dev) 284 { 285 struct ata_channel *ch = device_get_softc(dev); 286 struct ata_request *request; 287 288 xpt_freeze_simq(ch->sim, 1); 289 if ((request = ch->running)) { 290 ch->running = NULL; 291 if (ch->state == ATA_ACTIVE) 292 ch->state = ATA_IDLE; 293 callout_stop(&request->callout); 294 if (ch->dma.unload) 295 ch->dma.unload(request); 296 request->result = ERESTART; 297 ata_cam_end_transaction(dev, request); 298 } 299 /* reset the controller HW, the channel and device(s) */ 300 ATA_RESET(dev); 301 /* Tell the XPT about the event */ 302 xpt_async(AC_BUS_RESET, ch->path, NULL); 303 xpt_release_simq(ch->sim, TRUE); 304 return(0); 305 } 306 307 int 308 ata_suspend(device_t dev) 309 { 310 struct ata_channel *ch; 311 312 /* check for valid device */ 313 if (!dev || !(ch = device_get_softc(dev))) 314 return ENXIO; 315 316 if (ch->flags & ATA_PERIODIC_POLL) 317 callout_drain(&ch->poll_callout); 318 mtx_lock(&ch->state_mtx); 319 xpt_freeze_simq(ch->sim, 1); 320 while (ch->state != ATA_IDLE) 321 msleep(ch, &ch->state_mtx, PRIBIO, "atasusp", hz/100); 322 mtx_unlock(&ch->state_mtx); 323 return(0); 324 } 325 326 int 327 ata_resume(device_t dev) 328 { 329 struct ata_channel *ch; 330 int error; 331 332 /* check for valid device */ 333 if (!dev || !(ch = device_get_softc(dev))) 334 return ENXIO; 335 336 mtx_lock(&ch->state_mtx); 337 error = ata_reinit(dev); 338 xpt_release_simq(ch->sim, TRUE); 339 mtx_unlock(&ch->state_mtx); 340 if (ch->flags & ATA_PERIODIC_POLL) 341 callout_reset(&ch->poll_callout, hz, ata_periodic_poll, ch); 342 return error; 343 } 344 345 void 346 ata_interrupt(void *data) 347 { 348 struct ata_channel *ch = (struct ata_channel *)data; 349 350 mtx_lock(&ch->state_mtx); 351 ata_interrupt_locked(data); 352 mtx_unlock(&ch->state_mtx); 353 } 354 355 static void 356 ata_interrupt_locked(void *data) 357 { 358 struct ata_channel *ch = (struct ata_channel *)data; 359 struct ata_request *request; 360 361 /* ignore interrupt if its not for us */ 362 if (ch->hw.status && !ch->hw.status(ch->dev)) 363 return; 364 365 /* do we have a running request */ 366 if (!(request = ch->running)) 367 return; 368 369 ATA_DEBUG_RQ(request, "interrupt"); 370 371 /* safetycheck for the right state */ 372 if (ch->state == ATA_IDLE) { 373 device_printf(request->dev, "interrupt on idle channel ignored\n"); 374 return; 375 } 376 377 /* 378 * we have the HW locks, so end the transaction for this request 379 * if it finishes immediately otherwise wait for next interrupt 380 */ 381 if (ch->hw.end_transaction(request) == ATA_OP_FINISHED) { 382 ch->running = NULL; 383 if (ch->state == ATA_ACTIVE) 384 ch->state = ATA_IDLE; 385 ata_cam_end_transaction(ch->dev, request); 386 return; 387 } 388 } 389 390 static void 391 ata_periodic_poll(void *data) 392 { 393 struct ata_channel *ch = (struct ata_channel *)data; 394 395 callout_reset(&ch->poll_callout, hz, ata_periodic_poll, ch); 396 ata_interrupt(ch); 397 } 398 399 void 400 ata_print_cable(device_t dev, u_int8_t *who) 401 { 402 device_printf(dev, 403 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who); 404 } 405 406 /* 407 * misc support functions 408 */ 409 void 410 ata_default_registers(device_t dev) 411 { 412 struct ata_channel *ch = device_get_softc(dev); 413 414 /* fill in the defaults from whats setup already */ 415 ch->r_io[ATA_ERROR].res = ch->r_io[ATA_FEATURE].res; 416 ch->r_io[ATA_ERROR].offset = ch->r_io[ATA_FEATURE].offset; 417 ch->r_io[ATA_IREASON].res = ch->r_io[ATA_COUNT].res; 418 ch->r_io[ATA_IREASON].offset = ch->r_io[ATA_COUNT].offset; 419 ch->r_io[ATA_STATUS].res = ch->r_io[ATA_COMMAND].res; 420 ch->r_io[ATA_STATUS].offset = ch->r_io[ATA_COMMAND].offset; 421 ch->r_io[ATA_ALTSTAT].res = ch->r_io[ATA_CONTROL].res; 422 ch->r_io[ATA_ALTSTAT].offset = ch->r_io[ATA_CONTROL].offset; 423 } 424 425 void 426 ata_udelay(int interval) 427 { 428 /* for now just use DELAY, the timer/sleep subsystems are not there yet */ 429 if (1 || interval < (1000000/hz)) 430 DELAY(interval); 431 else 432 pause("ataslp", interval/(1000000/hz)); 433 } 434 435 const char * 436 ata_cmd2str(struct ata_request *request) 437 { 438 static char buffer[20]; 439 440 if (request->flags & ATA_R_ATAPI) { 441 switch (request->u.atapi.sense.key ? 442 request->u.atapi.saved_cmd : request->u.atapi.ccb[0]) { 443 case 0x00: return ("TEST_UNIT_READY"); 444 case 0x01: return ("REZERO"); 445 case 0x03: return ("REQUEST_SENSE"); 446 case 0x04: return ("FORMAT"); 447 case 0x08: return ("READ"); 448 case 0x0a: return ("WRITE"); 449 case 0x10: return ("WEOF"); 450 case 0x11: return ("SPACE"); 451 case 0x12: return ("INQUIRY"); 452 case 0x15: return ("MODE_SELECT"); 453 case 0x19: return ("ERASE"); 454 case 0x1a: return ("MODE_SENSE"); 455 case 0x1b: return ("START_STOP"); 456 case 0x1e: return ("PREVENT_ALLOW"); 457 case 0x23: return ("ATAPI_READ_FORMAT_CAPACITIES"); 458 case 0x25: return ("READ_CAPACITY"); 459 case 0x28: return ("READ_BIG"); 460 case 0x2a: return ("WRITE_BIG"); 461 case 0x2b: return ("LOCATE"); 462 case 0x34: return ("READ_POSITION"); 463 case 0x35: return ("SYNCHRONIZE_CACHE"); 464 case 0x3b: return ("WRITE_BUFFER"); 465 case 0x3c: return ("READ_BUFFER"); 466 case 0x42: return ("READ_SUBCHANNEL"); 467 case 0x43: return ("READ_TOC"); 468 case 0x45: return ("PLAY_10"); 469 case 0x47: return ("PLAY_MSF"); 470 case 0x48: return ("PLAY_TRACK"); 471 case 0x4b: return ("PAUSE"); 472 case 0x51: return ("READ_DISK_INFO"); 473 case 0x52: return ("READ_TRACK_INFO"); 474 case 0x53: return ("RESERVE_TRACK"); 475 case 0x54: return ("SEND_OPC_INFO"); 476 case 0x55: return ("MODE_SELECT_BIG"); 477 case 0x58: return ("REPAIR_TRACK"); 478 case 0x59: return ("READ_MASTER_CUE"); 479 case 0x5a: return ("MODE_SENSE_BIG"); 480 case 0x5b: return ("CLOSE_TRACK/SESSION"); 481 case 0x5c: return ("READ_BUFFER_CAPACITY"); 482 case 0x5d: return ("SEND_CUE_SHEET"); 483 case 0x96: return ("SERVICE_ACTION_IN"); 484 case 0xa1: return ("BLANK_CMD"); 485 case 0xa3: return ("SEND_KEY"); 486 case 0xa4: return ("REPORT_KEY"); 487 case 0xa5: return ("PLAY_12"); 488 case 0xa6: return ("LOAD_UNLOAD"); 489 case 0xad: return ("READ_DVD_STRUCTURE"); 490 case 0xb4: return ("PLAY_CD"); 491 case 0xbb: return ("SET_SPEED"); 492 case 0xbd: return ("MECH_STATUS"); 493 case 0xbe: return ("READ_CD"); 494 case 0xff: return ("POLL_DSC"); 495 } 496 } else { 497 switch (request->u.ata.command) { 498 case 0x00: 499 switch (request->u.ata.feature) { 500 case 0x00: return ("NOP FLUSHQUEUE"); 501 case 0x01: return ("NOP AUTOPOLL"); 502 } 503 return ("NOP"); 504 case 0x03: return ("CFA_REQUEST_EXTENDED_ERROR"); 505 case 0x06: 506 switch (request->u.ata.feature) { 507 case 0x01: return ("DSM TRIM"); 508 } 509 return "DSM"; 510 case 0x08: return ("DEVICE_RESET"); 511 case 0x20: return ("READ"); 512 case 0x24: return ("READ48"); 513 case 0x25: return ("READ_DMA48"); 514 case 0x26: return ("READ_DMA_QUEUED48"); 515 case 0x27: return ("READ_NATIVE_MAX_ADDRESS48"); 516 case 0x29: return ("READ_MUL48"); 517 case 0x2a: return ("READ_STREAM_DMA48"); 518 case 0x2b: return ("READ_STREAM48"); 519 case 0x2f: return ("READ_LOG_EXT"); 520 case 0x30: return ("WRITE"); 521 case 0x34: return ("WRITE48"); 522 case 0x35: return ("WRITE_DMA48"); 523 case 0x36: return ("WRITE_DMA_QUEUED48"); 524 case 0x37: return ("SET_MAX_ADDRESS48"); 525 case 0x39: return ("WRITE_MUL48"); 526 case 0x3a: return ("WRITE_STREAM_DMA48"); 527 case 0x3b: return ("WRITE_STREAM48"); 528 case 0x3d: return ("WRITE_DMA_FUA48"); 529 case 0x3e: return ("WRITE_DMA_QUEUED_FUA48"); 530 case 0x3f: return ("WRITE_LOG_EXT"); 531 case 0x40: return ("READ_VERIFY"); 532 case 0x42: return ("READ_VERIFY48"); 533 case 0x45: 534 switch (request->u.ata.feature) { 535 case 0x55: return ("WRITE_UNCORRECTABLE48 PSEUDO"); 536 case 0xaa: return ("WRITE_UNCORRECTABLE48 FLAGGED"); 537 } 538 return "WRITE_UNCORRECTABLE48"; 539 case 0x51: return ("CONFIGURE_STREAM"); 540 case 0x60: return ("READ_FPDMA_QUEUED"); 541 case 0x61: return ("WRITE_FPDMA_QUEUED"); 542 case 0x63: return ("NCQ_NON_DATA"); 543 case 0x64: return ("SEND_FPDMA_QUEUED"); 544 case 0x65: return ("RECEIVE_FPDMA_QUEUED"); 545 case 0x67: 546 if (request->u.ata.feature == 0xec) 547 return ("SEP_ATTN IDENTIFY"); 548 switch (request->u.ata.lba) { 549 case 0x00: return ("SEP_ATTN READ BUFFER"); 550 case 0x02: return ("SEP_ATTN RECEIVE DIAGNOSTIC RESULTS"); 551 case 0x80: return ("SEP_ATTN WRITE BUFFER"); 552 case 0x82: return ("SEP_ATTN SEND DIAGNOSTIC"); 553 } 554 return ("SEP_ATTN"); 555 case 0x70: return ("SEEK"); 556 case 0x87: return ("CFA_TRANSLATE_SECTOR"); 557 case 0x90: return ("EXECUTE_DEVICE_DIAGNOSTIC"); 558 case 0x92: return ("DOWNLOAD_MICROCODE"); 559 case 0xa0: return ("PACKET"); 560 case 0xa1: return ("ATAPI_IDENTIFY"); 561 case 0xa2: return ("SERVICE"); 562 case 0xb0: 563 switch(request->u.ata.feature) { 564 case 0xd0: return ("SMART READ ATTR VALUES"); 565 case 0xd1: return ("SMART READ ATTR THRESHOLDS"); 566 case 0xd3: return ("SMART SAVE ATTR VALUES"); 567 case 0xd4: return ("SMART EXECUTE OFFLINE IMMEDIATE"); 568 case 0xd5: return ("SMART READ LOG DATA"); 569 case 0xd8: return ("SMART ENABLE OPERATION"); 570 case 0xd9: return ("SMART DISABLE OPERATION"); 571 case 0xda: return ("SMART RETURN STATUS"); 572 } 573 return ("SMART"); 574 case 0xb1: return ("DEVICE CONFIGURATION"); 575 case 0xc0: return ("CFA_ERASE"); 576 case 0xc4: return ("READ_MUL"); 577 case 0xc5: return ("WRITE_MUL"); 578 case 0xc6: return ("SET_MULTI"); 579 case 0xc7: return ("READ_DMA_QUEUED"); 580 case 0xc8: return ("READ_DMA"); 581 case 0xca: return ("WRITE_DMA"); 582 case 0xcc: return ("WRITE_DMA_QUEUED"); 583 case 0xcd: return ("CFA_WRITE_MULTIPLE_WITHOUT_ERASE"); 584 case 0xce: return ("WRITE_MUL_FUA48"); 585 case 0xd1: return ("CHECK_MEDIA_CARD_TYPE"); 586 case 0xda: return ("GET_MEDIA_STATUS"); 587 case 0xde: return ("MEDIA_LOCK"); 588 case 0xdf: return ("MEDIA_UNLOCK"); 589 case 0xe0: return ("STANDBY_IMMEDIATE"); 590 case 0xe1: return ("IDLE_IMMEDIATE"); 591 case 0xe2: return ("STANDBY"); 592 case 0xe3: return ("IDLE"); 593 case 0xe4: return ("READ_BUFFER/PM"); 594 case 0xe5: return ("CHECK_POWER_MODE"); 595 case 0xe6: return ("SLEEP"); 596 case 0xe7: return ("FLUSHCACHE"); 597 case 0xe8: return ("WRITE_PM"); 598 case 0xea: return ("FLUSHCACHE48"); 599 case 0xec: return ("ATA_IDENTIFY"); 600 case 0xed: return ("MEDIA_EJECT"); 601 case 0xef: 602 switch (request->u.ata.feature) { 603 case 0x03: return ("SETFEATURES SET TRANSFER MODE"); 604 case 0x02: return ("SETFEATURES ENABLE WCACHE"); 605 case 0x82: return ("SETFEATURES DISABLE WCACHE"); 606 case 0x06: return ("SETFEATURES ENABLE PUIS"); 607 case 0x86: return ("SETFEATURES DISABLE PUIS"); 608 case 0x07: return ("SETFEATURES SPIN-UP"); 609 case 0x10: return ("SETFEATURES ENABLE SATA FEATURE"); 610 case 0x90: return ("SETFEATURES DISABLE SATA FEATURE"); 611 case 0xaa: return ("SETFEATURES ENABLE RCACHE"); 612 case 0x55: return ("SETFEATURES DISABLE RCACHE"); 613 case 0x5d: return ("SETFEATURES ENABLE RELIRQ"); 614 case 0xdd: return ("SETFEATURES DISABLE RELIRQ"); 615 case 0x5e: return ("SETFEATURES ENABLE SRVIRQ"); 616 case 0xde: return ("SETFEATURES DISABLE SRVIRQ"); 617 } 618 return "SETFEATURES"; 619 case 0xf1: return ("SECURITY_SET_PASSWORD"); 620 case 0xf2: return ("SECURITY_UNLOCK"); 621 case 0xf3: return ("SECURITY_ERASE_PREPARE"); 622 case 0xf4: return ("SECURITY_ERASE_UNIT"); 623 case 0xf5: return ("SECURITY_FREEZE_LOCK"); 624 case 0xf6: return ("SECURITY_DISABLE_PASSWORD"); 625 case 0xf8: return ("READ_NATIVE_MAX_ADDRESS"); 626 case 0xf9: return ("SET_MAX_ADDRESS"); 627 } 628 } 629 sprintf(buffer, "unknown CMD (0x%02x)", request->u.ata.command); 630 return (buffer); 631 } 632 633 const char * 634 ata_mode2str(int mode) 635 { 636 switch (mode) { 637 case -1: return "UNSUPPORTED"; 638 case ATA_PIO0: return "PIO0"; 639 case ATA_PIO1: return "PIO1"; 640 case ATA_PIO2: return "PIO2"; 641 case ATA_PIO3: return "PIO3"; 642 case ATA_PIO4: return "PIO4"; 643 case ATA_WDMA0: return "WDMA0"; 644 case ATA_WDMA1: return "WDMA1"; 645 case ATA_WDMA2: return "WDMA2"; 646 case ATA_UDMA0: return "UDMA16"; 647 case ATA_UDMA1: return "UDMA25"; 648 case ATA_UDMA2: return "UDMA33"; 649 case ATA_UDMA3: return "UDMA40"; 650 case ATA_UDMA4: return "UDMA66"; 651 case ATA_UDMA5: return "UDMA100"; 652 case ATA_UDMA6: return "UDMA133"; 653 case ATA_SA150: return "SATA150"; 654 case ATA_SA300: return "SATA300"; 655 case ATA_SA600: return "SATA600"; 656 default: 657 if (mode & ATA_DMA_MASK) 658 return "BIOSDMA"; 659 else 660 return "BIOSPIO"; 661 } 662 } 663 664 static int 665 ata_str2mode(const char *str) 666 { 667 668 if (!strcasecmp(str, "PIO0")) return (ATA_PIO0); 669 if (!strcasecmp(str, "PIO1")) return (ATA_PIO1); 670 if (!strcasecmp(str, "PIO2")) return (ATA_PIO2); 671 if (!strcasecmp(str, "PIO3")) return (ATA_PIO3); 672 if (!strcasecmp(str, "PIO4")) return (ATA_PIO4); 673 if (!strcasecmp(str, "WDMA0")) return (ATA_WDMA0); 674 if (!strcasecmp(str, "WDMA1")) return (ATA_WDMA1); 675 if (!strcasecmp(str, "WDMA2")) return (ATA_WDMA2); 676 if (!strcasecmp(str, "UDMA0")) return (ATA_UDMA0); 677 if (!strcasecmp(str, "UDMA16")) return (ATA_UDMA0); 678 if (!strcasecmp(str, "UDMA1")) return (ATA_UDMA1); 679 if (!strcasecmp(str, "UDMA25")) return (ATA_UDMA1); 680 if (!strcasecmp(str, "UDMA2")) return (ATA_UDMA2); 681 if (!strcasecmp(str, "UDMA33")) return (ATA_UDMA2); 682 if (!strcasecmp(str, "UDMA3")) return (ATA_UDMA3); 683 if (!strcasecmp(str, "UDMA44")) return (ATA_UDMA3); 684 if (!strcasecmp(str, "UDMA4")) return (ATA_UDMA4); 685 if (!strcasecmp(str, "UDMA66")) return (ATA_UDMA4); 686 if (!strcasecmp(str, "UDMA5")) return (ATA_UDMA5); 687 if (!strcasecmp(str, "UDMA100")) return (ATA_UDMA5); 688 if (!strcasecmp(str, "UDMA6")) return (ATA_UDMA6); 689 if (!strcasecmp(str, "UDMA133")) return (ATA_UDMA6); 690 return (-1); 691 } 692 693 int 694 ata_atapi(device_t dev, int target) 695 { 696 struct ata_channel *ch = device_get_softc(dev); 697 698 return (ch->devices & (ATA_ATAPI_MASTER << target)); 699 } 700 701 void 702 ata_timeout(void *arg) 703 { 704 struct ata_request *request; 705 struct ata_channel *ch; 706 707 request = arg; 708 ch = device_get_softc(request->parent); 709 //request->flags |= ATA_R_DEBUG; 710 ATA_DEBUG_RQ(request, "timeout"); 711 712 /* 713 * If we have an ATA_ACTIVE request running, we flag the request 714 * ATA_R_TIMEOUT so ata_cam_end_transaction() will handle it correctly. 715 * Also, NULL out the running request so we wont loose the race with 716 * an eventual interrupt arriving late. 717 */ 718 if (ch->state == ATA_ACTIVE) { 719 request->flags |= ATA_R_TIMEOUT; 720 if (ch->dma.unload) 721 ch->dma.unload(request); 722 ch->running = NULL; 723 ch->state = ATA_IDLE; 724 ata_cam_end_transaction(ch->dev, request); 725 } 726 mtx_unlock(&ch->state_mtx); 727 } 728 729 static void 730 ata_cam_begin_transaction(device_t dev, union ccb *ccb) 731 { 732 struct ata_channel *ch = device_get_softc(dev); 733 struct ata_request *request; 734 735 request = &ch->request; 736 bzero(request, sizeof(*request)); 737 738 /* setup request */ 739 request->dev = NULL; 740 request->parent = dev; 741 request->unit = ccb->ccb_h.target_id; 742 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 743 request->data = ccb->ataio.data_ptr; 744 request->bytecount = ccb->ataio.dxfer_len; 745 request->u.ata.command = ccb->ataio.cmd.command; 746 request->u.ata.feature = ((uint16_t)ccb->ataio.cmd.features_exp << 8) | 747 (uint16_t)ccb->ataio.cmd.features; 748 request->u.ata.count = ((uint16_t)ccb->ataio.cmd.sector_count_exp << 8) | 749 (uint16_t)ccb->ataio.cmd.sector_count; 750 if (ccb->ataio.cmd.flags & CAM_ATAIO_48BIT) { 751 request->flags |= ATA_R_48BIT; 752 request->u.ata.lba = 753 ((uint64_t)ccb->ataio.cmd.lba_high_exp << 40) | 754 ((uint64_t)ccb->ataio.cmd.lba_mid_exp << 32) | 755 ((uint64_t)ccb->ataio.cmd.lba_low_exp << 24); 756 } else { 757 request->u.ata.lba = 758 ((uint64_t)(ccb->ataio.cmd.device & 0x0f) << 24); 759 } 760 request->u.ata.lba |= ((uint64_t)ccb->ataio.cmd.lba_high << 16) | 761 ((uint64_t)ccb->ataio.cmd.lba_mid << 8) | 762 (uint64_t)ccb->ataio.cmd.lba_low; 763 if (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT) 764 request->flags |= ATA_R_NEEDRESULT; 765 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 766 ccb->ataio.cmd.flags & CAM_ATAIO_DMA) 767 request->flags |= ATA_R_DMA; 768 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 769 request->flags |= ATA_R_READ; 770 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) 771 request->flags |= ATA_R_WRITE; 772 if (ccb->ataio.cmd.command == ATA_READ_MUL || 773 ccb->ataio.cmd.command == ATA_READ_MUL48 || 774 ccb->ataio.cmd.command == ATA_WRITE_MUL || 775 ccb->ataio.cmd.command == ATA_WRITE_MUL48) { 776 request->transfersize = min(request->bytecount, 777 ch->curr[ccb->ccb_h.target_id].bytecount); 778 } else 779 request->transfersize = min(request->bytecount, 512); 780 } else { 781 request->data = ccb->csio.data_ptr; 782 request->bytecount = ccb->csio.dxfer_len; 783 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 784 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 785 request->u.atapi.ccb, ccb->csio.cdb_len); 786 request->flags |= ATA_R_ATAPI; 787 if (ch->curr[ccb->ccb_h.target_id].atapi == 16) 788 request->flags |= ATA_R_ATAPI16; 789 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 790 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 791 request->flags |= ATA_R_DMA; 792 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 793 request->flags |= ATA_R_READ; 794 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) 795 request->flags |= ATA_R_WRITE; 796 request->transfersize = min(request->bytecount, 797 ch->curr[ccb->ccb_h.target_id].bytecount); 798 } 799 request->retries = 0; 800 request->timeout = (ccb->ccb_h.timeout + 999) / 1000; 801 callout_init_mtx(&request->callout, &ch->state_mtx, CALLOUT_RETURNUNLOCKED); 802 request->ccb = ccb; 803 request->flags |= ATA_R_DATA_IN_CCB; 804 805 ch->running = request; 806 ch->state = ATA_ACTIVE; 807 if (ch->hw.begin_transaction(request) == ATA_OP_FINISHED) { 808 ch->running = NULL; 809 ch->state = ATA_IDLE; 810 ata_cam_end_transaction(dev, request); 811 return; 812 } 813 } 814 815 static void 816 ata_cam_request_sense(device_t dev, struct ata_request *request) 817 { 818 struct ata_channel *ch = device_get_softc(dev); 819 union ccb *ccb = request->ccb; 820 821 ch->requestsense = 1; 822 823 bzero(request, sizeof(*request)); 824 request->dev = NULL; 825 request->parent = dev; 826 request->unit = ccb->ccb_h.target_id; 827 request->data = (void *)&ccb->csio.sense_data; 828 request->bytecount = ccb->csio.sense_len; 829 request->u.atapi.ccb[0] = ATAPI_REQUEST_SENSE; 830 request->u.atapi.ccb[4] = ccb->csio.sense_len; 831 request->flags |= ATA_R_ATAPI; 832 if (ch->curr[ccb->ccb_h.target_id].atapi == 16) 833 request->flags |= ATA_R_ATAPI16; 834 if (ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 835 request->flags |= ATA_R_DMA; 836 request->flags |= ATA_R_READ; 837 request->transfersize = min(request->bytecount, 838 ch->curr[ccb->ccb_h.target_id].bytecount); 839 request->retries = 0; 840 request->timeout = (ccb->ccb_h.timeout + 999) / 1000; 841 callout_init_mtx(&request->callout, &ch->state_mtx, CALLOUT_RETURNUNLOCKED); 842 request->ccb = ccb; 843 844 ch->running = request; 845 ch->state = ATA_ACTIVE; 846 if (ch->hw.begin_transaction(request) == ATA_OP_FINISHED) { 847 ch->running = NULL; 848 ch->state = ATA_IDLE; 849 ata_cam_end_transaction(dev, request); 850 return; 851 } 852 } 853 854 static void 855 ata_cam_process_sense(device_t dev, struct ata_request *request) 856 { 857 struct ata_channel *ch = device_get_softc(dev); 858 union ccb *ccb = request->ccb; 859 int fatalerr = 0; 860 861 ch->requestsense = 0; 862 863 if (request->flags & ATA_R_TIMEOUT) 864 fatalerr = 1; 865 if ((request->flags & ATA_R_TIMEOUT) == 0 && 866 (request->status & ATA_S_ERROR) == 0 && 867 request->result == 0) { 868 ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 869 } else { 870 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 871 ccb->ccb_h.status |= CAM_AUTOSENSE_FAIL; 872 } 873 874 xpt_done(ccb); 875 /* Do error recovery if needed. */ 876 if (fatalerr) 877 ata_reinit(dev); 878 } 879 880 static void 881 ata_cam_end_transaction(device_t dev, struct ata_request *request) 882 { 883 struct ata_channel *ch = device_get_softc(dev); 884 union ccb *ccb = request->ccb; 885 int fatalerr = 0; 886 887 if (ch->requestsense) { 888 ata_cam_process_sense(dev, request); 889 return; 890 } 891 892 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 893 if (request->flags & ATA_R_TIMEOUT) { 894 xpt_freeze_simq(ch->sim, 1); 895 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 896 ccb->ccb_h.status |= CAM_CMD_TIMEOUT | CAM_RELEASE_SIMQ; 897 fatalerr = 1; 898 } else if (request->status & ATA_S_ERROR) { 899 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 900 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 901 } else { 902 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 903 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 904 } 905 } else if (request->result == ERESTART) 906 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 907 else if (request->result != 0) 908 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 909 else 910 ccb->ccb_h.status |= CAM_REQ_CMP; 911 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP && 912 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 913 xpt_freeze_devq(ccb->ccb_h.path, 1); 914 ccb->ccb_h.status |= CAM_DEV_QFRZN; 915 } 916 if (ccb->ccb_h.func_code == XPT_ATA_IO && 917 ((request->status & ATA_S_ERROR) || 918 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT))) { 919 struct ata_res *res = &ccb->ataio.res; 920 res->status = request->status; 921 res->error = request->error; 922 res->lba_low = request->u.ata.lba; 923 res->lba_mid = request->u.ata.lba >> 8; 924 res->lba_high = request->u.ata.lba >> 16; 925 res->device = request->u.ata.lba >> 24; 926 res->lba_low_exp = request->u.ata.lba >> 24; 927 res->lba_mid_exp = request->u.ata.lba >> 32; 928 res->lba_high_exp = request->u.ata.lba >> 40; 929 res->sector_count = request->u.ata.count; 930 res->sector_count_exp = request->u.ata.count >> 8; 931 } 932 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 933 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 934 ccb->ataio.resid = 935 ccb->ataio.dxfer_len - request->donecount; 936 } else { 937 ccb->csio.resid = 938 ccb->csio.dxfer_len - request->donecount; 939 } 940 } 941 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 942 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) 943 ata_cam_request_sense(dev, request); 944 else 945 xpt_done(ccb); 946 /* Do error recovery if needed. */ 947 if (fatalerr) 948 ata_reinit(dev); 949 } 950 951 static int 952 ata_check_ids(device_t dev, union ccb *ccb) 953 { 954 struct ata_channel *ch = device_get_softc(dev); 955 956 if (ccb->ccb_h.target_id > ((ch->flags & ATA_NO_SLAVE) ? 0 : 1)) { 957 ccb->ccb_h.status = CAM_TID_INVALID; 958 xpt_done(ccb); 959 return (-1); 960 } 961 if (ccb->ccb_h.target_lun != 0) { 962 ccb->ccb_h.status = CAM_LUN_INVALID; 963 xpt_done(ccb); 964 return (-1); 965 } 966 /* 967 * It's a programming error to see AUXILIARY register requests. 968 */ 969 KASSERT(ccb->ccb_h.func_code != XPT_ATA_IO || 970 ((ccb->ataio.ata_flags & ATA_FLAG_AUX) == 0), 971 ("AUX register unsupported")); 972 return (0); 973 } 974 975 static void 976 ataaction(struct cam_sim *sim, union ccb *ccb) 977 { 978 device_t dev, parent; 979 struct ata_channel *ch; 980 981 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ataaction func_code=%x\n", 982 ccb->ccb_h.func_code)); 983 984 ch = (struct ata_channel *)cam_sim_softc(sim); 985 dev = ch->dev; 986 switch (ccb->ccb_h.func_code) { 987 /* Common cases first */ 988 case XPT_ATA_IO: /* Execute the requested I/O operation */ 989 case XPT_SCSI_IO: 990 if (ata_check_ids(dev, ccb)) 991 return; 992 if ((ch->devices & ((ATA_ATA_MASTER | ATA_ATAPI_MASTER) 993 << ccb->ccb_h.target_id)) == 0) { 994 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 995 break; 996 } 997 if (ch->running) 998 device_printf(dev, "already running!\n"); 999 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1000 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1001 (ccb->ataio.cmd.control & ATA_A_RESET)) { 1002 struct ata_res *res = &ccb->ataio.res; 1003 1004 bzero(res, sizeof(*res)); 1005 if (ch->devices & (ATA_ATA_MASTER << ccb->ccb_h.target_id)) { 1006 res->lba_high = 0; 1007 res->lba_mid = 0; 1008 } else { 1009 res->lba_high = 0xeb; 1010 res->lba_mid = 0x14; 1011 } 1012 ccb->ccb_h.status = CAM_REQ_CMP; 1013 break; 1014 } 1015 ata_cam_begin_transaction(dev, ccb); 1016 return; 1017 case XPT_ABORT: /* Abort the specified CCB */ 1018 /* XXX Implement */ 1019 ccb->ccb_h.status = CAM_REQ_INVALID; 1020 break; 1021 case XPT_SET_TRAN_SETTINGS: 1022 { 1023 struct ccb_trans_settings *cts = &ccb->cts; 1024 struct ata_cam_device *d; 1025 1026 if (ata_check_ids(dev, ccb)) 1027 return; 1028 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 1029 d = &ch->curr[ccb->ccb_h.target_id]; 1030 else 1031 d = &ch->user[ccb->ccb_h.target_id]; 1032 if (ch->flags & ATA_SATA) { 1033 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 1034 d->revision = cts->xport_specific.sata.revision; 1035 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) { 1036 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 1037 d->mode = ATA_SETMODE(ch->dev, 1038 ccb->ccb_h.target_id, 1039 cts->xport_specific.sata.mode); 1040 } else 1041 d->mode = cts->xport_specific.sata.mode; 1042 } 1043 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 1044 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 1045 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 1046 d->atapi = cts->xport_specific.sata.atapi; 1047 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 1048 d->caps = cts->xport_specific.sata.caps; 1049 } else { 1050 if (cts->xport_specific.ata.valid & CTS_ATA_VALID_MODE) { 1051 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 1052 d->mode = ATA_SETMODE(ch->dev, 1053 ccb->ccb_h.target_id, 1054 cts->xport_specific.ata.mode); 1055 } else 1056 d->mode = cts->xport_specific.ata.mode; 1057 } 1058 if (cts->xport_specific.ata.valid & CTS_ATA_VALID_BYTECOUNT) 1059 d->bytecount = cts->xport_specific.ata.bytecount; 1060 if (cts->xport_specific.ata.valid & CTS_ATA_VALID_ATAPI) 1061 d->atapi = cts->xport_specific.ata.atapi; 1062 if (cts->xport_specific.ata.valid & CTS_ATA_VALID_CAPS) 1063 d->caps = cts->xport_specific.ata.caps; 1064 } 1065 ccb->ccb_h.status = CAM_REQ_CMP; 1066 break; 1067 } 1068 case XPT_GET_TRAN_SETTINGS: 1069 { 1070 struct ccb_trans_settings *cts = &ccb->cts; 1071 struct ata_cam_device *d; 1072 1073 if (ata_check_ids(dev, ccb)) 1074 return; 1075 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 1076 d = &ch->curr[ccb->ccb_h.target_id]; 1077 else 1078 d = &ch->user[ccb->ccb_h.target_id]; 1079 cts->protocol = PROTO_UNSPECIFIED; 1080 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 1081 if (ch->flags & ATA_SATA) { 1082 cts->transport = XPORT_SATA; 1083 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 1084 cts->xport_specific.sata.valid = 0; 1085 cts->xport_specific.sata.mode = d->mode; 1086 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 1087 cts->xport_specific.sata.bytecount = d->bytecount; 1088 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 1089 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 1090 cts->xport_specific.sata.revision = 1091 ATA_GETREV(dev, ccb->ccb_h.target_id); 1092 if (cts->xport_specific.sata.revision != 0xff) { 1093 cts->xport_specific.sata.valid |= 1094 CTS_SATA_VALID_REVISION; 1095 } 1096 cts->xport_specific.sata.caps = 1097 d->caps & CTS_SATA_CAPS_D; 1098 if (ch->pm_level) { 1099 cts->xport_specific.sata.caps |= 1100 CTS_SATA_CAPS_H_PMREQ; 1101 } 1102 cts->xport_specific.sata.caps &= 1103 ch->user[ccb->ccb_h.target_id].caps; 1104 } else { 1105 cts->xport_specific.sata.revision = d->revision; 1106 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 1107 cts->xport_specific.sata.caps = d->caps; 1108 } 1109 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 1110 cts->xport_specific.sata.atapi = d->atapi; 1111 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 1112 } else { 1113 cts->transport = XPORT_ATA; 1114 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 1115 cts->xport_specific.ata.valid = 0; 1116 cts->xport_specific.ata.mode = d->mode; 1117 cts->xport_specific.ata.valid |= CTS_ATA_VALID_MODE; 1118 cts->xport_specific.ata.bytecount = d->bytecount; 1119 cts->xport_specific.ata.valid |= CTS_ATA_VALID_BYTECOUNT; 1120 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 1121 cts->xport_specific.ata.caps = 1122 d->caps & CTS_ATA_CAPS_D; 1123 if (!(ch->flags & ATA_NO_48BIT_DMA)) 1124 cts->xport_specific.ata.caps |= 1125 CTS_ATA_CAPS_H_DMA48; 1126 cts->xport_specific.ata.caps &= 1127 ch->user[ccb->ccb_h.target_id].caps; 1128 } else 1129 cts->xport_specific.ata.caps = d->caps; 1130 cts->xport_specific.ata.valid |= CTS_ATA_VALID_CAPS; 1131 cts->xport_specific.ata.atapi = d->atapi; 1132 cts->xport_specific.ata.valid |= CTS_ATA_VALID_ATAPI; 1133 } 1134 ccb->ccb_h.status = CAM_REQ_CMP; 1135 break; 1136 } 1137 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 1138 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 1139 ata_reinit(dev); 1140 ccb->ccb_h.status = CAM_REQ_CMP; 1141 break; 1142 case XPT_TERM_IO: /* Terminate the I/O process */ 1143 /* XXX Implement */ 1144 ccb->ccb_h.status = CAM_REQ_INVALID; 1145 break; 1146 case XPT_PATH_INQ: /* Path routing inquiry */ 1147 { 1148 struct ccb_pathinq *cpi = &ccb->cpi; 1149 1150 parent = device_get_parent(dev); 1151 cpi->version_num = 1; /* XXX??? */ 1152 cpi->hba_inquiry = PI_SDTR_ABLE; 1153 cpi->target_sprt = 0; 1154 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 1155 cpi->hba_eng_cnt = 0; 1156 if (ch->flags & ATA_NO_SLAVE) 1157 cpi->max_target = 0; 1158 else 1159 cpi->max_target = 1; 1160 cpi->max_lun = 0; 1161 cpi->initiator_id = 0; 1162 cpi->bus_id = cam_sim_bus(sim); 1163 if (ch->flags & ATA_SATA) 1164 cpi->base_transfer_speed = 150000; 1165 else 1166 cpi->base_transfer_speed = 3300; 1167 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 1168 strlcpy(cpi->hba_vid, "ATA", HBA_IDLEN); 1169 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 1170 cpi->unit_number = cam_sim_unit(sim); 1171 if (ch->flags & ATA_SATA) 1172 cpi->transport = XPORT_SATA; 1173 else 1174 cpi->transport = XPORT_ATA; 1175 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 1176 cpi->protocol = PROTO_ATA; 1177 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 1178 cpi->maxio = ch->dma.max_iosize ? ch->dma.max_iosize : DFLTPHYS; 1179 if (device_get_devclass(device_get_parent(parent)) == 1180 devclass_find("pci")) { 1181 cpi->hba_vendor = pci_get_vendor(parent); 1182 cpi->hba_device = pci_get_device(parent); 1183 cpi->hba_subvendor = pci_get_subvendor(parent); 1184 cpi->hba_subdevice = pci_get_subdevice(parent); 1185 } 1186 cpi->ccb_h.status = CAM_REQ_CMP; 1187 break; 1188 } 1189 default: 1190 ccb->ccb_h.status = CAM_REQ_INVALID; 1191 break; 1192 } 1193 xpt_done(ccb); 1194 } 1195 1196 static void 1197 atapoll(struct cam_sim *sim) 1198 { 1199 struct ata_channel *ch = (struct ata_channel *)cam_sim_softc(sim); 1200 1201 ata_interrupt_locked(ch); 1202 } 1203 1204 /* 1205 * module handeling 1206 */ 1207 static int 1208 ata_module_event_handler(module_t mod, int what, void *arg) 1209 { 1210 1211 switch (what) { 1212 case MOD_LOAD: 1213 ata_devclass = devclass_find("ata"); 1214 return 0; 1215 1216 case MOD_UNLOAD: 1217 return 0; 1218 1219 default: 1220 return EOPNOTSUPP; 1221 } 1222 } 1223 1224 static moduledata_t ata_moduledata = { "ata", ata_module_event_handler, NULL }; 1225 DECLARE_MODULE(ata, ata_moduledata, SI_SUB_DRIVERS, SI_ORDER_ANY); 1226 MODULE_VERSION(ata, 1); 1227 MODULE_DEPEND(ata, cam, 1, 1, 1); 1228