1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 #define ASMC_MAXFANS 6 31 32 struct asmc_softc { 33 device_t sc_dev; 34 struct mtx sc_mtx; 35 int sc_nfan; 36 int sc_nkeys; 37 int16_t sms_rest_x; 38 int16_t sms_rest_y; 39 int16_t sms_rest_z; 40 struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1]; 41 struct sysctl_oid *sc_temp_tree; 42 struct sysctl_oid *sc_sms_tree; 43 struct sysctl_oid *sc_light_tree; 44 const struct asmc_model *sc_model; 45 int sc_rid_port; 46 int sc_rid_irq; 47 struct resource *sc_ioport; 48 struct resource *sc_irq; 49 void *sc_cookie; 50 int sc_sms_intrtype; 51 struct taskqueue *sc_sms_tq; 52 struct task sc_sms_task; 53 uint8_t sc_sms_intr_works; 54 }; 55 56 /* 57 * Data port. 58 */ 59 #define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00) 60 #define ASMC_DATAPORT_WRITE(sc, val) \ 61 bus_write_1(sc->sc_ioport, 0x00, val) 62 #define ASMC_STATUS_MASK 0x0f 63 64 /* 65 * Command port. 66 */ 67 #define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04) 68 #define ASMC_CMDPORT_WRITE(sc, val) \ 69 bus_write_1(sc->sc_ioport, 0x04, val) 70 #define ASMC_CMDREAD 0x10 71 #define ASMC_CMDWRITE 0x11 72 73 /* 74 * Interrupt port. 75 */ 76 #define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f) 77 78 /* Number of keys */ 79 #define ASMC_NKEYS "#KEY" /* RO; 4 bytes */ 80 81 /* 82 * Fan control via SMC. 83 */ 84 #define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */ 85 #define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */ 86 #define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */ 87 #define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */ 88 #define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */ 89 #define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */ 90 #define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */ 91 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */ 92 93 /* 94 * Sudden Motion Sensor (SMS). 95 */ 96 #define ASMC_SMS_INIT1 0xe0 97 #define ASMC_SMS_INIT2 0xf8 98 #define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */ 99 #define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */ 100 #define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */ 101 #define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */ 102 #define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */ 103 #define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */ 104 #define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */ 105 #define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */ 106 #define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */ 107 #define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */ 108 #define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */ 109 #define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */ 110 111 /* 112 * Light Sensor. 113 */ 114 #define ASMC_ALSL_INT2A 0x2a /* Ambient Light related Interrupt */ 115 116 /* 117 * Keyboard backlight. 118 */ 119 #define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */ 120 #define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */ 121 #define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */ 122 123 /* 124 * Clamshell. 125 */ 126 #define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */ 127 128 /* 129 * Interrupt keys. 130 */ 131 #define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */ 132 133 /* 134 * Temperatures. 135 * 136 * First for MacBook, second for MacBook Pro, third for Intel Mac Mini, 137 * fourth the Mac Pro 8-core and finally the MacBook Air. 138 * 139 */ 140 /* maximum array size for temperatures including the last NULL */ 141 #define ASMC_TEMP_MAX 80 142 #define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \ 143 "TM0P", NULL } 144 #define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \ 145 "northbridge2", "heatsink1", \ 146 "heatsink2", "memory", } 147 #define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \ 148 "Northbridge Point 1", \ 149 "Northbridge Point 2", "Heatsink 1", \ 150 "Heatsink 2", "Memory Bank A", } 151 152 #define ASMC_MB31_TEMPS { "TB0T", "TN0P", "Th0H", "Th1H", \ 153 "TM0P", NULL } 154 155 #define ASMC_MB31_TEMPNAMES { "enclosure", "northbridge1", \ 156 "heatsink1", "heatsink2", \ 157 "memory", } 158 159 #define ASMC_MB31_TEMPDESCS { "Enclosure Bottomside", \ 160 "Northbridge Point 1", \ 161 "Heatsink 1","Heatsink 2" \ 162 "Memory Bank A", } 163 164 #define ASMC_MB71_TEMPS { "TB0T", "TB1T", "TB2T", "TC0D", "TC0P", \ 165 "TH0P", "TN0D", "TN0P", "TN0S", "TN1D", \ 166 "TN1E", "TN1F", "TN1G", "TN1S", "Th1H", \ 167 "Ts0P", "Ts0S", NULL } 168 169 #define ASMC_MB71_TEMPNAMES { "enclosure_bottom0", "battery_1", "battery_2", "cpu_package", "cpu_proximity", \ 170 "hdd_bay", "northbridge0_diode", "northbridge0_proximity", "TN0S", "mpc_die2", \ 171 "TN1E", "TN1F", "TN1G", "TN1S", "heatsink1", \ 172 "palm_rest", "memory_proximity", } 173 174 #define ASMC_MB71_TEMPDESCS { "Enclosure Bottom 0", "Battery 1", "Battery 2", "CPU Package", "CPU Proximity", \ 175 "HDD Bay", "Northbridge Diode", "Northbridge Proximity", "TN0S", "MPC Die 2", \ 176 "TN1E", "TN1F", "TN1G", "TN1S", "Heatsink 1", \ 177 "Palm Rest", "Memory Proximity", } 178 179 #define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \ 180 "TG0H", "TG0P", "TG0T", NULL } 181 182 #define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \ 183 "heatsink2", "memory", "graphics", \ 184 "graphicssink", "unknown", } 185 186 #define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \ 187 "Heatsink 1", "Heatsink 2", \ 188 "Memory Controller", \ 189 "Graphics Chip", "Graphics Heatsink", \ 190 "Unknown", } 191 192 #define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \ 193 "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \ 194 "TTF0", "TW0P", NULL } 195 196 #define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \ 197 "heatsink3", "memory", "graphicssink", \ 198 "graphics", "cpu", "cpu2", "unknown1", \ 199 "unknown2", "wireless", } 200 201 #define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \ 202 "Main Heatsink 1", "Main Heatsink 2", \ 203 "Main Heatsink 3", \ 204 "Memory Controller", \ 205 "Graphics Chip Heatsink", \ 206 "Graphics Chip Diode", \ 207 "CPU Temperature Diode", "CPU Point 2", \ 208 "Unknown", "Unknown", \ 209 "Wireless Module", } 210 211 #define ASMC_MBP51_TEMPS { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", \ 212 "TC0F", "TC0P", "TG0D", "TG0F", "TG0H", \ 213 "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", \ 214 "TTF0", "Th2H", "Tm0P", "Ts0P", "Ts0S", \ 215 NULL } 216 217 #define ASMC_MBP51_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 218 "enclosure_bottom_2", "enclosure_bottom_3", \ 219 "cpu_diode", "cpu", \ 220 "cpu_pin", "gpu_diode", \ 221 "gpu", "gpu_heatsink", \ 222 "gpu_pin", "gpu_transistor", \ 223 "gpu_2_heatsink", "northbridge_diode", \ 224 "northbridge_pin", "unknown", \ 225 "heatsink_2", "memory_controller", \ 226 "pci_express_slot_pin", "pci_express_slot_unk" } 227 228 #define ASMC_MBP51_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 229 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 230 "CPU Diode", "CPU ???", \ 231 "CPU Pin", "GPU Diode", \ 232 "GPU ???", "GPU Heatsink", \ 233 "GPU Pin", "GPU Transistor", \ 234 "GPU 2 Heatsink", "Northbridge Diode", \ 235 "Northbridge Pin", "Unknown", \ 236 "Heatsink 2", "Memory Controller", \ 237 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 238 239 #define ASMC_MBP62_TEMPS { "TB0T", "TB1T", "TB2T", \ 240 "TC0C", "TC0D", "TC0P", \ 241 "TC1C", "TG0D", "TG0P", \ 242 "TG0T", "TMCD", "TP0P", \ 243 "TPCD", "Th1H", "Th2H", \ 244 "Tm0P", "Ts0P", "Ts0S" } 245 246 #define ASMC_MBP62_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 247 "enclosure_bottom_2", "cpu0", \ 248 "cpu_diode", "cpu_proximity", \ 249 "cpu1", "gpu_diode", \ 250 "gpu_pin", "gpu_transistor", \ 251 "TMCD", "pch_controller_proximity", \ 252 "pch_die", "heatsink1", \ 253 "heatsink2", "memory-controller", \ 254 "palmrest", "memoryproximity" } 255 256 #define ASMC_MBP62_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 257 "Enclosure Bottom 2", "CPU 0", \ 258 "CPU Diode", "CPU Proximity", \ 259 "CPU 1", "GPU Diode", \ 260 "GPU Pin", "GPU Transistor", \ 261 "TMCD", "PCH Controller Proximity", \ 262 "PCH Die", "Heat Sink 1", \ 263 "Heat Sink 2", "Memory Controller", \ 264 "Palm Rest", "Memory Proximity" } 265 266 #define ASMC_MBP55_TEMPS { "TB0T", "TB1T", \ 267 "TB2T", "TB3T", \ 268 "TC0D", "TC0P", \ 269 "TN0D", "TN0P", \ 270 "TTF0", \ 271 "Th0H", "Th1H", "ThFH", \ 272 "Ts0P", "Ts0S", \ 273 NULL } 274 275 #define ASMC_MBP55_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 276 "enclosure_bottom_2", "enclosure_bottom_3", \ 277 "cpu_diode", "cpu_pin", \ 278 "northbridge_diode", "northbridge_pin", \ 279 "unknown", \ 280 "heatsink_0", "heatsink_1", "heatsink_2", \ 281 "pci_express_slot_pin", "pci_express_slot_unk" } 282 283 #define ASMC_MBP55_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 284 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 285 "CPU Diode", "CPU Pin", \ 286 "Northbridge Diode", "Northbridge Pin", \ 287 "Unknown", \ 288 "Heatsink 0", "Heatsink 1", "Heatsink 2", \ 289 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 290 291 #define ASMC_MBP81_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 292 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 293 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 294 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 295 "Ts0S", NULL } 296 297 #define ASMC_MBP81_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 298 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 299 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 300 "TP0P", "TPCD", "wireless", "Th1H", "Ts0P", \ 301 "Ts0S" } 302 303 #define ASMC_MBP81_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 304 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 305 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 306 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 307 "Ts0S" } 308 309 #define ASMC_MBP82_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 310 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 311 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 312 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 313 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 314 "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL } 315 316 #define ASMC_MBP82_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 317 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 318 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 319 "TCTD", "graphics", "TG0P", "THSP", "TM0S", \ 320 "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \ 321 "Th2H", "memory", "Ts0P", "Ts0S" } 322 323 #define ASMC_MBP82_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 324 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 325 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 326 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 327 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 328 "Th2H", "Tm0P", "Ts0P", "Ts0S" } 329 330 #define ASMC_MBP91_TEMPS { "TA0P", "TB0T", "TB1T", "TB2T", "TC0E", \ 331 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 332 "TC4C", "TCGC", "TCSA", "TCXC", "TG0D", \ 333 "TG0P", "TG1D", "TG1F", "TG1d", "TGTC", \ 334 "TGTD", "TM0P", "TM0S", "TP0P", "TPCD", \ 335 "Th1H", "Th2H", "Ts0P", "Ts0S", "Tsqf", NULL } 336 337 #define ASMC_MBP91_TEMPNAMES { "ambient", "enclosure_bottom_1", "enclosure_bottom_2", \ 338 "enclosure_bottom_3", "cpu_die_peci_0", "cpu_die_peci_1", \ 339 "cpu_proximity", "cpu_core_1", "cpu_core_2", "cpu_core_3", \ 340 "cpu_core_4", "intel_gpu", "cpu_sys_agent", \ 341 "cpu_core_peci", "gpu_analog", \ 342 "gpu_proximity", "geforce_gpu_digital", "tg1f", \ 343 "gpu_2_die", "tgtc", "tgtd", "memory_proximity", \ 344 "mem_bank_a1", "platform_ctrl_hub", "pch_digital", \ 345 "main_heatsink_r", "main_heatsink_l", "palm_rest", \ 346 "bottom_skin", "tsqf" } 347 348 #define ASMC_MBP91_TEMPDESCS { "Ambient", "Enclosure Bottom 1", "Enclosure Bottom 2", \ 349 "Enclosure Bottom 3", "CPU Die PECI 0", "CPU Die PECI 1", \ 350 "CPU Proximity", "CPU Core 1", "CPU Core 2", \ 351 "CPU Core 3", "CPU Core 4", "Intel GPU", \ 352 "CPU System Agent Core", "CPU Core - PECI", \ 353 "GPU Die - Analog", "GPU Proximity", \ 354 "GeForce GPU Die - Digital", "TG1F", "GPU 2 Die" \ 355 "TGTC", "TGTD", "Memory Proximity", \ 356 "Memory Bank A1", "Platform Controller Hub", "PCH Die - Digital", \ 357 "Main Heatsink Right", "Main Heatsink Left", "Palm Rest", \ 358 "Bottom Skin", "Tsqf" } 359 360 #define ASMC_MBP92_TEMPS { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 361 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 362 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 363 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 364 "TPCD", NULL } 365 366 #define ASMC_MBP92_TEMPNAMES { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 367 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 368 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 369 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 370 "TPCD" } 371 372 #define ASMC_MBP92_TEMPDESCS { "Palm Rest", "Memory Proximity", "Airflow 1", \ 373 "Battery 1", "Battery 2", "Battery TS_MAX", \ 374 "CPU Core 1", "CPU Core 2", "CPU1", "CPU1", \ 375 "TC0J", "CPU 1 Proximity", "TCFC", \ 376 "PECI GPU", "PECI SA", "TCTD", "PECI CPU", \ 377 "GPU Die", "Memory Bank A1", "Memory Module A1", \ 378 "PCH Die" } 379 380 #define ASMC_MBP112_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 381 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 382 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 383 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 384 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 385 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 386 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 387 "Ts1S", NULL } 388 389 #define ASMC_MBP112_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 390 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 391 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 392 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 393 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 394 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 395 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 396 "Ts1S" } 397 398 #define ASMC_MBP112_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 399 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 400 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 401 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 402 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 403 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 404 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 405 "Ts1S" } 406 407 #define ASMC_MBP113_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 408 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 409 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 410 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 411 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 412 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 413 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 414 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 415 "Ts1S", NULL } 416 417 #define ASMC_MBP113_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 418 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 419 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 420 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 421 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 422 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 423 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 424 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 425 "Ts1S" } 426 427 #define ASMC_MBP113_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 428 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 429 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 430 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 431 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 432 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 433 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 434 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 435 "Ts1S" } 436 437 #define ASMC_MBP114_TEMPS { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 438 "IO3R", "IO5R", "IM0C", "IC1C", "IC2C", \ 439 "IC3C", "ILDC", "IBLC", "IAPC", "IHSC", \ 440 "ICMC", "TC0P", "TP0P", "TM0P", \ 441 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 442 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 443 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 444 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 445 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 446 "PCPG", "PCPT", "PSTR", "PDTR", NULL } 447 448 #define ASMC_MBP114_TEMPNAMES { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 449 "IO3R", "IO5R", "IM0C", "IC1C", "IC2C", \ 450 "IC3C", "ILDC", "IBLC", "IAPC", "IHSC", \ 451 "ICMC", "TC0P", "TP0P", "TM0P", \ 452 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 453 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 454 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 455 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 456 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 457 "PCPG", "PCPT", "PSTR", "PDTR" } 458 459 #define ASMC_MBP114_TEMPDESCS { "CPU High (CPU, I/O)", "DC In", "SSD", "Charger (BMON)", "CPU", \ 460 "Other 3.3V", "Other 5V", "Memory", "Platform Controller Hub Core", "CPU Load Current Monitor", \ 461 "CPU DDR", "LCD Panel", "LCD Backlight", "Airport", "Thunderbolt", \ 462 "S2", "CPU Proximity", "Platform Controller Hub", "Memory Proximity", "Air Flow Proximity", \ 463 "Left Fin Stack", "Right Fin Stack", "Airport Proximity", "Palm Rest", "Palm Rest Actuator", \ 464 "Battery Max", "Battery Sensor 1", "Battery Sensor 2", "SSD A", "SSD B", \ 465 "CPU Core 1", "CPU Core 2", "CPU Core 3", "CPU Core 4", "CPU PECI Die", \ 466 "Intel GPU", "Platform Controller Hub PECI", "CPU System Agent Core", "CPU VCore", "DC In", \ 467 "Pbus", "Ambient Light", "Leftside", "Rightside", "CPU Package Core", \ 468 "CPU Package GPU", "CPU Package Total", "System Total", "DC In" } 469 470 #define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL } 471 #define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" } 472 #define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \ 473 "Northbridge Point 2" } 474 475 #define ASMC_MM21_TEMPS { "TA0P", "TC0D", \ 476 "TC0H", "TC0P", \ 477 "TC1P", "TN0P", \ 478 "TN1P", NULL } 479 480 #define ASMC_MM21_TEMPNAMES { "ambient_air", "cpu_die", \ 481 "cpu_heatsink", "cpu_proximity1", \ 482 "cpu_proximity2", "northbridge_proximity1", \ 483 "northbridge_proximity2", } 484 485 #define ASMC_MM21_TEMPDESCS { "Ambient Air Temperature" \ 486 "CPU Die Core Temperature", \ 487 "CPU Heatsink Temperature", \ 488 "CPU Proximity 1 Temperature", \ 489 "CPU Proximity 2 Temperature", \ 490 "Northbridge Proximity 1 Temperature", \ 491 "Northbridge Proximity 2 Temperature", } 492 493 #define ASMC_MM31_TEMPS { "TC0D", "TC0H", \ 494 "TC0P", "TH0P", \ 495 "TN0D", "TN0P", \ 496 "TW0P", NULL } 497 498 #define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \ 499 "cpu0_proximity", "hdd_bay", \ 500 "northbridge_die", \ 501 "northbridge_proximity", \ 502 "wireless_proximity", } 503 504 #define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \ 505 "CPU0 Heatsink Temperature", \ 506 "CPU0 Proximity Temperature", \ 507 "HDD Bay Temperature", \ 508 "Northbridge Die Core Temperature", \ 509 "Northbridge Proximity Temperature", \ 510 "Wireless Module Proximity Temperature", } 511 512 #define ASMC_MM41_TEMPS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 513 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 514 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 515 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 516 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 517 "TW0P", "Tm0P", "Tp0C", NULL } 518 519 #define ASMC_MM41_TEMPNAMES { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 520 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 521 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 522 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 523 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 524 "TW0P", "Tm0P", "Tp0C", NULL } 525 526 #define ASMC_MM41_TEMPDESCS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 527 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 528 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 529 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 530 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 531 "TW0P", "Tm0P", "Tp0C", NULL } 532 533 #define ASMC_MM52_TEMPS { "TA0P", "TA1P", \ 534 "TC0D", "TC0P", \ 535 "TG0D", "TG1D", \ 536 "TG0P", "TG0M", \ 537 "TI0P", \ 538 "TM0S", "TMBS", \ 539 "TM0P", "TP0P", \ 540 "TPCD", "Tp0C", \ 541 "TW0P", NULL } 542 543 #define ASMC_MM52_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 544 "cpu_die", "cpu_proximity", \ 545 "gpu_diode1", "gpu_diode2", \ 546 "gpu_proximity", "gpu_integrated_switcher", \ 547 "thunderbolt_proximity", \ 548 "memory_slot1", "memory_slot2", \ 549 "memory_proximity", "pch_controller_proximity", \ 550 "pch_controller_die", "pwr_supply", \ 551 "wireless_proximity", } 552 553 #define ASMC_MM52_TEMPDESCS { "Ambient Air Proximity Temperature", \ 554 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 555 "CPU Die Temperature", "CPU Proximity Temperature", \ 556 "GPU Diode 1 Temperature" , "GPU Diode 2 Temperature", \ 557 "GPU Proximity Temperature", \ 558 "Integrated Graphics/GPU Switcher Temperature", \ 559 "Thunderbolt Proximity Temperature", \ 560 "Memory Slot 1 Temperature", \ 561 "Memory Slot 2 Temperature", \ 562 "Memory Slots Proximity Temperature", \ 563 "Platform Controller Hub Proximity Temperature", \ 564 "Platform Controller Hub Die Temperature", \ 565 "Power Supply Temperature", \ 566 "Wireless Module Proximity Temperature", } 567 568 #define ASMC_MM61_TEMPS { "TA0P", "TA1P", \ 569 "TC0D", "TC0G", "TC0P", "TCPG", \ 570 "TI0P", \ 571 "TM0S", "TMBS", "TM0P", \ 572 "TP0P", "TPCD", \ 573 "Tp0C", \ 574 "TW0P", NULL } 575 576 #define ASMC_MM61_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 577 "cpu_die", "TC0G", "cpu_proximity", "TCPG", \ 578 "thunderbolt_proximity", \ 579 "memory_slot1", "memory_slot2", "memory_proximity", \ 580 "pch_controller_proximity", "pch_controller_die", \ 581 "pwr_supply", \ 582 "wireless_proximity", NULL } 583 584 #define ASMC_MM61_TEMPDESCS { "Ambient Air Proximity Temperature", \ 585 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 586 "CPU Die Temperature", \ 587 NULL, \ 588 "CPU Proximity Temperature", \ 589 NULL, \ 590 "Thunderbolt Proximity Temperature", \ 591 "Memory Slot 1 Temperature", \ 592 "Memory Slot 2 Temperature", \ 593 "Memory Slots Proximity Temperature", \ 594 "Platform Controller Hub Proximity Temperature", \ 595 "Platform Controller Hub Die Temperature", \ 596 "Power Supply Temperature", \ 597 "Wireless Module Proximity Temperature", NULL } 598 599 #define ASMC_MM62_TEMPS { "TA0P", "TA1P", \ 600 "TC0D", "TC0G", "TC0P", "TCPG", \ 601 "TI0P", \ 602 "TM0S", "TMBS", "TM0P", \ 603 "TP0P", "TPCD", \ 604 "Tp0C", \ 605 "TW0P", NULL } 606 607 #define ASMC_MM62_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 608 "cpu_die", "TC0G", "cpu_proximity", "TCPG", \ 609 "thunderbolt_proximity", \ 610 "memory_slot1", "memory_slot2", "memory_proximity", \ 611 "pch_controller_proximity", "pch_controller_die", \ 612 "pwr_supply", \ 613 "wireless_proximity", NULL } 614 615 #define ASMC_MM62_TEMPDESCS { "Ambient Air Proximity Temperature", \ 616 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 617 "CPU Die Temperature", \ 618 NULL, \ 619 "CPU Proximity Temperature", \ 620 NULL, \ 621 "Thunderbolt Proximity Temperature", \ 622 "Memory Slot 1 Temperature", \ 623 "Memory Slot 2 Temperature", \ 624 "Memory Slots Proximity Temperature", \ 625 "Platform Controller Hub Proximity Temperature", \ 626 "Platform Controller Hub Die Temperature", \ 627 "Power Supply Temperature", \ 628 "Wireless Module Proximity Temperature", NULL } 629 630 #define ASMC_MM71_TEMPS { "TA0p", "TA1p", \ 631 "TA2p", "TC0c", \ 632 "TC0p", "TC1c", \ 633 "TCGc", "TCSc", \ 634 "TCXC", "TCXR", \ 635 "TM0p", "TPCd", \ 636 "TW0p", "Te0T", \ 637 "Tm0P", NULL } 638 639 #define ASMC_MM71_TEMPNAMES { "ambient_air1", "ambient_air2", \ 640 "ambient_air3", "cpu_core1_peci", \ 641 "cpu_proximity", "cpu_core2_peci", \ 642 "intel_gpu", "cpu_sa_core_peci", \ 643 "cpu_core", "cpu_peci_dts", \ 644 "memory_proximity", "pch_controller_die", \ 645 "wireless_proximity", "thunderbolt_diode", \ 646 "logic_board", } 647 648 #define ASMC_MM71_TEMPDESCS { "Ambient Air Temperature 1", \ 649 "Ambient Air Temperature 2", \ 650 "Ambient Air Temperature 3", \ 651 "CPU Core 1 PECI Temperature", "CPU Proximity Temperature", \ 652 "CPU Core 2 PECI Temperature", "Intel GPU Temperature", \ 653 "CPU System Agent Core PECI Temperature", \ 654 "CPU Core Temperature", "CPU PECI DTS Temperature", \ 655 "Memory Proximity Temperature", \ 656 "Platform Controller Hub Die Temperature", \ 657 "Wireless Module Proximity Temperature", \ 658 "Thunderbolt Diode Temperature", \ 659 "Logic Board temperature", } 660 661 #define ASMC_MP1_TEMPS { "TA0P", \ 662 "TCAH", "TCBH", \ 663 "TC0P", "TC0C", "TC1C", \ 664 "TC2C", "TC3C", "THTG", \ 665 "TH0P", "TH1P", \ 666 "TH2P", "TH3P", \ 667 "TM0P", "TM1P", "TM2P", \ 668 "TM8P", "TM9P", "TMAP", \ 669 "TM0S", "TM1S", "TM2P", "TM3S", \ 670 "TM8S", "TM9S", "TMAS", "TMBS", \ 671 "TN0H", "TS0C", \ 672 "Tp0C", "Tp1C", "Tv0S", "Tv1S", NULL } 673 674 #define ASMC_MP1_TEMPNAMES { "ambient", \ 675 "cpu_a_heatsink", "cpu_b_heatsink", \ 676 "cpu_a_proximity", "cpu_core0", "cpu_core1", \ 677 "cpu_core2", "cpu_core3", "THTG", \ 678 "hdd_bay0", "hdd_bay1", \ 679 "hdd_bay2", "hdd_bay3", \ 680 "memory_card_a_proximity0", \ 681 "memory_card_a_proximity1", \ 682 "memory_card_a_proximity2", \ 683 "memory_card_b_proximity0", \ 684 "memory_card_b_proximity1", \ 685 "memory_card_b_proximity2", \ 686 "memory_card_a_slot0", \ 687 "memory_card_a_slot1", \ 688 "memory_card_a_slot2", \ 689 "memory_card_a_slot3", \ 690 "memory_card_b_slot0", \ 691 "memory_card_b_slot1", \ 692 "memory_card_b_slot2", \ 693 "memory_card_b_slot3", \ 694 "mch_heatsink", "expansion_slots", \ 695 "power_supply_loc0", "power_supply_loc1", \ 696 "Tv0S", "Tv1S", } 697 698 #define ASMC_MP1_TEMPDESCS { "Ambient Air", \ 699 "CPU A Heatsink", "CPU B Heatsink", \ 700 "CPU A Proximity", \ 701 "CPU Core 1", "CPU Core 2", \ 702 "CPU Core 3", "CPU Core 4", "THTG", \ 703 "Hard Drive Bay 1", "Hard Drive Bay 2", \ 704 "Hard Drive Bay 3", "Hard Drive Bay 4", \ 705 "Memory Riser A, Proximity 1", \ 706 "Memory Riser A, Proximity 2", \ 707 "Memory Riser A, Proximity 3", \ 708 "Memory Riser B, Proximity 1", \ 709 "Memory Riser B, Proximity 2", \ 710 "Memory Riser B, Proximity 3", \ 711 "Memory Riser A, Slot 1", \ 712 "Memory Riser A, Slot 2", \ 713 "Memory Riser A, Slot 3", \ 714 "Memory Riser A, Slot 4", \ 715 "Memory Riser B, Slot 1", \ 716 "Memory Riser B, Slot 2", \ 717 "Memory Riser B, Slot 3", \ 718 "Memory Riser B, Slot 4", \ 719 "MCH Heatsink", "Expansion Slots", \ 720 "Power Supply, Location 1", \ 721 "Power Supply, Location 2", \ 722 "Tv0S", "Tv1S", } 723 724 #define ASMC_MP2_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 725 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 726 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 727 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 728 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 729 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 730 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \ 731 NULL } 732 733 #define ASMC_MP2_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 734 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 735 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 736 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 737 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 738 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 739 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 740 741 #define ASMC_MP2_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 742 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 743 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 744 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 745 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 746 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 747 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 748 749 #define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 750 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 751 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 752 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 753 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 754 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 755 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 756 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 757 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 758 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 759 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 760 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 761 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 762 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 763 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \ 764 NULL } 765 766 #define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \ 767 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 768 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 769 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 770 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 771 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 772 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 773 "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \ 774 "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \ 775 "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \ 776 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 777 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 778 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 779 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 780 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 781 782 #define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 783 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 784 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 785 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 786 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 787 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 788 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 789 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 790 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 791 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 792 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 793 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 794 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 795 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 796 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 797 798 #define ASMC_MP6_TEMPS { "TA0P", "TA1P", "TC0P", "TG0D", "TG0P", \ 799 "TG1D", "TG1P", "TM0P", "TM1P", NULL } 800 801 #define ASMC_MP6_TEMPNAMES { "ambient_air_1", "ambient_air_2", \ 802 "cpu_proximity", "gpu_diode_1", \ 803 "gpu_proximity_1", "gpu_diode_2", \ 804 "gpu_proximity_2", "mem_proximity_1", \ 805 "mem_proximity_2" } 806 807 #define ASMC_MP6_TEMPDESCS { "Ambient Air 1", "Ambient Air 2", \ 808 "CPU Proximity", "GPU Diode 1", \ 809 "GPU Proximity 1", "GPU Diode 2", \ 810 "GPU Proximity 2", "Memory Bank A", \ 811 "Memory Bank B" } 812 813 #define ASMC_MBA_TEMPS { "TB0T", NULL } 814 #define ASMC_MBA_TEMPNAMES { "enclosure" } 815 #define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" } 816 817 #define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \ 818 "TC0D", "TC0E", "TC0P", NULL } 819 820 #define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \ 821 "TC0D", "TC0E", "TC0P" } 822 823 #define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \ 824 "TC0D", "TC0E", "TC0P" } 825 826 #define ASMC_MBA4_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 827 "TC0D", "TC0E", "TC0F", "TC0P", \ 828 "TC1C", "TC2C", "TCGC", "TCSA", \ 829 "TH0F", "TH0J", "TH0O", "TH0o", \ 830 "TM0P", "TPCD", "Ta0P", "Th1H", \ 831 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 832 NULL } 833 834 #define ASMC_MBA4_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TC0C", \ 835 "TC0D", "TC0E", "TC0F", "TC0P", \ 836 "TC1C", "TC2C", "TCGC", "TCSA", \ 837 "TH0F", "TH0J", "TH0O", "TH0o", \ 838 "TM0P", "TPCD", "Ta0P", "Th1H", \ 839 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 840 NULL } 841 842 #define ASMC_MBA4_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TC0C", \ 843 "TC0D", "TC0E", "TC0F", "TC0P", \ 844 "TC1C", "TC2C", "TCGC", "TCSA", \ 845 "TH0F", "TH0J", "TH0O", "TH0o", \ 846 "TM0P", "TPCD", "Ta0P", "Th1H", \ 847 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 848 NULL } 849 850 #define ASMC_MBA5_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 851 "TC0D", "TC0E", "TC0F", "TC0P", \ 852 "TC1C", "TC2C", "TCGC", "TCSA", \ 853 "TCXC", "THSP", "TM0P", "TPCD", \ 854 "Ta0P", "Th1H", "Tm0P", "Tm1P", \ 855 "Ts0P", "Ts0S", NULL } 856 857 #define ASMC_MBA5_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", "TC0C", \ 858 "cpudiode", "cputemp1", "cputemp2", "cpuproximity", \ 859 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 860 "TCXC", "THSP", "memorybank", "pchdie", \ 861 "Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \ 862 "palmrest", "memoryproximity" } 863 864 #define ASMC_MBA5_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\ 865 "CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 866 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 867 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 868 "Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \ 869 "Palm Rest", "Memory Proximity" } 870 871 /* 872 * TODO: validate the temp zones for MBA 6.x ! 873 */ 874 #define ASMC_MBA6_TEMPS { "TB0T", "TB1T", "TB2T", \ 875 "TC0E", "TC0F", "TC0P", \ 876 "TC1C", "TC2C", "TCGC", "TCSA", \ 877 "TCXC", "THSP", "TM0P", "TPCD", \ 878 "Ta0P", "Th1H", "Tm0P", \ 879 "Ts0P", "Ts0S", NULL } 880 881 #define ASMC_MBA6_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \ 882 "cputemp1", "cputemp2", "cpuproximity", \ 883 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 884 "TCXC", "THSP", "memorybank", "pchdie", \ 885 "Ta0P", "heatpipe", "mainboardproximity1", \ 886 "palmrest", "memoryproximity" } 887 888 #define ASMC_MBA6_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \ 889 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 890 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 891 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 892 "Ta0P", "Heatpipe", "Mainboard Proximity 1", \ 893 "Palm Rest", "Memory Proximity" } 894 895 896 #define ASMC_MBA7_TEMPS { "TB0T", "TB1T", "TB2T", \ 897 "TC0E", "TC0F", "TC0P", \ 898 "TC1C", "TC2C", \ 899 "TCGC", "TCSA", "TCXC", \ 900 "THSP", "TM0P", "TPCD", \ 901 "TW0P" "Ta0P", "Th1H", \ 902 "Tm0P", "Ts0P", "Ts0S", NULL } 903 904 #define ASMC_MBA7_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \ 905 "cputemp1", "cputemp2", "cpuproximity", \ 906 "cpucore1", "cpucore2", \ 907 "pecigpu", "pecisa", "pecicpu", \ 908 "thunderboltproximity", "memorybank", "pchdie", \ 909 "wirelessproximity", "airflowproximity", "heatpipe", \ 910 "mainboardproximity", "palmrest", "memoryproximity" } 911 912 #define ASMC_MBA7_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \ 913 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 914 "CPU Core 1", "CPU Core 2", \ 915 "PECI GPU", "PECI SA", "PECI CPU", \ 916 "Thunderbolt Proximity", "Memory Bank A", "PCH Die", \ 917 "Wireless Proximity", "Airflow Proxmity", "Heatpipe", \ 918 "Mainboard Proximity", "Palm Rest", "Memory Proximity" } 919