1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 #define ASMC_MAXFANS 6 31 32 struct asmc_softc { 33 device_t sc_dev; 34 struct mtx sc_mtx; 35 int sc_nfan; 36 int sc_nkeys; 37 int16_t sms_rest_x; 38 int16_t sms_rest_y; 39 int16_t sms_rest_z; 40 struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1]; 41 struct sysctl_oid *sc_temp_tree; 42 struct sysctl_oid *sc_sms_tree; 43 struct sysctl_oid *sc_light_tree; 44 const struct asmc_model *sc_model; 45 int sc_rid_port; 46 int sc_rid_irq; 47 struct resource *sc_ioport; 48 struct resource *sc_irq; 49 void *sc_cookie; 50 int sc_sms_intrtype; 51 struct taskqueue *sc_sms_tq; 52 struct task sc_sms_task; 53 uint8_t sc_sms_intr_works; 54 }; 55 56 /* 57 * Data port. 58 */ 59 #define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00) 60 #define ASMC_DATAPORT_WRITE(sc, val) \ 61 bus_write_1(sc->sc_ioport, 0x00, val) 62 #define ASMC_STATUS_MASK 0x0f 63 64 /* 65 * Command port. 66 */ 67 #define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04) 68 #define ASMC_CMDPORT_WRITE(sc, val) \ 69 bus_write_1(sc->sc_ioport, 0x04, val) 70 #define ASMC_CMDREAD 0x10 71 #define ASMC_CMDWRITE 0x11 72 73 /* 74 * Interrupt port. 75 */ 76 #define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f) 77 78 /* Number of keys */ 79 #define ASMC_NKEYS "#KEY" /* RO; 4 bytes */ 80 81 /* Query the ASMC revision */ 82 #define ASMC_KEY_REV "REV " /* RO: 6 bytes */ 83 84 /* 85 * Fan control via SMC. 86 */ 87 #define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */ 88 #define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */ 89 #define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */ 90 #define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */ 91 #define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */ 92 #define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */ 93 #define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */ 94 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */ 95 96 /* 97 * Sudden Motion Sensor (SMS). 98 */ 99 #define ASMC_SMS_INIT1 0xe0 100 #define ASMC_SMS_INIT2 0xf8 101 #define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */ 102 #define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */ 103 #define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */ 104 #define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */ 105 #define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */ 106 #define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */ 107 #define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */ 108 #define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */ 109 #define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */ 110 #define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */ 111 #define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */ 112 #define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */ 113 114 /* 115 * Light Sensor. 116 */ 117 #define ASMC_ALSL_INT2A 0x2a /* Ambient Light related Interrupt */ 118 119 /* 120 * Keyboard backlight. 121 */ 122 #define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */ 123 #define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */ 124 #define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */ 125 126 /* 127 * Clamshell. 128 */ 129 #define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */ 130 131 /* 132 * Auto power on / Wake-on-LAN. 133 */ 134 #define ASMC_KEY_AUPO "AUPO" /* RW; 1 byte */ 135 136 /* 137 * Interrupt keys. 138 */ 139 #define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */ 140 141 /* 142 * Temperatures. 143 * 144 * First for MacBook, second for MacBook Pro, third for Intel Mac Mini, 145 * fourth the Mac Pro 8-core and finally the MacBook Air. 146 * 147 */ 148 /* maximum array size for temperatures including the last NULL */ 149 #define ASMC_TEMP_MAX 80 150 #define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \ 151 "TM0P", NULL } 152 #define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \ 153 "northbridge2", "heatsink1", \ 154 "heatsink2", "memory", } 155 #define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \ 156 "Northbridge Point 1", \ 157 "Northbridge Point 2", "Heatsink 1", \ 158 "Heatsink 2", "Memory Bank A", } 159 160 #define ASMC_MB31_TEMPS { "TB0T", "TN0P", "Th0H", "Th1H", \ 161 "TM0P", NULL } 162 163 #define ASMC_MB31_TEMPNAMES { "enclosure", "northbridge1", \ 164 "heatsink1", "heatsink2", \ 165 "memory", } 166 167 #define ASMC_MB31_TEMPDESCS { "Enclosure Bottomside", \ 168 "Northbridge Point 1", \ 169 "Heatsink 1","Heatsink 2" \ 170 "Memory Bank A", } 171 172 #define ASMC_MB71_TEMPS { "TB0T", "TB1T", "TB2T", "TC0D", "TC0P", \ 173 "TH0P", "TN0D", "TN0P", "TN0S", "TN1D", \ 174 "TN1E", "TN1F", "TN1G", "TN1S", "Th1H", \ 175 "Ts0P", "Ts0S", NULL } 176 177 #define ASMC_MB71_TEMPNAMES { "enclosure_bottom0", "battery_1", "battery_2", "cpu_package", "cpu_proximity", \ 178 "hdd_bay", "northbridge0_diode", "northbridge0_proximity", "TN0S", "mpc_die2", \ 179 "TN1E", "TN1F", "TN1G", "TN1S", "heatsink1", \ 180 "palm_rest", "memory_proximity", } 181 182 #define ASMC_MB71_TEMPDESCS { "Enclosure Bottom 0", "Battery 1", "Battery 2", "CPU Package", "CPU Proximity", \ 183 "HDD Bay", "Northbridge Diode", "Northbridge Proximity", "TN0S", "MPC Die 2", \ 184 "TN1E", "TN1F", "TN1G", "TN1S", "Heatsink 1", \ 185 "Palm Rest", "Memory Proximity", } 186 187 #define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \ 188 "TG0H", "TG0P", "TG0T", NULL } 189 190 #define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \ 191 "heatsink2", "memory", "graphics", \ 192 "graphicssink", "unknown", } 193 194 #define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \ 195 "Heatsink 1", "Heatsink 2", \ 196 "Memory Controller", \ 197 "Graphics Chip", "Graphics Heatsink", \ 198 "Unknown", } 199 200 #define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \ 201 "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \ 202 "TTF0", "TW0P", NULL } 203 204 #define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \ 205 "heatsink3", "memory", "graphicssink", \ 206 "graphics", "cpu", "cpu2", "unknown1", \ 207 "unknown2", "wireless", } 208 209 #define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \ 210 "Main Heatsink 1", "Main Heatsink 2", \ 211 "Main Heatsink 3", \ 212 "Memory Controller", \ 213 "Graphics Chip Heatsink", \ 214 "Graphics Chip Diode", \ 215 "CPU Temperature Diode", "CPU Point 2", \ 216 "Unknown", "Unknown", \ 217 "Wireless Module", } 218 219 #define ASMC_MBP51_TEMPS { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", \ 220 "TC0F", "TC0P", "TG0D", "TG0F", "TG0H", \ 221 "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", \ 222 "TTF0", "Th2H", "Tm0P", "Ts0P", "Ts0S", \ 223 NULL } 224 225 #define ASMC_MBP51_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 226 "enclosure_bottom_2", "enclosure_bottom_3", \ 227 "cpu_diode", "cpu", \ 228 "cpu_pin", "gpu_diode", \ 229 "gpu", "gpu_heatsink", \ 230 "gpu_pin", "gpu_transistor", \ 231 "gpu_2_heatsink", "northbridge_diode", \ 232 "northbridge_pin", "unknown", \ 233 "heatsink_2", "memory_controller", \ 234 "pci_express_slot_pin", "pci_express_slot_unk" } 235 236 #define ASMC_MBP51_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 237 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 238 "CPU Diode", "CPU ???", \ 239 "CPU Pin", "GPU Diode", \ 240 "GPU ???", "GPU Heatsink", \ 241 "GPU Pin", "GPU Transistor", \ 242 "GPU 2 Heatsink", "Northbridge Diode", \ 243 "Northbridge Pin", "Unknown", \ 244 "Heatsink 2", "Memory Controller", \ 245 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 246 247 #define ASMC_MBP62_TEMPS { "TB0T", "TB1T", "TB2T", \ 248 "TC0C", "TC0D", "TC0P", \ 249 "TC1C", "TG0D", "TG0P", \ 250 "TG0T", "TMCD", "TP0P", \ 251 "TPCD", "Th1H", "Th2H", \ 252 "Tm0P", "Ts0P", "Ts0S" } 253 254 #define ASMC_MBP62_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 255 "enclosure_bottom_2", "cpu0", \ 256 "cpu_diode", "cpu_proximity", \ 257 "cpu1", "gpu_diode", \ 258 "gpu_pin", "gpu_transistor", \ 259 "TMCD", "pch_controller_proximity", \ 260 "pch_die", "heatsink1", \ 261 "heatsink2", "memory-controller", \ 262 "palmrest", "memoryproximity" } 263 264 #define ASMC_MBP62_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 265 "Enclosure Bottom 2", "CPU 0", \ 266 "CPU Diode", "CPU Proximity", \ 267 "CPU 1", "GPU Diode", \ 268 "GPU Pin", "GPU Transistor", \ 269 "TMCD", "PCH Controller Proximity", \ 270 "PCH Die", "Heat Sink 1", \ 271 "Heat Sink 2", "Memory Controller", \ 272 "Palm Rest", "Memory Proximity" } 273 274 #define ASMC_MBP55_TEMPS { "TB0T", "TB1T", \ 275 "TB2T", "TB3T", \ 276 "TC0D", "TC0P", \ 277 "TN0D", "TN0P", \ 278 "TTF0", \ 279 "Th0H", "Th1H", "ThFH", \ 280 "Ts0P", "Ts0S", \ 281 NULL } 282 283 #define ASMC_MBP55_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 284 "enclosure_bottom_2", "enclosure_bottom_3", \ 285 "cpu_diode", "cpu_pin", \ 286 "northbridge_diode", "northbridge_pin", \ 287 "unknown", \ 288 "heatsink_0", "heatsink_1", "heatsink_2", \ 289 "pci_express_slot_pin", "pci_express_slot_unk" } 290 291 #define ASMC_MBP55_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 292 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 293 "CPU Diode", "CPU Pin", \ 294 "Northbridge Diode", "Northbridge Pin", \ 295 "Unknown", \ 296 "Heatsink 0", "Heatsink 1", "Heatsink 2", \ 297 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 298 299 #define ASMC_MBP81_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 300 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 301 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 302 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 303 "Ts0S", NULL } 304 305 #define ASMC_MBP81_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 306 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 307 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 308 "TP0P", "TPCD", "wireless", "Th1H", "Ts0P", \ 309 "Ts0S" } 310 311 #define ASMC_MBP81_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 312 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 313 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 314 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 315 "Ts0S" } 316 317 #define ASMC_MBP82_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 318 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 319 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 320 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 321 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 322 "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL } 323 324 #define ASMC_MBP82_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 325 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 326 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 327 "TCTD", "graphics", "TG0P", "THSP", "TM0S", \ 328 "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \ 329 "Th2H", "memory", "Ts0P", "Ts0S" } 330 331 #define ASMC_MBP82_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 332 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 333 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 334 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 335 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 336 "Th2H", "Tm0P", "Ts0P", "Ts0S" } 337 338 #define ASMC_MBP83_TEMPS { "ALSL", "F0Ac", "F1Ac", "IB0R", "IC0R", \ 339 "ID0R", "IG0R", "IO0R", "PCPC", "PCPG", \ 340 "PCPT", "PD0R", "TB1T", "TB2T", "TC0C", \ 341 "TC0D", "TC0P", "TC1C", "TC2C", "TC3C", \ 342 "TC4C", "TG0D", "TG0P", "THSP", "TP0P", \ 343 "TPCD", "Th1H", "Th2H", "Tm0P", "Ts0P", \ 344 "VC0C", "VD0R", "VG0C", "VN0C", "VP0R", NULL } 345 346 #define ASMC_MBP83_TEMPNAMES { "ambient_light", "fan_leftside", "fan_rightside", \ 347 "battery_current", "cpu_vcorevtt", "dc_current", \ 348 "gpu_voltage", "other", "cpu_package_core", \ 349 "cpu_package_gpu", "cpu_package_total", "dc_in", \ 350 "battery_1", "battery_2", "cpu_die_digital", \ 351 "cpu_die_analog", "cpu_proximity", "cpu_core_1", \ 352 "cpu_core_2", "cpu_core_3", "cpu_core_4", "gpu_die_analog", \ 353 "gpu_proximity", "thunderbolt", "platform_controller", \ 354 "pch_die_digital", "right_fin_stack", "left_fin_stack", \ 355 "dc_in_air_flow", "palm_rest", "cpu_vcore", "dc_in_voltage", \ 356 "gpu_vcore", "intel_gpu_vcore", "pbus_voltage" } 357 358 #define ASMC_MBP83_TEMPDESCS { "Ambient Light", "Fan Leftside", "Fan Rightside", \ 359 "Battery BMON Current", "CPU VcoreVTT", "DC In AMON Current", \ 360 "GPU Voltage", "Other 5V 3V", "CPU Package Core", \ 361 "CPU Package GPU", "CPU Package Total", "DC In", \ 362 "Battery Sensor 1", "Battery Sensor 2", "CPU Die Digital", \ 363 "CPU Die Analog", "CPU Proximity", "CPU Core 1 DTS", \ 364 "CPU Core 2 DTS", "CPU Core 3 DTS", "CPU Core 4 DTS", \ 365 "GPU Die Analog", "GPU Proximity", "Thunderbolt Proximity", \ 366 "Platform Controller Hub", "PCH Die Digital", \ 367 "Right Fin Stack Proximity", "Left Fin Stack Proximity", \ 368 "DC In Proximity Air Flow", "Palm Rest", "CPU VCore", \ 369 "DC In Voltage", "GPU VCore", "Intel GPU VCore", "PBus Voltage" } 370 371 #define ASMC_MBP91_TEMPS { "TA0P", "TB0T", "TB1T", "TB2T", "TC0E", \ 372 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 373 "TC4C", "TCGC", "TCSA", "TCXC", "TG0D", \ 374 "TG0P", "TG1D", "TG1F", "TG1d", "TGTC", \ 375 "TGTD", "TM0P", "TM0S", "TP0P", "TPCD", \ 376 "Th1H", "Th2H", "Ts0P", "Ts0S", "Tsqf", NULL } 377 378 #define ASMC_MBP91_TEMPNAMES { "ambient", "enclosure_bottom_1", "enclosure_bottom_2", \ 379 "enclosure_bottom_3", "cpu_die_peci_0", "cpu_die_peci_1", \ 380 "cpu_proximity", "cpu_core_1", "cpu_core_2", "cpu_core_3", \ 381 "cpu_core_4", "intel_gpu", "cpu_sys_agent", \ 382 "cpu_core_peci", "gpu_analog", \ 383 "gpu_proximity", "geforce_gpu_digital", "tg1f", \ 384 "gpu_2_die", "tgtc", "tgtd", "memory_proximity", \ 385 "mem_bank_a1", "platform_ctrl_hub", "pch_digital", \ 386 "main_heatsink_r", "main_heatsink_l", "palm_rest", \ 387 "bottom_skin", "tsqf" } 388 389 #define ASMC_MBP91_TEMPDESCS { "Ambient", "Enclosure Bottom 1", "Enclosure Bottom 2", \ 390 "Enclosure Bottom 3", "CPU Die PECI 0", "CPU Die PECI 1", \ 391 "CPU Proximity", "CPU Core 1", "CPU Core 2", \ 392 "CPU Core 3", "CPU Core 4", "Intel GPU", \ 393 "CPU System Agent Core", "CPU Core - PECI", \ 394 "GPU Die - Analog", "GPU Proximity", \ 395 "GeForce GPU Die - Digital", "TG1F", "GPU 2 Die" \ 396 "TGTC", "TGTD", "Memory Proximity", \ 397 "Memory Bank A1", "Platform Controller Hub", "PCH Die - Digital", \ 398 "Main Heatsink Right", "Main Heatsink Left", "Palm Rest", \ 399 "Bottom Skin", "Tsqf" } 400 401 #define ASMC_MBP92_TEMPS { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 402 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 403 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 404 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 405 "TPCD", NULL } 406 407 #define ASMC_MBP92_TEMPNAMES { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 408 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 409 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 410 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 411 "TPCD" } 412 413 #define ASMC_MBP92_TEMPDESCS { "Palm Rest", "Memory Proximity", "Airflow 1", \ 414 "Battery 1", "Battery 2", "Battery TS_MAX", \ 415 "CPU Core 1", "CPU Core 2", "CPU1", "CPU1", \ 416 "TC0J", "CPU 1 Proximity", "TCFC", \ 417 "PECI GPU", "PECI SA", "TCTD", "PECI CPU", \ 418 "GPU Die", "Memory Bank A1", "Memory Module A1", \ 419 "PCH Die" } 420 421 #define ASMC_MBP112_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 422 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 423 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 424 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 425 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 426 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 427 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 428 "Ts1S", NULL } 429 430 #define ASMC_MBP112_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 431 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 432 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 433 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 434 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 435 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 436 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 437 "Ts1S" } 438 439 #define ASMC_MBP112_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 440 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 441 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 442 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 443 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 444 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 445 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 446 "Ts1S" } 447 448 #define ASMC_MBP113_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 449 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 450 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 451 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 452 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 453 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 454 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 455 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 456 "Ts1S", NULL } 457 458 #define ASMC_MBP113_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 459 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 460 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 461 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 462 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 463 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 464 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 465 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 466 "Ts1S" } 467 468 #define ASMC_MBP113_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 469 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 470 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 471 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 472 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 473 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 474 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 475 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 476 "Ts1S" } 477 478 #define ASMC_MBP114_TEMPS { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 479 "IO3R", "IO5R", "IM0C", "IC1C", "IC2C", \ 480 "IC3C", "ILDC", "IBLC", "IAPC", "IHSC", \ 481 "ICMC", "TC0P", "TP0P", "TM0P", \ 482 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 483 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 484 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 485 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 486 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 487 "PCPG", "PCPT", "PSTR", "PDTR", NULL } 488 489 #define ASMC_MBP114_TEMPNAMES { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 490 "IO3R", "IO5R", "IM0C", "IC1C", "IC2C", \ 491 "IC3C", "ILDC", "IBLC", "IAPC", "IHSC", \ 492 "ICMC", "TC0P", "TP0P", "TM0P", \ 493 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 494 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 495 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 496 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 497 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 498 "PCPG", "PCPT", "PSTR", "PDTR" } 499 500 #define ASMC_MBP114_TEMPDESCS { "CPU High (CPU, I/O)", "DC In", "SSD", "Charger (BMON)", "CPU", \ 501 "Other 3.3V", "Other 5V", "Memory", "Platform Controller Hub Core", "CPU Load Current Monitor", \ 502 "CPU DDR", "LCD Panel", "LCD Backlight", "Airport", "Thunderbolt", \ 503 "S2", "CPU Proximity", "Platform Controller Hub", "Memory Proximity", "Air Flow Proximity", \ 504 "Left Fin Stack", "Right Fin Stack", "Airport Proximity", "Palm Rest", "Palm Rest Actuator", \ 505 "Battery Max", "Battery Sensor 1", "Battery Sensor 2", "SSD A", "SSD B", \ 506 "CPU Core 1", "CPU Core 2", "CPU Core 3", "CPU Core 4", "CPU PECI Die", \ 507 "Intel GPU", "Platform Controller Hub PECI", "CPU System Agent Core", "CPU VCore", "DC In", \ 508 "Pbus", "Ambient Light", "Leftside", "Rightside", "CPU Package Core", \ 509 "CPU Package GPU", "CPU Package Total", "System Total", "DC In" } 510 511 /* MacBookPro11,5 - same as 11,4 but without IBLC, ICMC, and IC2C keys */ 512 #define ASMC_MBP115_TEMPS { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 513 "IO3R", "IO5R", "IM0C", "IC1C", \ 514 "IC3C", "ILDC", "IAPC", "IHSC", \ 515 "TC0P", "TP0P", "TM0P", \ 516 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 517 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 518 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 519 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 520 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 521 "PCPG", "PCPT", "PSTR", "PDTR", NULL } 522 523 524 #define ASMC_MBP115_TEMPNAMES { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 525 "IO3R", "IO5R", "IM0C", "IC1C", \ 526 "IC3C", "ILDC", "IAPC", "IHSC", \ 527 "TC0P", "TP0P", "TM0P", \ 528 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 529 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 530 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 531 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 532 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 533 "PCPG", "PCPT", "PSTR", "PDTR" } 534 535 #define ASMC_MBP115_TEMPDESCS { "CPU High (CPU, I/O)", "DC In", "SSD", "Charger (BMON)", "CPU", \ 536 "Other 3.3V", "Other 5V", "Memory", "Platform Controller Hub Core", \ 537 "CPU DDR", "LCD Panel", "Airport", "Thunderbolt", \ 538 "CPU Proximity", "Platform Controller Hub", "Memory Proximity", "Air Flow Proximity", \ 539 "Left Fin Stack", "Right Fin Stack", "Airport Proximity", "Palm Rest", "Palm Rest Actuator", \ 540 "Battery Max", "Battery Sensor 1", "Battery Sensor 2", "SSD A", "SSD B", \ 541 "CPU Core 1", "CPU Core 2", "CPU Core 3", "CPU Core 4", "CPU PECI Die", \ 542 "Intel GPU", "Platform Controller Hub PECI", "CPU System Agent Core", "CPU VCore", "DC In", \ 543 "Pbus", "Ambient Light", "Leftside", "Rightside", "CPU Package Core", \ 544 "CPU Package GPU", "CPU Package Total", "System Total", "DC In" } 545 546 #define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL } 547 #define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" } 548 #define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \ 549 "Northbridge Point 2" } 550 551 #define ASMC_MM21_TEMPS { "TA0P", "TC0D", \ 552 "TC0H", "TC0P", \ 553 "TC1P", "TN0P", \ 554 "TN1P", NULL } 555 556 #define ASMC_MM21_TEMPNAMES { "ambient_air", "cpu_die", \ 557 "cpu_heatsink", "cpu_proximity1", \ 558 "cpu_proximity2", "northbridge_proximity1", \ 559 "northbridge_proximity2", } 560 561 #define ASMC_MM21_TEMPDESCS { "Ambient Air Temperature" \ 562 "CPU Die Core Temperature", \ 563 "CPU Heatsink Temperature", \ 564 "CPU Proximity 1 Temperature", \ 565 "CPU Proximity 2 Temperature", \ 566 "Northbridge Proximity 1 Temperature", \ 567 "Northbridge Proximity 2 Temperature", } 568 569 #define ASMC_MM31_TEMPS { "TC0D", "TC0H", \ 570 "TC0P", "TH0P", \ 571 "TN0D", "TN0P", \ 572 "TW0P", NULL } 573 574 #define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \ 575 "cpu0_proximity", "hdd_bay", \ 576 "northbridge_die", \ 577 "northbridge_proximity", \ 578 "wireless_proximity", } 579 580 #define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \ 581 "CPU0 Heatsink Temperature", \ 582 "CPU0 Proximity Temperature", \ 583 "HDD Bay Temperature", \ 584 "Northbridge Die Core Temperature", \ 585 "Northbridge Proximity Temperature", \ 586 "Wireless Module Proximity Temperature", } 587 588 #define ASMC_MM41_TEMPS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 589 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 590 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 591 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 592 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 593 "TW0P", "Tm0P", "Tp0C", NULL } 594 595 #define ASMC_MM41_TEMPNAMES { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 596 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 597 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 598 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 599 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 600 "TW0P", "Tm0P", "Tp0C", NULL } 601 602 #define ASMC_MM41_TEMPDESCS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 603 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 604 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 605 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 606 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 607 "TW0P", "Tm0P", "Tp0C", NULL } 608 609 #define ASMC_MM52_TEMPS { "TA0P", "TA1P", \ 610 "TC0D", "TC0P", \ 611 "TG0D", "TG1D", \ 612 "TG0P", "TG0M", \ 613 "TI0P", \ 614 "TM0S", "TMBS", \ 615 "TM0P", "TP0P", \ 616 "TPCD", "Tp0C", \ 617 "TW0P", NULL } 618 619 #define ASMC_MM52_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 620 "cpu_die", "cpu_proximity", \ 621 "gpu_diode1", "gpu_diode2", \ 622 "gpu_proximity", "gpu_integrated_switcher", \ 623 "thunderbolt_proximity", \ 624 "memory_slot1", "memory_slot2", \ 625 "memory_proximity", "pch_controller_proximity", \ 626 "pch_controller_die", "pwr_supply", \ 627 "wireless_proximity", } 628 629 #define ASMC_MM52_TEMPDESCS { "Ambient Air Proximity Temperature", \ 630 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 631 "CPU Die Temperature", "CPU Proximity Temperature", \ 632 "GPU Diode 1 Temperature" , "GPU Diode 2 Temperature", \ 633 "GPU Proximity Temperature", \ 634 "Integrated Graphics/GPU Switcher Temperature", \ 635 "Thunderbolt Proximity Temperature", \ 636 "Memory Slot 1 Temperature", \ 637 "Memory Slot 2 Temperature", \ 638 "Memory Slots Proximity Temperature", \ 639 "Platform Controller Hub Proximity Temperature", \ 640 "Platform Controller Hub Die Temperature", \ 641 "Power Supply Temperature", \ 642 "Wireless Module Proximity Temperature", } 643 644 #define ASMC_MM61_TEMPS { "TA0P", "TA1P", \ 645 "TC0D", "TC0G", "TC0P", "TCPG", \ 646 "TI0P", \ 647 "TM0S", "TMBS", "TM0P", \ 648 "TP0P", "TPCD", \ 649 "Tp0C", \ 650 "TW0P", NULL } 651 652 #define ASMC_MM61_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 653 "cpu_die", "TC0G", "cpu_proximity", "TCPG", \ 654 "thunderbolt_proximity", \ 655 "memory_slot1", "memory_slot2", "memory_proximity", \ 656 "pch_controller_proximity", "pch_controller_die", \ 657 "pwr_supply", \ 658 "wireless_proximity", NULL } 659 660 #define ASMC_MM61_TEMPDESCS { "Ambient Air Proximity Temperature", \ 661 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 662 "CPU Die Temperature", \ 663 NULL, \ 664 "CPU Proximity Temperature", \ 665 NULL, \ 666 "Thunderbolt Proximity Temperature", \ 667 "Memory Slot 1 Temperature", \ 668 "Memory Slot 2 Temperature", \ 669 "Memory Slots Proximity Temperature", \ 670 "Platform Controller Hub Proximity Temperature", \ 671 "Platform Controller Hub Die Temperature", \ 672 "Power Supply Temperature", \ 673 "Wireless Module Proximity Temperature", NULL } 674 675 #define ASMC_MM62_TEMPS { "TA0P", "TA1P", \ 676 "TC0D", "TC0G", "TC0P", "TCPG", \ 677 "TI0P", \ 678 "TM0S", "TMBS", "TM0P", \ 679 "TP0P", "TPCD", \ 680 "Tp0C", \ 681 "TW0P", NULL } 682 683 #define ASMC_MM62_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 684 "cpu_die", "TC0G", "cpu_proximity", "TCPG", \ 685 "thunderbolt_proximity", \ 686 "memory_slot1", "memory_slot2", "memory_proximity", \ 687 "pch_controller_proximity", "pch_controller_die", \ 688 "pwr_supply", \ 689 "wireless_proximity", NULL } 690 691 #define ASMC_MM62_TEMPDESCS { "Ambient Air Proximity Temperature", \ 692 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 693 "CPU Die Temperature", \ 694 NULL, \ 695 "CPU Proximity Temperature", \ 696 NULL, \ 697 "Thunderbolt Proximity Temperature", \ 698 "Memory Slot 1 Temperature", \ 699 "Memory Slot 2 Temperature", \ 700 "Memory Slots Proximity Temperature", \ 701 "Platform Controller Hub Proximity Temperature", \ 702 "Platform Controller Hub Die Temperature", \ 703 "Power Supply Temperature", \ 704 "Wireless Module Proximity Temperature", NULL } 705 706 #define ASMC_MM71_TEMPS { "TA0p", "TA1p", \ 707 "TA2p", "TC0c", \ 708 "TC0p", "TC1c", \ 709 "TCGc", "TCSc", \ 710 "TCXC", "TCXR", \ 711 "TM0p", "TPCd", \ 712 "TW0p", "Te0T", \ 713 "Tm0P", NULL } 714 715 #define ASMC_MM71_TEMPNAMES { "ambient_air1", "ambient_air2", \ 716 "ambient_air3", "cpu_core1_peci", \ 717 "cpu_proximity", "cpu_core2_peci", \ 718 "intel_gpu", "cpu_sa_core_peci", \ 719 "cpu_core", "cpu_peci_dts", \ 720 "memory_proximity", "pch_controller_die", \ 721 "wireless_proximity", "thunderbolt_diode", \ 722 "logic_board", } 723 724 #define ASMC_MM71_TEMPDESCS { "Ambient Air Temperature 1", \ 725 "Ambient Air Temperature 2", \ 726 "Ambient Air Temperature 3", \ 727 "CPU Core 1 PECI Temperature", "CPU Proximity Temperature", \ 728 "CPU Core 2 PECI Temperature", "Intel GPU Temperature", \ 729 "CPU System Agent Core PECI Temperature", \ 730 "CPU Core Temperature", "CPU PECI DTS Temperature", \ 731 "Memory Proximity Temperature", \ 732 "Platform Controller Hub Die Temperature", \ 733 "Wireless Module Proximity Temperature", \ 734 "Thunderbolt Diode Temperature", \ 735 "Logic Board temperature", } 736 737 #define ASMC_MP1_TEMPS { "TA0P", \ 738 "TCAH", "TCBH", \ 739 "TC0P", "TC0C", "TC1C", \ 740 "TC2C", "TC3C", "THTG", \ 741 "TH0P", "TH1P", \ 742 "TH2P", "TH3P", \ 743 "TM0P", "TM1P", "TM2P", \ 744 "TM8P", "TM9P", "TMAP", \ 745 "TM0S", "TM1S", "TM2P", "TM3S", \ 746 "TM8S", "TM9S", "TMAS", "TMBS", \ 747 "TN0H", "TS0C", \ 748 "Tp0C", "Tp1C", "Tv0S", "Tv1S", NULL } 749 750 #define ASMC_MP1_TEMPNAMES { "ambient", \ 751 "cpu_a_heatsink", "cpu_b_heatsink", \ 752 "cpu_a_proximity", "cpu_core0", "cpu_core1", \ 753 "cpu_core2", "cpu_core3", "THTG", \ 754 "hdd_bay0", "hdd_bay1", \ 755 "hdd_bay2", "hdd_bay3", \ 756 "memory_card_a_proximity0", \ 757 "memory_card_a_proximity1", \ 758 "memory_card_a_proximity2", \ 759 "memory_card_b_proximity0", \ 760 "memory_card_b_proximity1", \ 761 "memory_card_b_proximity2", \ 762 "memory_card_a_slot0", \ 763 "memory_card_a_slot1", \ 764 "memory_card_a_slot2", \ 765 "memory_card_a_slot3", \ 766 "memory_card_b_slot0", \ 767 "memory_card_b_slot1", \ 768 "memory_card_b_slot2", \ 769 "memory_card_b_slot3", \ 770 "mch_heatsink", "expansion_slots", \ 771 "power_supply_loc0", "power_supply_loc1", \ 772 "Tv0S", "Tv1S", } 773 774 #define ASMC_MP1_TEMPDESCS { "Ambient Air", \ 775 "CPU A Heatsink", "CPU B Heatsink", \ 776 "CPU A Proximity", \ 777 "CPU Core 1", "CPU Core 2", \ 778 "CPU Core 3", "CPU Core 4", "THTG", \ 779 "Hard Drive Bay 1", "Hard Drive Bay 2", \ 780 "Hard Drive Bay 3", "Hard Drive Bay 4", \ 781 "Memory Riser A, Proximity 1", \ 782 "Memory Riser A, Proximity 2", \ 783 "Memory Riser A, Proximity 3", \ 784 "Memory Riser B, Proximity 1", \ 785 "Memory Riser B, Proximity 2", \ 786 "Memory Riser B, Proximity 3", \ 787 "Memory Riser A, Slot 1", \ 788 "Memory Riser A, Slot 2", \ 789 "Memory Riser A, Slot 3", \ 790 "Memory Riser A, Slot 4", \ 791 "Memory Riser B, Slot 1", \ 792 "Memory Riser B, Slot 2", \ 793 "Memory Riser B, Slot 3", \ 794 "Memory Riser B, Slot 4", \ 795 "MCH Heatsink", "Expansion Slots", \ 796 "Power Supply, Location 1", \ 797 "Power Supply, Location 2", \ 798 "Tv0S", "Tv1S", } 799 800 #define ASMC_MP31_TEMPS { "TA0P", \ 801 "TC0C", "TC0D", "TC0P", \ 802 "TC1C", "TC1D", \ 803 "TC2C", "TC2D", \ 804 "TC3C", "TC3D", \ 805 "TCAG", "TCAH", "TCBG", "TCBH", \ 806 "TH0P", "TH1P", "TH2P", "TH3P", \ 807 "TM0P", "TM0S", "TM1P", "TM1S", \ 808 "TM2P", "TM2S", "TM3S", \ 809 "TM8P", "TM8S", "TM9P", "TM9S", \ 810 "TMAP", "TMAS", "TMBS", \ 811 "TN0C", "TN0D", "TN0H", \ 812 "TS0C", \ 813 "Tp0C", "Tp1C", \ 814 "Tv0S", "Tv1S", NULL } 815 816 #define ASMC_MP31_TEMPNAMES { "ambient", \ 817 "cpu_core0", "cpu_diode0", "cpu_a_proximity", \ 818 "cpu_core1", "cpu_diode1", \ 819 "cpu_core2", "cpu_diode2", \ 820 "cpu_core3", "cpu_diode3", \ 821 "cpu_a_pkg", "cpu_a_heatsink", \ 822 "cpu_b_pkg", "cpu_b_heatsink", \ 823 "hdd_bay0", "hdd_bay1", \ 824 "hdd_bay2", "hdd_bay3", \ 825 "mem_riser_a_prox0", "mem_riser_a_slot0", \ 826 "mem_riser_a_prox1", "mem_riser_a_slot1", \ 827 "mem_riser_a_prox2", "mem_riser_a_slot2", \ 828 "mem_riser_a_slot3", \ 829 "mem_riser_b_prox0", "mem_riser_b_slot0", \ 830 "mem_riser_b_prox1", "mem_riser_b_slot1", \ 831 "mem_riser_b_prox2", "mem_riser_b_slot2", \ 832 "mem_riser_b_slot3", \ 833 "northbridge_core", "northbridge_diode", \ 834 "northbridge_heatsink", \ 835 "expansion_slots", \ 836 "power_supply0", "power_supply1", \ 837 "vrm0", "vrm1", } 838 839 #define ASMC_MP31_TEMPDESCS { "Ambient Air", \ 840 "CPU Core 1", "CPU Diode 1", \ 841 "CPU A Proximity", \ 842 "CPU Core 2", "CPU Diode 2", \ 843 "CPU Core 3", "CPU Diode 3", \ 844 "CPU Core 4", "CPU Diode 4", \ 845 "CPU A Package", "CPU A Heatsink", \ 846 "CPU B Package", "CPU B Heatsink", \ 847 "Hard Drive Bay 1", "Hard Drive Bay 2", \ 848 "Hard Drive Bay 3", "Hard Drive Bay 4", \ 849 "Memory Riser A, Proximity 1", \ 850 "Memory Riser A, Slot 1", \ 851 "Memory Riser A, Proximity 2", \ 852 "Memory Riser A, Slot 2", \ 853 "Memory Riser A, Proximity 3", \ 854 "Memory Riser A, Slot 3", \ 855 "Memory Riser A, Slot 4", \ 856 "Memory Riser B, Proximity 1", \ 857 "Memory Riser B, Slot 1", \ 858 "Memory Riser B, Proximity 2", \ 859 "Memory Riser B, Slot 2", \ 860 "Memory Riser B, Proximity 3", \ 861 "Memory Riser B, Slot 3", \ 862 "Memory Riser B, Slot 4", \ 863 "Northbridge Core", "Northbridge Diode", \ 864 "Northbridge Heatsink", \ 865 "Expansion Slots", \ 866 "Power Supply 1", "Power Supply 2", \ 867 "VRM 1", "VRM 2", } 868 869 #define ASMC_MP2_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 870 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 871 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 872 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 873 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 874 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 875 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \ 876 NULL } 877 878 #define ASMC_MP2_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 879 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 880 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 881 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 882 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 883 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 884 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 885 886 #define ASMC_MP2_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 887 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 888 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 889 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 890 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 891 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 892 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 893 894 #define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 895 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 896 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 897 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 898 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 899 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 900 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 901 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 902 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 903 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 904 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 905 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 906 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 907 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 908 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \ 909 NULL } 910 911 #define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \ 912 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 913 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 914 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 915 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 916 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 917 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 918 "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \ 919 "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \ 920 "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \ 921 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 922 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 923 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 924 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 925 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 926 927 #define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 928 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 929 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 930 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 931 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 932 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 933 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 934 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 935 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 936 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 937 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 938 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 939 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 940 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 941 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 942 943 #define ASMC_MP6_TEMPS { "TA0P", "TA1P", "TC0P", "TG0D", "TG0P", \ 944 "TG1D", "TG1P", "TM0P", "TM1P", NULL } 945 946 #define ASMC_MP6_TEMPNAMES { "ambient_air_1", "ambient_air_2", \ 947 "cpu_proximity", "gpu_diode_1", \ 948 "gpu_proximity_1", "gpu_diode_2", \ 949 "gpu_proximity_2", "mem_proximity_1", \ 950 "mem_proximity_2" } 951 952 #define ASMC_MP6_TEMPDESCS { "Ambient Air 1", "Ambient Air 2", \ 953 "CPU Proximity", "GPU Diode 1", \ 954 "GPU Proximity 1", "GPU Diode 2", \ 955 "GPU Proximity 2", "Memory Bank A", \ 956 "Memory Bank B" } 957 958 #define ASMC_MBA_TEMPS { "TB0T", NULL } 959 #define ASMC_MBA_TEMPNAMES { "enclosure" } 960 #define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" } 961 962 #define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \ 963 "TC0D", "TC0E", "TC0P", NULL } 964 965 #define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \ 966 "TC0D", "TC0E", "TC0P" } 967 968 #define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \ 969 "TC0D", "TC0E", "TC0P" } 970 971 #define ASMC_MBA4_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 972 "TC0D", "TC0E", "TC0F", "TC0P", \ 973 "TC1C", "TC2C", "TCGC", "TCSA", \ 974 "TH0F", "TH0J", "TH0O", "TH0o", \ 975 "TM0P", "TPCD", "Ta0P", "Th1H", \ 976 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 977 NULL } 978 979 #define ASMC_MBA4_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TC0C", \ 980 "TC0D", "TC0E", "TC0F", "TC0P", \ 981 "TC1C", "TC2C", "TCGC", "TCSA", \ 982 "TH0F", "TH0J", "TH0O", "TH0o", \ 983 "TM0P", "TPCD", "Ta0P", "Th1H", \ 984 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 985 NULL } 986 987 #define ASMC_MBA4_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TC0C", \ 988 "TC0D", "TC0E", "TC0F", "TC0P", \ 989 "TC1C", "TC2C", "TCGC", "TCSA", \ 990 "TH0F", "TH0J", "TH0O", "TH0o", \ 991 "TM0P", "TPCD", "Ta0P", "Th1H", \ 992 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 993 NULL } 994 995 #define ASMC_MBA5_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 996 "TC0D", "TC0E", "TC0F", "TC0P", \ 997 "TC1C", "TC2C", "TCGC", "TCSA", \ 998 "TCXC", "THSP", "TM0P", "TPCD", \ 999 "Ta0P", "Th1H", "Tm0P", "Tm1P", \ 1000 "Ts0P", "Ts0S", NULL } 1001 1002 #define ASMC_MBA5_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", "TC0C", \ 1003 "cpudiode", "cputemp1", "cputemp2", "cpuproximity", \ 1004 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 1005 "TCXC", "THSP", "memorybank", "pchdie", \ 1006 "Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \ 1007 "palmrest", "memoryproximity" } 1008 1009 #define ASMC_MBA5_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\ 1010 "CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 1011 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 1012 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 1013 "Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \ 1014 "Palm Rest", "Memory Proximity" } 1015 1016 /* 1017 * TODO: validate the temp zones for MBA 6.x ! 1018 */ 1019 #define ASMC_MBA6_TEMPS { "TB0T", "TB1T", "TB2T", \ 1020 "TC0E", "TC0F", "TC0P", \ 1021 "TC1C", "TC2C", "TCGC", "TCSA", \ 1022 "TCXC", "THSP", "TM0P", "TPCD", \ 1023 "Ta0P", "Th1H", "Tm0P", \ 1024 "Ts0P", "Ts0S", NULL } 1025 1026 #define ASMC_MBA6_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \ 1027 "cputemp1", "cputemp2", "cpuproximity", \ 1028 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 1029 "TCXC", "THSP", "memorybank", "pchdie", \ 1030 "Ta0P", "heatpipe", "mainboardproximity1", \ 1031 "palmrest", "memoryproximity" } 1032 1033 #define ASMC_MBA6_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \ 1034 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 1035 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 1036 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 1037 "Ta0P", "Heatpipe", "Mainboard Proximity 1", \ 1038 "Palm Rest", "Memory Proximity" } 1039 1040 1041 #define ASMC_MBA7_TEMPS { "TB0T", "TB1T", "TB2T", \ 1042 "TC0E", "TC0F", "TC0P", \ 1043 "TC1C", "TC2C", \ 1044 "TCGC", "TCSA", "TCXC", \ 1045 "THSP", "TM0P", "TPCD", \ 1046 "TW0P" "Ta0P", "Th1H", \ 1047 "Tm0P", "Ts0P", "Ts0S", NULL } 1048 1049 #define ASMC_MBA7_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \ 1050 "cputemp1", "cputemp2", "cpuproximity", \ 1051 "cpucore1", "cpucore2", \ 1052 "pecigpu", "pecisa", "pecicpu", \ 1053 "thunderboltproximity", "memorybank", "pchdie", \ 1054 "wirelessproximity", "airflowproximity", "heatpipe", \ 1055 "mainboardproximity", "palmrest", "memoryproximity" } 1056 1057 #define ASMC_MBA7_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \ 1058 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 1059 "CPU Core 1", "CPU Core 2", \ 1060 "PECI GPU", "PECI SA", "PECI CPU", \ 1061 "Thunderbolt Proximity", "Memory Bank A", "PCH Die", \ 1062 "Wireless Proximity", "Airflow Proxmity", "Heatpipe", \ 1063 "Mainboard Proximity", "Palm Rest", "Memory Proximity" } 1064