1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 #define ASMC_MAXFANS 6 31 #define ASMC_MAXVAL 32 /* Maximum SMC value size */ 32 #define ASMC_KEYLEN 4 /* SMC key name length */ 33 #define ASMC_TYPELEN 4 /* SMC type string length */ 34 #define ASMC_MAX_SENSORS 64 /* Max sensors per type */ 35 36 struct asmc_softc { 37 device_t sc_dev; 38 struct mtx sc_mtx; 39 int sc_nfan; 40 int sc_nkeys; 41 int16_t sms_rest_x; 42 int16_t sms_rest_y; 43 int16_t sms_rest_z; 44 struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1]; 45 struct sysctl_oid *sc_temp_tree; 46 struct sysctl_oid *sc_sms_tree; 47 struct sysctl_oid *sc_light_tree; 48 const struct asmc_model *sc_model; 49 int sc_rid_port; 50 int sc_rid_irq; 51 struct resource *sc_ioport; 52 struct resource *sc_irq; 53 void *sc_cookie; 54 int sc_sms_intrtype; 55 struct taskqueue *sc_sms_tq; 56 struct task sc_sms_task; 57 uint8_t sc_sms_intr_works; 58 struct cdev *sc_kbd_bkl; 59 uint32_t sc_kbd_bkl_level; 60 #ifdef ASMC_DEBUG 61 /* Raw key access */ 62 struct sysctl_oid *sc_raw_tree; 63 char sc_rawkey[ASMC_KEYLEN + 1]; 64 uint8_t sc_rawval[ASMC_MAXVAL]; 65 uint8_t sc_rawlen; 66 char sc_rawtype[ASMC_TYPELEN + 1]; 67 #endif 68 /* Voltage/Current/Power/Light sensors */ 69 char *sc_voltage_sensors[ASMC_MAX_SENSORS]; 70 int sc_voltage_count; 71 char *sc_current_sensors[ASMC_MAX_SENSORS]; 72 int sc_current_count; 73 char *sc_power_sensors[ASMC_MAX_SENSORS]; 74 int sc_power_count; 75 char *sc_light_sensors[ASMC_MAX_SENSORS]; 76 int sc_light_count; 77 }; 78 79 /* 80 * Data port. 81 */ 82 #define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00) 83 #define ASMC_DATAPORT_WRITE(sc, val) \ 84 bus_write_1(sc->sc_ioport, 0x00, val) 85 #define ASMC_STATUS_MASK 0x0f 86 87 /* 88 * Command port. 89 */ 90 #define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04) 91 #define ASMC_CMDPORT_WRITE(sc, val) \ 92 bus_write_1(sc->sc_ioport, 0x04, val) 93 #define ASMC_CMDREAD 0x10 94 #define ASMC_CMDWRITE 0x11 95 #define ASMC_CMDGETBYINDEX 0x12 96 #define ASMC_CMDGETINFO 0x13 97 98 #define ASMC_STATUS_AWAIT_DATA 0x04 99 #define ASMC_STATUS_DATA_READY 0x05 100 101 #define ASMC_KEYINFO_RESPLEN 6 /* getinfo: 1 len + 4 type + 1 attr */ 102 #define ASMC_MAXRETRIES 10 103 104 /* 105 * Interrupt port. 106 */ 107 #define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f) 108 109 /* Number of keys */ 110 #define ASMC_NKEYS "#KEY" /* RO; 4 bytes */ 111 112 /* Query the ASMC revision */ 113 #define ASMC_KEY_REV "REV " /* RO: 6 bytes */ 114 115 /* 116 * Fan control via SMC. 117 */ 118 #define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */ 119 #define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */ 120 #define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */ 121 #define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */ 122 #define ASMC_KEY_FANMINSPEED "F%dMn" /* RW; 2 bytes */ 123 #define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */ 124 #define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */ 125 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */ 126 127 /* 128 * Sudden Motion Sensor (SMS). 129 */ 130 #define ASMC_SMS_INIT1 0xe0 131 #define ASMC_SMS_INIT2 0xf8 132 #define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */ 133 #define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */ 134 #define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */ 135 #define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */ 136 #define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */ 137 #define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */ 138 #define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */ 139 #define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */ 140 #define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */ 141 #define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */ 142 #define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */ 143 #define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */ 144 145 /* 146 * Light Sensor. 147 */ 148 #define ASMC_ALSL_INT2A 0x2a /* Ambient Light related Interrupt */ 149 150 /* 151 * Keyboard backlight. 152 */ 153 #define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */ 154 #define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */ 155 #define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */ 156 157 /* 158 * Clamshell. 159 */ 160 #define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */ 161 162 /* 163 * Auto power on / Wake-on-LAN. 164 */ 165 #define ASMC_KEY_AUPO "AUPO" /* RW; 1 byte */ 166 167 /* 168 * Interrupt keys. 169 */ 170 #define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */ 171 172 /* 173 * Temperatures. 174 * 175 * First for MacBook, second for MacBook Pro, third for Intel Mac Mini, 176 * fourth the Mac Pro 8-core and finally the MacBook Air. 177 * 178 */ 179 /* maximum array size for temperatures including the last NULL */ 180 #define ASMC_TEMP_MAX 80 181 #define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \ 182 "TM0P", NULL } 183 #define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \ 184 "northbridge2", "heatsink1", \ 185 "heatsink2", "memory", } 186 #define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \ 187 "Northbridge Point 1", \ 188 "Northbridge Point 2", "Heatsink 1", \ 189 "Heatsink 2", "Memory Bank A", } 190 191 #define ASMC_MB31_TEMPS { "TB0T", "TN0P", "Th0H", "Th1H", \ 192 "TM0P", NULL } 193 194 #define ASMC_MB31_TEMPNAMES { "enclosure", "northbridge1", \ 195 "heatsink1", "heatsink2", \ 196 "memory", } 197 198 #define ASMC_MB31_TEMPDESCS { "Enclosure Bottomside", \ 199 "Northbridge Point 1", \ 200 "Heatsink 1","Heatsink 2" \ 201 "Memory Bank A", } 202 203 #define ASMC_MB71_TEMPS { "TB0T", "TB1T", "TB2T", "TC0D", "TC0P", \ 204 "TH0P", "TN0D", "TN0P", "TN0S", "TN1D", \ 205 "TN1E", "TN1F", "TN1G", "TN1S", "Th1H", \ 206 "Ts0P", "Ts0S", NULL } 207 208 #define ASMC_MB71_TEMPNAMES { "enclosure_bottom0", "battery_1", "battery_2", "cpu_package", "cpu_proximity", \ 209 "hdd_bay", "northbridge0_diode", "northbridge0_proximity", "TN0S", "mpc_die2", \ 210 "TN1E", "TN1F", "TN1G", "TN1S", "heatsink1", \ 211 "palm_rest", "memory_proximity", } 212 213 #define ASMC_MB71_TEMPDESCS { "Enclosure Bottom 0", "Battery 1", "Battery 2", "CPU Package", "CPU Proximity", \ 214 "HDD Bay", "Northbridge Diode", "Northbridge Proximity", "TN0S", "MPC Die 2", \ 215 "TN1E", "TN1F", "TN1G", "TN1S", "Heatsink 1", \ 216 "Palm Rest", "Memory Proximity", } 217 218 #define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \ 219 "TG0H", "TG0P", "TG0T", NULL } 220 221 #define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \ 222 "heatsink2", "memory", "graphics", \ 223 "graphicssink", "unknown", } 224 225 #define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \ 226 "Heatsink 1", "Heatsink 2", \ 227 "Memory Controller", \ 228 "Graphics Chip", "Graphics Heatsink", \ 229 "Unknown", } 230 231 #define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \ 232 "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \ 233 "TTF0", "TW0P", NULL } 234 235 #define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \ 236 "heatsink3", "memory", "graphicssink", \ 237 "graphics", "cpu", "cpu2", "unknown1", \ 238 "unknown2", "wireless", } 239 240 #define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \ 241 "Main Heatsink 1", "Main Heatsink 2", \ 242 "Main Heatsink 3", \ 243 "Memory Controller", \ 244 "Graphics Chip Heatsink", \ 245 "Graphics Chip Diode", \ 246 "CPU Temperature Diode", "CPU Point 2", \ 247 "Unknown", "Unknown", \ 248 "Wireless Module", } 249 250 #define ASMC_MBP51_TEMPS { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", \ 251 "TC0F", "TC0P", "TG0D", "TG0F", "TG0H", \ 252 "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", \ 253 "TTF0", "Th2H", "Tm0P", "Ts0P", "Ts0S", \ 254 NULL } 255 256 #define ASMC_MBP51_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 257 "enclosure_bottom_2", "enclosure_bottom_3", \ 258 "cpu_diode", "cpu", \ 259 "cpu_pin", "gpu_diode", \ 260 "gpu", "gpu_heatsink", \ 261 "gpu_pin", "gpu_transistor", \ 262 "gpu_2_heatsink", "northbridge_diode", \ 263 "northbridge_pin", "unknown", \ 264 "heatsink_2", "memory_controller", \ 265 "pci_express_slot_pin", "pci_express_slot_unk" } 266 267 #define ASMC_MBP51_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 268 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 269 "CPU Diode", "CPU ???", \ 270 "CPU Pin", "GPU Diode", \ 271 "GPU ???", "GPU Heatsink", \ 272 "GPU Pin", "GPU Transistor", \ 273 "GPU 2 Heatsink", "Northbridge Diode", \ 274 "Northbridge Pin", "Unknown", \ 275 "Heatsink 2", "Memory Controller", \ 276 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 277 278 #define ASMC_MBP62_TEMPS { "TB0T", "TB1T", "TB2T", \ 279 "TC0C", "TC0D", "TC0P", \ 280 "TC1C", "TG0D", "TG0P", \ 281 "TG0T", "TMCD", "TP0P", \ 282 "TPCD", "Th1H", "Th2H", \ 283 "Tm0P", "Ts0P", "Ts0S" } 284 285 #define ASMC_MBP62_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 286 "enclosure_bottom_2", "cpu0", \ 287 "cpu_diode", "cpu_proximity", \ 288 "cpu1", "gpu_diode", \ 289 "gpu_pin", "gpu_transistor", \ 290 "TMCD", "pch_controller_proximity", \ 291 "pch_die", "heatsink1", \ 292 "heatsink2", "memory-controller", \ 293 "palmrest", "memoryproximity" } 294 295 #define ASMC_MBP62_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 296 "Enclosure Bottom 2", "CPU 0", \ 297 "CPU Diode", "CPU Proximity", \ 298 "CPU 1", "GPU Diode", \ 299 "GPU Pin", "GPU Transistor", \ 300 "TMCD", "PCH Controller Proximity", \ 301 "PCH Die", "Heat Sink 1", \ 302 "Heat Sink 2", "Memory Controller", \ 303 "Palm Rest", "Memory Proximity" } 304 305 #define ASMC_MBP55_TEMPS { "TB0T", "TB1T", \ 306 "TB2T", "TB3T", \ 307 "TC0D", "TC0P", \ 308 "TN0D", "TN0P", \ 309 "TTF0", \ 310 "Th0H", "Th1H", "ThFH", \ 311 "Ts0P", "Ts0S", \ 312 NULL } 313 314 #define ASMC_MBP55_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 315 "enclosure_bottom_2", "enclosure_bottom_3", \ 316 "cpu_diode", "cpu_pin", \ 317 "northbridge_diode", "northbridge_pin", \ 318 "unknown", \ 319 "heatsink_0", "heatsink_1", "heatsink_2", \ 320 "pci_express_slot_pin", "pci_express_slot_unk" } 321 322 #define ASMC_MBP55_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 323 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 324 "CPU Diode", "CPU Pin", \ 325 "Northbridge Diode", "Northbridge Pin", \ 326 "Unknown", \ 327 "Heatsink 0", "Heatsink 1", "Heatsink 2", \ 328 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 329 330 #define ASMC_MBP81_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 331 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 332 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 333 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 334 "Ts0S", NULL } 335 336 #define ASMC_MBP81_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 337 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 338 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 339 "TP0P", "TPCD", "wireless", "Th1H", "Ts0P", \ 340 "Ts0S" } 341 342 #define ASMC_MBP81_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 343 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 344 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 345 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 346 "Ts0S" } 347 348 #define ASMC_MBP82_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 349 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 350 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 351 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 352 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 353 "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL } 354 355 #define ASMC_MBP82_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 356 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 357 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 358 "TCTD", "graphics", "TG0P", "THSP", "TM0S", \ 359 "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \ 360 "Th2H", "memory", "Ts0P", "Ts0S" } 361 362 #define ASMC_MBP82_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 363 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 364 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 365 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 366 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 367 "Th2H", "Tm0P", "Ts0P", "Ts0S" } 368 369 #define ASMC_MBP83_TEMPS { "ALSL", "F0Ac", "F1Ac", "IB0R", "IC0R", \ 370 "ID0R", "IG0R", "IO0R", "PCPC", "PCPG", \ 371 "PCPT", "PD0R", "TB1T", "TB2T", "TC0C", \ 372 "TC0D", "TC0P", "TC1C", "TC2C", "TC3C", \ 373 "TC4C", "TG0D", "TG0P", "THSP", "TP0P", \ 374 "TPCD", "Th1H", "Th2H", "Tm0P", "Ts0P", \ 375 "VC0C", "VD0R", "VG0C", "VN0C", "VP0R", NULL } 376 377 #define ASMC_MBP83_TEMPNAMES { "ambient_light", "fan_leftside", "fan_rightside", \ 378 "battery_current", "cpu_vcorevtt", "dc_current", \ 379 "gpu_voltage", "other", "cpu_package_core", \ 380 "cpu_package_gpu", "cpu_package_total", "dc_in", \ 381 "battery_1", "battery_2", "cpu_die_digital", \ 382 "cpu_die_analog", "cpu_proximity", "cpu_core_1", \ 383 "cpu_core_2", "cpu_core_3", "cpu_core_4", "gpu_die_analog", \ 384 "gpu_proximity", "thunderbolt", "platform_controller", \ 385 "pch_die_digital", "right_fin_stack", "left_fin_stack", \ 386 "dc_in_air_flow", "palm_rest", "cpu_vcore", "dc_in_voltage", \ 387 "gpu_vcore", "intel_gpu_vcore", "pbus_voltage" } 388 389 #define ASMC_MBP83_TEMPDESCS { "Ambient Light", "Fan Leftside", "Fan Rightside", \ 390 "Battery BMON Current", "CPU VcoreVTT", "DC In AMON Current", \ 391 "GPU Voltage", "Other 5V 3V", "CPU Package Core", \ 392 "CPU Package GPU", "CPU Package Total", "DC In", \ 393 "Battery Sensor 1", "Battery Sensor 2", "CPU Die Digital", \ 394 "CPU Die Analog", "CPU Proximity", "CPU Core 1 DTS", \ 395 "CPU Core 2 DTS", "CPU Core 3 DTS", "CPU Core 4 DTS", \ 396 "GPU Die Analog", "GPU Proximity", "Thunderbolt Proximity", \ 397 "Platform Controller Hub", "PCH Die Digital", \ 398 "Right Fin Stack Proximity", "Left Fin Stack Proximity", \ 399 "DC In Proximity Air Flow", "Palm Rest", "CPU VCore", \ 400 "DC In Voltage", "GPU VCore", "Intel GPU VCore", "PBus Voltage" } 401 402 #define ASMC_MBP91_TEMPS { "TA0P", "TB0T", "TB1T", "TB2T", "TC0E", \ 403 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 404 "TC4C", "TCGC", "TCSA", "TCXC", "TG0D", \ 405 "TG0P", "TG1D", "TG1F", "TG1d", "TGTC", \ 406 "TGTD", "TM0P", "TM0S", "TP0P", "TPCD", \ 407 "Th1H", "Th2H", "Ts0P", "Ts0S", "Tsqf", NULL } 408 409 #define ASMC_MBP91_TEMPNAMES { "ambient", "enclosure_bottom_1", "enclosure_bottom_2", \ 410 "enclosure_bottom_3", "cpu_die_peci_0", "cpu_die_peci_1", \ 411 "cpu_proximity", "cpu_core_1", "cpu_core_2", "cpu_core_3", \ 412 "cpu_core_4", "intel_gpu", "cpu_sys_agent", \ 413 "cpu_core_peci", "gpu_analog", \ 414 "gpu_proximity", "geforce_gpu_digital", "tg1f", \ 415 "gpu_2_die", "tgtc", "tgtd", "memory_proximity", \ 416 "mem_bank_a1", "platform_ctrl_hub", "pch_digital", \ 417 "main_heatsink_r", "main_heatsink_l", "palm_rest", \ 418 "bottom_skin", "tsqf" } 419 420 #define ASMC_MBP91_TEMPDESCS { "Ambient", "Enclosure Bottom 1", "Enclosure Bottom 2", \ 421 "Enclosure Bottom 3", "CPU Die PECI 0", "CPU Die PECI 1", \ 422 "CPU Proximity", "CPU Core 1", "CPU Core 2", \ 423 "CPU Core 3", "CPU Core 4", "Intel GPU", \ 424 "CPU System Agent Core", "CPU Core - PECI", \ 425 "GPU Die - Analog", "GPU Proximity", \ 426 "GeForce GPU Die - Digital", "TG1F", "GPU 2 Die" \ 427 "TGTC", "TGTD", "Memory Proximity", \ 428 "Memory Bank A1", "Platform Controller Hub", "PCH Die - Digital", \ 429 "Main Heatsink Right", "Main Heatsink Left", "Palm Rest", \ 430 "Bottom Skin", "Tsqf" } 431 432 #define ASMC_MBP92_TEMPS { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 433 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 434 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 435 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 436 "TPCD", NULL } 437 438 #define ASMC_MBP92_TEMPNAMES { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 439 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 440 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 441 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 442 "TPCD" } 443 444 #define ASMC_MBP92_TEMPDESCS { "Palm Rest", "Memory Proximity", "Airflow 1", \ 445 "Battery 1", "Battery 2", "Battery TS_MAX", \ 446 "CPU Core 1", "CPU Core 2", "CPU1", "CPU1", \ 447 "TC0J", "CPU 1 Proximity", "TCFC", \ 448 "PECI GPU", "PECI SA", "TCTD", "PECI CPU", \ 449 "GPU Die", "Memory Bank A1", "Memory Module A1", \ 450 "PCH Die" } 451 452 #define ASMC_MBP112_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 453 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 454 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 455 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 456 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 457 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 458 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 459 "Ts1S", NULL } 460 461 #define ASMC_MBP112_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 462 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 463 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 464 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 465 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 466 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 467 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 468 "Ts1S" } 469 470 #define ASMC_MBP112_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 471 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 472 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 473 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 474 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 475 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 476 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 477 "Ts1S" } 478 479 #define ASMC_MBP113_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 480 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 481 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 482 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 483 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 484 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 485 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 486 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 487 "Ts1S", NULL } 488 489 #define ASMC_MBP113_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 490 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 491 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 492 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 493 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 494 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 495 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 496 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 497 "Ts1S" } 498 499 #define ASMC_MBP113_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 500 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 501 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 502 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 503 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 504 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 505 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 506 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 507 "Ts1S" } 508 509 #define ASMC_MBP114_TEMPS { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 510 "IO3R", "IO5R", "IM0C", "IC1C", "IC2C", \ 511 "IC3C", "ILDC", "IBLC", "IAPC", "IHSC", \ 512 "ICMC", "TC0P", "TP0P", "TM0P", \ 513 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 514 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 515 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 516 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 517 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 518 "PCPG", "PCPT", "PSTR", "PDTR", NULL } 519 520 #define ASMC_MBP114_TEMPNAMES { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 521 "IO3R", "IO5R", "IM0C", "IC1C", "IC2C", \ 522 "IC3C", "ILDC", "IBLC", "IAPC", "IHSC", \ 523 "ICMC", "TC0P", "TP0P", "TM0P", \ 524 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 525 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 526 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 527 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 528 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 529 "PCPG", "PCPT", "PSTR", "PDTR" } 530 531 #define ASMC_MBP114_TEMPDESCS { "CPU High (CPU, I/O)", "DC In", "SSD", "Charger (BMON)", "CPU", \ 532 "Other 3.3V", "Other 5V", "Memory", "Platform Controller Hub Core", "CPU Load Current Monitor", \ 533 "CPU DDR", "LCD Panel", "LCD Backlight", "Airport", "Thunderbolt", \ 534 "S2", "CPU Proximity", "Platform Controller Hub", "Memory Proximity", "Air Flow Proximity", \ 535 "Left Fin Stack", "Right Fin Stack", "Airport Proximity", "Palm Rest", "Palm Rest Actuator", \ 536 "Battery Max", "Battery Sensor 1", "Battery Sensor 2", "SSD A", "SSD B", \ 537 "CPU Core 1", "CPU Core 2", "CPU Core 3", "CPU Core 4", "CPU PECI Die", \ 538 "Intel GPU", "Platform Controller Hub PECI", "CPU System Agent Core", "CPU VCore", "DC In", \ 539 "Pbus", "Ambient Light", "Leftside", "Rightside", "CPU Package Core", \ 540 "CPU Package GPU", "CPU Package Total", "System Total", "DC In" } 541 542 /* MacBookPro11,5 - same as 11,4 but without IBLC, ICMC, and IC2C keys */ 543 #define ASMC_MBP115_TEMPS { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 544 "IO3R", "IO5R", "IM0C", "IC1C", \ 545 "IC3C", "ILDC", "IAPC", "IHSC", \ 546 "TC0P", "TP0P", "TM0P", \ 547 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 548 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 549 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 550 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 551 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 552 "PCPG", "PCPT", "PSTR", "PDTR", NULL } 553 554 555 #define ASMC_MBP115_TEMPNAMES { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 556 "IO3R", "IO5R", "IM0C", "IC1C", \ 557 "IC3C", "ILDC", "IAPC", "IHSC", \ 558 "TC0P", "TP0P", "TM0P", \ 559 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 560 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 561 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 562 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 563 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 564 "PCPG", "PCPT", "PSTR", "PDTR" } 565 566 #define ASMC_MBP115_TEMPDESCS { "CPU High (CPU, I/O)", "DC In", "SSD", "Charger (BMON)", "CPU", \ 567 "Other 3.3V", "Other 5V", "Memory", "Platform Controller Hub Core", \ 568 "CPU DDR", "LCD Panel", "Airport", "Thunderbolt", \ 569 "CPU Proximity", "Platform Controller Hub", "Memory Proximity", "Air Flow Proximity", \ 570 "Left Fin Stack", "Right Fin Stack", "Airport Proximity", "Palm Rest", "Palm Rest Actuator", \ 571 "Battery Max", "Battery Sensor 1", "Battery Sensor 2", "SSD A", "SSD B", \ 572 "CPU Core 1", "CPU Core 2", "CPU Core 3", "CPU Core 4", "CPU PECI Die", \ 573 "Intel GPU", "Platform Controller Hub PECI", "CPU System Agent Core", "CPU VCore", "DC In", \ 574 "Pbus", "Ambient Light", "Leftside", "Rightside", "CPU Package Core", \ 575 "CPU Package GPU", "CPU Package Total", "System Total", "DC In" } 576 577 #define ASMC_MBP131_TEMPS { "TB0T", "TB1T", "TB2T", "TC0F", \ 578 "TC0P", "TC1C", "TC2C", "TCGC", \ 579 "TCSA", "TCXC", "Th1H", "TM0P", \ 580 "TPCD", "Ts0P", "Ts0S", "TaLC", \ 581 "Ts1P", NULL } 582 583 #define ASMC_MBP131_TEMPNAMES { "battery", "battery_1", "battery_2", "cpu_die_peci", \ 584 "cpu_proximity", "cpu_core_1", "cpu_core_2", "intel_gpu", \ 585 "cpu_sys_agent", "cpu_core_peci", "right_fin_stack", "memory_proximity", \ 586 "platform_ctrl_hub", "trackpad", "bottom_skin", "air_flow", \ 587 "trackpad_act" } 588 589 #define ASMC_MBP131_TEMPDESCS { "Battery", "Battery Sensor 1", "Battery Sensor 2", "CPU Die (PECI)", \ 590 "CPU Proximity", "CPU Core 1", "CPU Core 2", "Intel GPU", \ 591 "CPU System Agent Core (PECI)", "CPU Core (PECI)", "Right Fin Stack", "DDR3 Proximity", \ 592 "Platform Controller Hub Die", "Trackpad", "Bottom Skin", "Air Flow", \ 593 "Trackpad Actuator" } 594 595 #define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL } 596 #define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" } 597 #define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \ 598 "Northbridge Point 2" } 599 600 #define ASMC_MM21_TEMPS { "TA0P", "TC0D", \ 601 "TC0H", "TC0P", \ 602 "TC1P", "TN0P", \ 603 "TN1P", NULL } 604 605 #define ASMC_MM21_TEMPNAMES { "ambient_air", "cpu_die", \ 606 "cpu_heatsink", "cpu_proximity1", \ 607 "cpu_proximity2", "northbridge_proximity1", \ 608 "northbridge_proximity2", } 609 610 #define ASMC_MM21_TEMPDESCS { "Ambient Air Temperature" \ 611 "CPU Die Core Temperature", \ 612 "CPU Heatsink Temperature", \ 613 "CPU Proximity 1 Temperature", \ 614 "CPU Proximity 2 Temperature", \ 615 "Northbridge Proximity 1 Temperature", \ 616 "Northbridge Proximity 2 Temperature", } 617 618 #define ASMC_MM31_TEMPS { "TC0D", "TC0H", \ 619 "TC0P", "TH0P", \ 620 "TN0D", "TN0P", \ 621 "TW0P", NULL } 622 623 #define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \ 624 "cpu0_proximity", "hdd_bay", \ 625 "northbridge_die", \ 626 "northbridge_proximity", \ 627 "wireless_proximity", } 628 629 #define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \ 630 "CPU0 Heatsink Temperature", \ 631 "CPU0 Proximity Temperature", \ 632 "HDD Bay Temperature", \ 633 "Northbridge Die Core Temperature", \ 634 "Northbridge Proximity Temperature", \ 635 "Wireless Module Proximity Temperature", } 636 637 #define ASMC_MM41_TEMPS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 638 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 639 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 640 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 641 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 642 "TW0P", "Tm0P", "Tp0C", NULL } 643 644 #define ASMC_MM41_TEMPNAMES { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 645 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 646 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 647 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 648 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 649 "TW0P", "Tm0P", "Tp0C", NULL } 650 651 #define ASMC_MM41_TEMPDESCS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 652 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 653 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 654 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 655 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 656 "TW0P", "Tm0P", "Tp0C", NULL } 657 658 #define ASMC_MM52_TEMPS { "TA0P", "TA1P", \ 659 "TC0D", "TC0P", \ 660 "TG0D", "TG1D", \ 661 "TG0P", "TG0M", \ 662 "TI0P", \ 663 "TM0S", "TMBS", \ 664 "TM0P", "TP0P", \ 665 "TPCD", "Tp0C", \ 666 "TW0P", NULL } 667 668 #define ASMC_MM52_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 669 "cpu_die", "cpu_proximity", \ 670 "gpu_diode1", "gpu_diode2", \ 671 "gpu_proximity", "gpu_integrated_switcher", \ 672 "thunderbolt_proximity", \ 673 "memory_slot1", "memory_slot2", \ 674 "memory_proximity", "pch_controller_proximity", \ 675 "pch_controller_die", "pwr_supply", \ 676 "wireless_proximity", } 677 678 #define ASMC_MM52_TEMPDESCS { "Ambient Air Proximity Temperature", \ 679 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 680 "CPU Die Temperature", "CPU Proximity Temperature", \ 681 "GPU Diode 1 Temperature" , "GPU Diode 2 Temperature", \ 682 "GPU Proximity Temperature", \ 683 "Integrated Graphics/GPU Switcher Temperature", \ 684 "Thunderbolt Proximity Temperature", \ 685 "Memory Slot 1 Temperature", \ 686 "Memory Slot 2 Temperature", \ 687 "Memory Slots Proximity Temperature", \ 688 "Platform Controller Hub Proximity Temperature", \ 689 "Platform Controller Hub Die Temperature", \ 690 "Power Supply Temperature", \ 691 "Wireless Module Proximity Temperature", } 692 693 #define ASMC_MM61_TEMPS { "TA0P", "TA1P", \ 694 "TC0D", "TC0G", "TC0P", "TCPG", \ 695 "TI0P", \ 696 "TM0S", "TMBS", "TM0P", \ 697 "TP0P", "TPCD", \ 698 "Tp0C", \ 699 "TW0P", NULL } 700 701 #define ASMC_MM61_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 702 "cpu_die", "TC0G", "cpu_proximity", "TCPG", \ 703 "thunderbolt_proximity", \ 704 "memory_slot1", "memory_slot2", "memory_proximity", \ 705 "pch_controller_proximity", "pch_controller_die", \ 706 "pwr_supply", \ 707 "wireless_proximity", NULL } 708 709 #define ASMC_MM61_TEMPDESCS { "Ambient Air Proximity Temperature", \ 710 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 711 "CPU Die Temperature", \ 712 NULL, \ 713 "CPU Proximity Temperature", \ 714 NULL, \ 715 "Thunderbolt Proximity Temperature", \ 716 "Memory Slot 1 Temperature", \ 717 "Memory Slot 2 Temperature", \ 718 "Memory Slots Proximity Temperature", \ 719 "Platform Controller Hub Proximity Temperature", \ 720 "Platform Controller Hub Die Temperature", \ 721 "Power Supply Temperature", \ 722 "Wireless Module Proximity Temperature", NULL } 723 724 #define ASMC_MM62_TEMPS { "TA0P", "TA1P", \ 725 "TC0D", "TC0G", "TC0P", "TCPG", \ 726 "TI0P", \ 727 "TM0S", "TMBS", "TM0P", \ 728 "TP0P", "TPCD", \ 729 "Tp0C", \ 730 "TW0P", NULL } 731 732 #define ASMC_MM62_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 733 "cpu_die", "TC0G", "cpu_proximity", "TCPG", \ 734 "thunderbolt_proximity", \ 735 "memory_slot1", "memory_slot2", "memory_proximity", \ 736 "pch_controller_proximity", "pch_controller_die", \ 737 "pwr_supply", \ 738 "wireless_proximity", NULL } 739 740 #define ASMC_MM62_TEMPDESCS { "Ambient Air Proximity Temperature", \ 741 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 742 "CPU Die Temperature", \ 743 NULL, \ 744 "CPU Proximity Temperature", \ 745 NULL, \ 746 "Thunderbolt Proximity Temperature", \ 747 "Memory Slot 1 Temperature", \ 748 "Memory Slot 2 Temperature", \ 749 "Memory Slots Proximity Temperature", \ 750 "Platform Controller Hub Proximity Temperature", \ 751 "Platform Controller Hub Die Temperature", \ 752 "Power Supply Temperature", \ 753 "Wireless Module Proximity Temperature", NULL } 754 755 #define ASMC_MM71_TEMPS { "TA0p", "TA1p", \ 756 "TA2p", "TC0c", \ 757 "TC0p", "TC1c", \ 758 "TCGc", "TCSc", \ 759 "TCXC", "TCXR", \ 760 "TM0p", "TPCd", \ 761 "TW0p", "Te0T", \ 762 "Tm0P", NULL } 763 764 #define ASMC_MM71_TEMPNAMES { "ambient_air1", "ambient_air2", \ 765 "ambient_air3", "cpu_core1_peci", \ 766 "cpu_proximity", "cpu_core2_peci", \ 767 "intel_gpu", "cpu_sa_core_peci", \ 768 "cpu_core", "cpu_peci_dts", \ 769 "memory_proximity", "pch_controller_die", \ 770 "wireless_proximity", "thunderbolt_diode", \ 771 "logic_board", } 772 773 #define ASMC_MM71_TEMPDESCS { "Ambient Air Temperature 1", \ 774 "Ambient Air Temperature 2", \ 775 "Ambient Air Temperature 3", \ 776 "CPU Core 1 PECI Temperature", "CPU Proximity Temperature", \ 777 "CPU Core 2 PECI Temperature", "Intel GPU Temperature", \ 778 "CPU System Agent Core PECI Temperature", \ 779 "CPU Core Temperature", "CPU PECI DTS Temperature", \ 780 "Memory Proximity Temperature", \ 781 "Platform Controller Hub Die Temperature", \ 782 "Wireless Module Proximity Temperature", \ 783 "Thunderbolt Diode Temperature", \ 784 "Logic Board temperature", } 785 786 #define ASMC_MP1_TEMPS { "TA0P", \ 787 "TCAH", "TCBH", \ 788 "TC0P", "TC0C", "TC1C", \ 789 "TC2C", "TC3C", "THTG", \ 790 "TH0P", "TH1P", \ 791 "TH2P", "TH3P", \ 792 "TM0P", "TM1P", "TM2P", \ 793 "TM8P", "TM9P", "TMAP", \ 794 "TM0S", "TM1S", "TM2P", "TM3S", \ 795 "TM8S", "TM9S", "TMAS", "TMBS", \ 796 "TN0H", "TS0C", \ 797 "Tp0C", "Tp1C", "Tv0S", "Tv1S", NULL } 798 799 #define ASMC_MP1_TEMPNAMES { "ambient", \ 800 "cpu_a_heatsink", "cpu_b_heatsink", \ 801 "cpu_a_proximity", "cpu_core0", "cpu_core1", \ 802 "cpu_core2", "cpu_core3", "THTG", \ 803 "hdd_bay0", "hdd_bay1", \ 804 "hdd_bay2", "hdd_bay3", \ 805 "memory_card_a_proximity0", \ 806 "memory_card_a_proximity1", \ 807 "memory_card_a_proximity2", \ 808 "memory_card_b_proximity0", \ 809 "memory_card_b_proximity1", \ 810 "memory_card_b_proximity2", \ 811 "memory_card_a_slot0", \ 812 "memory_card_a_slot1", \ 813 "memory_card_a_slot2", \ 814 "memory_card_a_slot3", \ 815 "memory_card_b_slot0", \ 816 "memory_card_b_slot1", \ 817 "memory_card_b_slot2", \ 818 "memory_card_b_slot3", \ 819 "mch_heatsink", "expansion_slots", \ 820 "power_supply_loc0", "power_supply_loc1", \ 821 "Tv0S", "Tv1S", } 822 823 #define ASMC_MP1_TEMPDESCS { "Ambient Air", \ 824 "CPU A Heatsink", "CPU B Heatsink", \ 825 "CPU A Proximity", \ 826 "CPU Core 1", "CPU Core 2", \ 827 "CPU Core 3", "CPU Core 4", "THTG", \ 828 "Hard Drive Bay 1", "Hard Drive Bay 2", \ 829 "Hard Drive Bay 3", "Hard Drive Bay 4", \ 830 "Memory Riser A, Proximity 1", \ 831 "Memory Riser A, Proximity 2", \ 832 "Memory Riser A, Proximity 3", \ 833 "Memory Riser B, Proximity 1", \ 834 "Memory Riser B, Proximity 2", \ 835 "Memory Riser B, Proximity 3", \ 836 "Memory Riser A, Slot 1", \ 837 "Memory Riser A, Slot 2", \ 838 "Memory Riser A, Slot 3", \ 839 "Memory Riser A, Slot 4", \ 840 "Memory Riser B, Slot 1", \ 841 "Memory Riser B, Slot 2", \ 842 "Memory Riser B, Slot 3", \ 843 "Memory Riser B, Slot 4", \ 844 "MCH Heatsink", "Expansion Slots", \ 845 "Power Supply, Location 1", \ 846 "Power Supply, Location 2", \ 847 "Tv0S", "Tv1S", } 848 849 #define ASMC_MP31_TEMPS { "TA0P", \ 850 "TC0C", "TC0D", "TC0P", \ 851 "TC1C", "TC1D", \ 852 "TC2C", "TC2D", \ 853 "TC3C", "TC3D", \ 854 "TCAG", "TCAH", "TCBG", "TCBH", \ 855 "TH0P", "TH1P", "TH2P", "TH3P", \ 856 "TM0P", "TM0S", "TM1P", "TM1S", \ 857 "TM2P", "TM2S", "TM3S", \ 858 "TM8P", "TM8S", "TM9P", "TM9S", \ 859 "TMAP", "TMAS", "TMBS", \ 860 "TN0C", "TN0D", "TN0H", \ 861 "TS0C", \ 862 "Tp0C", "Tp1C", \ 863 "Tv0S", "Tv1S", NULL } 864 865 #define ASMC_MP31_TEMPNAMES { "ambient", \ 866 "cpu_core0", "cpu_diode0", "cpu_a_proximity", \ 867 "cpu_core1", "cpu_diode1", \ 868 "cpu_core2", "cpu_diode2", \ 869 "cpu_core3", "cpu_diode3", \ 870 "cpu_a_pkg", "cpu_a_heatsink", \ 871 "cpu_b_pkg", "cpu_b_heatsink", \ 872 "hdd_bay0", "hdd_bay1", \ 873 "hdd_bay2", "hdd_bay3", \ 874 "mem_riser_a_prox0", "mem_riser_a_slot0", \ 875 "mem_riser_a_prox1", "mem_riser_a_slot1", \ 876 "mem_riser_a_prox2", "mem_riser_a_slot2", \ 877 "mem_riser_a_slot3", \ 878 "mem_riser_b_prox0", "mem_riser_b_slot0", \ 879 "mem_riser_b_prox1", "mem_riser_b_slot1", \ 880 "mem_riser_b_prox2", "mem_riser_b_slot2", \ 881 "mem_riser_b_slot3", \ 882 "northbridge_core", "northbridge_diode", \ 883 "northbridge_heatsink", \ 884 "expansion_slots", \ 885 "power_supply0", "power_supply1", \ 886 "vrm0", "vrm1", } 887 888 #define ASMC_MP31_TEMPDESCS { "Ambient Air", \ 889 "CPU Core 1", "CPU Diode 1", \ 890 "CPU A Proximity", \ 891 "CPU Core 2", "CPU Diode 2", \ 892 "CPU Core 3", "CPU Diode 3", \ 893 "CPU Core 4", "CPU Diode 4", \ 894 "CPU A Package", "CPU A Heatsink", \ 895 "CPU B Package", "CPU B Heatsink", \ 896 "Hard Drive Bay 1", "Hard Drive Bay 2", \ 897 "Hard Drive Bay 3", "Hard Drive Bay 4", \ 898 "Memory Riser A, Proximity 1", \ 899 "Memory Riser A, Slot 1", \ 900 "Memory Riser A, Proximity 2", \ 901 "Memory Riser A, Slot 2", \ 902 "Memory Riser A, Proximity 3", \ 903 "Memory Riser A, Slot 3", \ 904 "Memory Riser A, Slot 4", \ 905 "Memory Riser B, Proximity 1", \ 906 "Memory Riser B, Slot 1", \ 907 "Memory Riser B, Proximity 2", \ 908 "Memory Riser B, Slot 2", \ 909 "Memory Riser B, Proximity 3", \ 910 "Memory Riser B, Slot 3", \ 911 "Memory Riser B, Slot 4", \ 912 "Northbridge Core", "Northbridge Diode", \ 913 "Northbridge Heatsink", \ 914 "Expansion Slots", \ 915 "Power Supply 1", "Power Supply 2", \ 916 "VRM 1", "VRM 2", } 917 918 #define ASMC_MP2_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 919 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 920 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 921 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 922 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 923 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 924 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \ 925 NULL } 926 927 #define ASMC_MP2_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 928 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 929 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 930 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 931 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 932 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 933 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 934 935 #define ASMC_MP2_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 936 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 937 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 938 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 939 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 940 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 941 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 942 943 #define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 944 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 945 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 946 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 947 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 948 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 949 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 950 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 951 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 952 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 953 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 954 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 955 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 956 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 957 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \ 958 NULL } 959 960 #define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \ 961 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 962 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 963 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 964 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 965 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 966 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 967 "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \ 968 "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \ 969 "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \ 970 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 971 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 972 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 973 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 974 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 975 976 #define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 977 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 978 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 979 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 980 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 981 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 982 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 983 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 984 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 985 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 986 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 987 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 988 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 989 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 990 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 991 992 #define ASMC_MP6_TEMPS { "TA0P", "TA1P", "TC0P", "TG0D", "TG0P", \ 993 "TG1D", "TG1P", "TM0P", "TM1P", NULL } 994 995 #define ASMC_MP6_TEMPNAMES { "ambient_air_1", "ambient_air_2", \ 996 "cpu_proximity", "gpu_diode_1", \ 997 "gpu_proximity_1", "gpu_diode_2", \ 998 "gpu_proximity_2", "mem_proximity_1", \ 999 "mem_proximity_2" } 1000 1001 #define ASMC_MP6_TEMPDESCS { "Ambient Air 1", "Ambient Air 2", \ 1002 "CPU Proximity", "GPU Diode 1", \ 1003 "GPU Proximity 1", "GPU Diode 2", \ 1004 "GPU Proximity 2", "Memory Bank A", \ 1005 "Memory Bank B" } 1006 1007 #define ASMC_MBA_TEMPS { "TB0T", NULL } 1008 #define ASMC_MBA_TEMPNAMES { "enclosure" } 1009 #define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" } 1010 1011 #define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \ 1012 "TC0D", "TC0E", "TC0P", NULL } 1013 1014 #define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \ 1015 "TC0D", "TC0E", "TC0P" } 1016 1017 #define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \ 1018 "TC0D", "TC0E", "TC0P" } 1019 1020 #define ASMC_MBA4_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 1021 "TC0D", "TC0E", "TC0F", "TC0P", \ 1022 "TC1C", "TC2C", "TCGC", "TCSA", \ 1023 "TH0F", "TH0J", "TH0O", "TH0o", \ 1024 "TM0P", "TPCD", "Ta0P", "Th1H", \ 1025 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 1026 NULL } 1027 1028 #define ASMC_MBA4_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TC0C", \ 1029 "TC0D", "TC0E", "TC0F", "TC0P", \ 1030 "TC1C", "TC2C", "TCGC", "TCSA", \ 1031 "TH0F", "TH0J", "TH0O", "TH0o", \ 1032 "TM0P", "TPCD", "Ta0P", "Th1H", \ 1033 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 1034 NULL } 1035 1036 #define ASMC_MBA4_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TC0C", \ 1037 "TC0D", "TC0E", "TC0F", "TC0P", \ 1038 "TC1C", "TC2C", "TCGC", "TCSA", \ 1039 "TH0F", "TH0J", "TH0O", "TH0o", \ 1040 "TM0P", "TPCD", "Ta0P", "Th1H", \ 1041 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 1042 NULL } 1043 1044 #define ASMC_MBA5_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 1045 "TC0D", "TC0E", "TC0F", "TC0P", \ 1046 "TC1C", "TC2C", "TCGC", "TCSA", \ 1047 "TCXC", "THSP", "TM0P", "TPCD", \ 1048 "Ta0P", "Th1H", "Tm0P", "Tm1P", \ 1049 "Ts0P", "Ts0S", NULL } 1050 1051 #define ASMC_MBA5_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", "TC0C", \ 1052 "cpudiode", "cputemp1", "cputemp2", "cpuproximity", \ 1053 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 1054 "TCXC", "THSP", "memorybank", "pchdie", \ 1055 "Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \ 1056 "palmrest", "memoryproximity" } 1057 1058 #define ASMC_MBA5_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\ 1059 "CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 1060 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 1061 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 1062 "Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \ 1063 "Palm Rest", "Memory Proximity" } 1064 1065 /* 1066 * TODO: validate the temp zones for MBA 6.x ! 1067 */ 1068 #define ASMC_MBA6_TEMPS { "TB0T", "TB1T", "TB2T", \ 1069 "TC0E", "TC0F", "TC0P", \ 1070 "TC1C", "TC2C", "TCGC", "TCSA", \ 1071 "TCXC", "THSP", "TM0P", "TPCD", \ 1072 "Ta0P", "Th1H", "Tm0P", \ 1073 "Ts0P", "Ts0S", NULL } 1074 1075 #define ASMC_MBA6_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \ 1076 "cputemp1", "cputemp2", "cpuproximity", \ 1077 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 1078 "TCXC", "THSP", "memorybank", "pchdie", \ 1079 "Ta0P", "heatpipe", "mainboardproximity1", \ 1080 "palmrest", "memoryproximity" } 1081 1082 #define ASMC_MBA6_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \ 1083 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 1084 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 1085 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 1086 "Ta0P", "Heatpipe", "Mainboard Proximity 1", \ 1087 "Palm Rest", "Memory Proximity" } 1088 1089 1090 #define ASMC_MBA7_TEMPS { "TB0T", "TB1T", "TB2T", \ 1091 "TC0E", "TC0F", "TC0P", \ 1092 "TC1C", "TC2C", \ 1093 "TCGC", "TCSA", "TCXC", \ 1094 "THSP", "TM0P", "TPCD", \ 1095 "TW0P" "Ta0P", "Th1H", \ 1096 "Tm0P", "Ts0P", "Ts0S", NULL } 1097 1098 #define ASMC_MBA7_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \ 1099 "cputemp1", "cputemp2", "cpuproximity", \ 1100 "cpucore1", "cpucore2", \ 1101 "pecigpu", "pecisa", "pecicpu", \ 1102 "thunderboltproximity", "memorybank", "pchdie", \ 1103 "wirelessproximity", "airflowproximity", "heatpipe", \ 1104 "mainboardproximity", "palmrest", "memoryproximity" } 1105 1106 #define ASMC_MBA7_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \ 1107 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 1108 "CPU Core 1", "CPU Core 2", \ 1109 "PECI GPU", "PECI SA", "PECI CPU", \ 1110 "Thunderbolt Proximity", "Memory Bank A", "PCH Die", \ 1111 "Wireless Proximity", "Airflow Proxmity", "Heatpipe", \ 1112 "Mainboard Proximity", "Palm Rest", "Memory Proximity" } 1113