1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 #define ASMC_MAXFANS 6 31 32 struct asmc_softc { 33 device_t sc_dev; 34 struct mtx sc_mtx; 35 int sc_nfan; 36 int sc_nkeys; 37 int16_t sms_rest_x; 38 int16_t sms_rest_y; 39 int16_t sms_rest_z; 40 struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1]; 41 struct sysctl_oid *sc_temp_tree; 42 struct sysctl_oid *sc_sms_tree; 43 struct sysctl_oid *sc_light_tree; 44 const struct asmc_model *sc_model; 45 int sc_rid_port; 46 int sc_rid_irq; 47 struct resource *sc_ioport; 48 struct resource *sc_irq; 49 void *sc_cookie; 50 int sc_sms_intrtype; 51 struct taskqueue *sc_sms_tq; 52 struct task sc_sms_task; 53 uint8_t sc_sms_intr_works; 54 struct cdev *sc_kbd_bkl; 55 uint32_t sc_kbd_bkl_level; 56 }; 57 58 /* 59 * Data port. 60 */ 61 #define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00) 62 #define ASMC_DATAPORT_WRITE(sc, val) \ 63 bus_write_1(sc->sc_ioport, 0x00, val) 64 #define ASMC_STATUS_MASK 0x0f 65 66 /* 67 * Command port. 68 */ 69 #define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04) 70 #define ASMC_CMDPORT_WRITE(sc, val) \ 71 bus_write_1(sc->sc_ioport, 0x04, val) 72 #define ASMC_CMDREAD 0x10 73 #define ASMC_CMDWRITE 0x11 74 75 /* 76 * Interrupt port. 77 */ 78 #define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f) 79 80 /* Number of keys */ 81 #define ASMC_NKEYS "#KEY" /* RO; 4 bytes */ 82 83 /* Query the ASMC revision */ 84 #define ASMC_KEY_REV "REV " /* RO: 6 bytes */ 85 86 /* 87 * Fan control via SMC. 88 */ 89 #define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */ 90 #define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */ 91 #define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */ 92 #define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */ 93 #define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */ 94 #define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */ 95 #define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */ 96 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */ 97 98 /* 99 * Sudden Motion Sensor (SMS). 100 */ 101 #define ASMC_SMS_INIT1 0xe0 102 #define ASMC_SMS_INIT2 0xf8 103 #define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */ 104 #define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */ 105 #define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */ 106 #define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */ 107 #define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */ 108 #define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */ 109 #define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */ 110 #define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */ 111 #define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */ 112 #define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */ 113 #define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */ 114 #define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */ 115 116 /* 117 * Light Sensor. 118 */ 119 #define ASMC_ALSL_INT2A 0x2a /* Ambient Light related Interrupt */ 120 121 /* 122 * Keyboard backlight. 123 */ 124 #define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */ 125 #define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */ 126 #define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */ 127 128 /* 129 * Clamshell. 130 */ 131 #define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */ 132 133 /* 134 * Auto power on / Wake-on-LAN. 135 */ 136 #define ASMC_KEY_AUPO "AUPO" /* RW; 1 byte */ 137 138 /* 139 * Interrupt keys. 140 */ 141 #define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */ 142 143 /* 144 * Temperatures. 145 * 146 * First for MacBook, second for MacBook Pro, third for Intel Mac Mini, 147 * fourth the Mac Pro 8-core and finally the MacBook Air. 148 * 149 */ 150 /* maximum array size for temperatures including the last NULL */ 151 #define ASMC_TEMP_MAX 80 152 #define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \ 153 "TM0P", NULL } 154 #define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \ 155 "northbridge2", "heatsink1", \ 156 "heatsink2", "memory", } 157 #define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \ 158 "Northbridge Point 1", \ 159 "Northbridge Point 2", "Heatsink 1", \ 160 "Heatsink 2", "Memory Bank A", } 161 162 #define ASMC_MB31_TEMPS { "TB0T", "TN0P", "Th0H", "Th1H", \ 163 "TM0P", NULL } 164 165 #define ASMC_MB31_TEMPNAMES { "enclosure", "northbridge1", \ 166 "heatsink1", "heatsink2", \ 167 "memory", } 168 169 #define ASMC_MB31_TEMPDESCS { "Enclosure Bottomside", \ 170 "Northbridge Point 1", \ 171 "Heatsink 1","Heatsink 2" \ 172 "Memory Bank A", } 173 174 #define ASMC_MB71_TEMPS { "TB0T", "TB1T", "TB2T", "TC0D", "TC0P", \ 175 "TH0P", "TN0D", "TN0P", "TN0S", "TN1D", \ 176 "TN1E", "TN1F", "TN1G", "TN1S", "Th1H", \ 177 "Ts0P", "Ts0S", NULL } 178 179 #define ASMC_MB71_TEMPNAMES { "enclosure_bottom0", "battery_1", "battery_2", "cpu_package", "cpu_proximity", \ 180 "hdd_bay", "northbridge0_diode", "northbridge0_proximity", "TN0S", "mpc_die2", \ 181 "TN1E", "TN1F", "TN1G", "TN1S", "heatsink1", \ 182 "palm_rest", "memory_proximity", } 183 184 #define ASMC_MB71_TEMPDESCS { "Enclosure Bottom 0", "Battery 1", "Battery 2", "CPU Package", "CPU Proximity", \ 185 "HDD Bay", "Northbridge Diode", "Northbridge Proximity", "TN0S", "MPC Die 2", \ 186 "TN1E", "TN1F", "TN1G", "TN1S", "Heatsink 1", \ 187 "Palm Rest", "Memory Proximity", } 188 189 #define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \ 190 "TG0H", "TG0P", "TG0T", NULL } 191 192 #define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \ 193 "heatsink2", "memory", "graphics", \ 194 "graphicssink", "unknown", } 195 196 #define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \ 197 "Heatsink 1", "Heatsink 2", \ 198 "Memory Controller", \ 199 "Graphics Chip", "Graphics Heatsink", \ 200 "Unknown", } 201 202 #define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \ 203 "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \ 204 "TTF0", "TW0P", NULL } 205 206 #define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \ 207 "heatsink3", "memory", "graphicssink", \ 208 "graphics", "cpu", "cpu2", "unknown1", \ 209 "unknown2", "wireless", } 210 211 #define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \ 212 "Main Heatsink 1", "Main Heatsink 2", \ 213 "Main Heatsink 3", \ 214 "Memory Controller", \ 215 "Graphics Chip Heatsink", \ 216 "Graphics Chip Diode", \ 217 "CPU Temperature Diode", "CPU Point 2", \ 218 "Unknown", "Unknown", \ 219 "Wireless Module", } 220 221 #define ASMC_MBP51_TEMPS { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", \ 222 "TC0F", "TC0P", "TG0D", "TG0F", "TG0H", \ 223 "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", \ 224 "TTF0", "Th2H", "Tm0P", "Ts0P", "Ts0S", \ 225 NULL } 226 227 #define ASMC_MBP51_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 228 "enclosure_bottom_2", "enclosure_bottom_3", \ 229 "cpu_diode", "cpu", \ 230 "cpu_pin", "gpu_diode", \ 231 "gpu", "gpu_heatsink", \ 232 "gpu_pin", "gpu_transistor", \ 233 "gpu_2_heatsink", "northbridge_diode", \ 234 "northbridge_pin", "unknown", \ 235 "heatsink_2", "memory_controller", \ 236 "pci_express_slot_pin", "pci_express_slot_unk" } 237 238 #define ASMC_MBP51_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 239 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 240 "CPU Diode", "CPU ???", \ 241 "CPU Pin", "GPU Diode", \ 242 "GPU ???", "GPU Heatsink", \ 243 "GPU Pin", "GPU Transistor", \ 244 "GPU 2 Heatsink", "Northbridge Diode", \ 245 "Northbridge Pin", "Unknown", \ 246 "Heatsink 2", "Memory Controller", \ 247 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 248 249 #define ASMC_MBP62_TEMPS { "TB0T", "TB1T", "TB2T", \ 250 "TC0C", "TC0D", "TC0P", \ 251 "TC1C", "TG0D", "TG0P", \ 252 "TG0T", "TMCD", "TP0P", \ 253 "TPCD", "Th1H", "Th2H", \ 254 "Tm0P", "Ts0P", "Ts0S" } 255 256 #define ASMC_MBP62_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 257 "enclosure_bottom_2", "cpu0", \ 258 "cpu_diode", "cpu_proximity", \ 259 "cpu1", "gpu_diode", \ 260 "gpu_pin", "gpu_transistor", \ 261 "TMCD", "pch_controller_proximity", \ 262 "pch_die", "heatsink1", \ 263 "heatsink2", "memory-controller", \ 264 "palmrest", "memoryproximity" } 265 266 #define ASMC_MBP62_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 267 "Enclosure Bottom 2", "CPU 0", \ 268 "CPU Diode", "CPU Proximity", \ 269 "CPU 1", "GPU Diode", \ 270 "GPU Pin", "GPU Transistor", \ 271 "TMCD", "PCH Controller Proximity", \ 272 "PCH Die", "Heat Sink 1", \ 273 "Heat Sink 2", "Memory Controller", \ 274 "Palm Rest", "Memory Proximity" } 275 276 #define ASMC_MBP55_TEMPS { "TB0T", "TB1T", \ 277 "TB2T", "TB3T", \ 278 "TC0D", "TC0P", \ 279 "TN0D", "TN0P", \ 280 "TTF0", \ 281 "Th0H", "Th1H", "ThFH", \ 282 "Ts0P", "Ts0S", \ 283 NULL } 284 285 #define ASMC_MBP55_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 286 "enclosure_bottom_2", "enclosure_bottom_3", \ 287 "cpu_diode", "cpu_pin", \ 288 "northbridge_diode", "northbridge_pin", \ 289 "unknown", \ 290 "heatsink_0", "heatsink_1", "heatsink_2", \ 291 "pci_express_slot_pin", "pci_express_slot_unk" } 292 293 #define ASMC_MBP55_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 294 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 295 "CPU Diode", "CPU Pin", \ 296 "Northbridge Diode", "Northbridge Pin", \ 297 "Unknown", \ 298 "Heatsink 0", "Heatsink 1", "Heatsink 2", \ 299 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 300 301 #define ASMC_MBP81_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 302 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 303 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 304 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 305 "Ts0S", NULL } 306 307 #define ASMC_MBP81_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 308 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 309 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 310 "TP0P", "TPCD", "wireless", "Th1H", "Ts0P", \ 311 "Ts0S" } 312 313 #define ASMC_MBP81_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 314 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 315 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 316 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 317 "Ts0S" } 318 319 #define ASMC_MBP82_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 320 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 321 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 322 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 323 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 324 "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL } 325 326 #define ASMC_MBP82_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 327 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 328 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 329 "TCTD", "graphics", "TG0P", "THSP", "TM0S", \ 330 "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \ 331 "Th2H", "memory", "Ts0P", "Ts0S" } 332 333 #define ASMC_MBP82_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 334 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 335 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 336 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 337 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 338 "Th2H", "Tm0P", "Ts0P", "Ts0S" } 339 340 #define ASMC_MBP83_TEMPS { "ALSL", "F0Ac", "F1Ac", "IB0R", "IC0R", \ 341 "ID0R", "IG0R", "IO0R", "PCPC", "PCPG", \ 342 "PCPT", "PD0R", "TB1T", "TB2T", "TC0C", \ 343 "TC0D", "TC0P", "TC1C", "TC2C", "TC3C", \ 344 "TC4C", "TG0D", "TG0P", "THSP", "TP0P", \ 345 "TPCD", "Th1H", "Th2H", "Tm0P", "Ts0P", \ 346 "VC0C", "VD0R", "VG0C", "VN0C", "VP0R", NULL } 347 348 #define ASMC_MBP83_TEMPNAMES { "ambient_light", "fan_leftside", "fan_rightside", \ 349 "battery_current", "cpu_vcorevtt", "dc_current", \ 350 "gpu_voltage", "other", "cpu_package_core", \ 351 "cpu_package_gpu", "cpu_package_total", "dc_in", \ 352 "battery_1", "battery_2", "cpu_die_digital", \ 353 "cpu_die_analog", "cpu_proximity", "cpu_core_1", \ 354 "cpu_core_2", "cpu_core_3", "cpu_core_4", "gpu_die_analog", \ 355 "gpu_proximity", "thunderbolt", "platform_controller", \ 356 "pch_die_digital", "right_fin_stack", "left_fin_stack", \ 357 "dc_in_air_flow", "palm_rest", "cpu_vcore", "dc_in_voltage", \ 358 "gpu_vcore", "intel_gpu_vcore", "pbus_voltage" } 359 360 #define ASMC_MBP83_TEMPDESCS { "Ambient Light", "Fan Leftside", "Fan Rightside", \ 361 "Battery BMON Current", "CPU VcoreVTT", "DC In AMON Current", \ 362 "GPU Voltage", "Other 5V 3V", "CPU Package Core", \ 363 "CPU Package GPU", "CPU Package Total", "DC In", \ 364 "Battery Sensor 1", "Battery Sensor 2", "CPU Die Digital", \ 365 "CPU Die Analog", "CPU Proximity", "CPU Core 1 DTS", \ 366 "CPU Core 2 DTS", "CPU Core 3 DTS", "CPU Core 4 DTS", \ 367 "GPU Die Analog", "GPU Proximity", "Thunderbolt Proximity", \ 368 "Platform Controller Hub", "PCH Die Digital", \ 369 "Right Fin Stack Proximity", "Left Fin Stack Proximity", \ 370 "DC In Proximity Air Flow", "Palm Rest", "CPU VCore", \ 371 "DC In Voltage", "GPU VCore", "Intel GPU VCore", "PBus Voltage" } 372 373 #define ASMC_MBP91_TEMPS { "TA0P", "TB0T", "TB1T", "TB2T", "TC0E", \ 374 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 375 "TC4C", "TCGC", "TCSA", "TCXC", "TG0D", \ 376 "TG0P", "TG1D", "TG1F", "TG1d", "TGTC", \ 377 "TGTD", "TM0P", "TM0S", "TP0P", "TPCD", \ 378 "Th1H", "Th2H", "Ts0P", "Ts0S", "Tsqf", NULL } 379 380 #define ASMC_MBP91_TEMPNAMES { "ambient", "enclosure_bottom_1", "enclosure_bottom_2", \ 381 "enclosure_bottom_3", "cpu_die_peci_0", "cpu_die_peci_1", \ 382 "cpu_proximity", "cpu_core_1", "cpu_core_2", "cpu_core_3", \ 383 "cpu_core_4", "intel_gpu", "cpu_sys_agent", \ 384 "cpu_core_peci", "gpu_analog", \ 385 "gpu_proximity", "geforce_gpu_digital", "tg1f", \ 386 "gpu_2_die", "tgtc", "tgtd", "memory_proximity", \ 387 "mem_bank_a1", "platform_ctrl_hub", "pch_digital", \ 388 "main_heatsink_r", "main_heatsink_l", "palm_rest", \ 389 "bottom_skin", "tsqf" } 390 391 #define ASMC_MBP91_TEMPDESCS { "Ambient", "Enclosure Bottom 1", "Enclosure Bottom 2", \ 392 "Enclosure Bottom 3", "CPU Die PECI 0", "CPU Die PECI 1", \ 393 "CPU Proximity", "CPU Core 1", "CPU Core 2", \ 394 "CPU Core 3", "CPU Core 4", "Intel GPU", \ 395 "CPU System Agent Core", "CPU Core - PECI", \ 396 "GPU Die - Analog", "GPU Proximity", \ 397 "GeForce GPU Die - Digital", "TG1F", "GPU 2 Die" \ 398 "TGTC", "TGTD", "Memory Proximity", \ 399 "Memory Bank A1", "Platform Controller Hub", "PCH Die - Digital", \ 400 "Main Heatsink Right", "Main Heatsink Left", "Palm Rest", \ 401 "Bottom Skin", "Tsqf" } 402 403 #define ASMC_MBP92_TEMPS { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 404 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 405 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 406 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 407 "TPCD", NULL } 408 409 #define ASMC_MBP92_TEMPNAMES { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 410 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 411 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 412 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 413 "TPCD" } 414 415 #define ASMC_MBP92_TEMPDESCS { "Palm Rest", "Memory Proximity", "Airflow 1", \ 416 "Battery 1", "Battery 2", "Battery TS_MAX", \ 417 "CPU Core 1", "CPU Core 2", "CPU1", "CPU1", \ 418 "TC0J", "CPU 1 Proximity", "TCFC", \ 419 "PECI GPU", "PECI SA", "TCTD", "PECI CPU", \ 420 "GPU Die", "Memory Bank A1", "Memory Module A1", \ 421 "PCH Die" } 422 423 #define ASMC_MBP112_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 424 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 425 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 426 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 427 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 428 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 429 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 430 "Ts1S", NULL } 431 432 #define ASMC_MBP112_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 433 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 434 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 435 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 436 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 437 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 438 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 439 "Ts1S" } 440 441 #define ASMC_MBP112_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 442 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 443 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 444 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 445 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 446 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 447 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 448 "Ts1S" } 449 450 #define ASMC_MBP113_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 451 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 452 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 453 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 454 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 455 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 456 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 457 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 458 "Ts1S", NULL } 459 460 #define ASMC_MBP113_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 461 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 462 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 463 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 464 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 465 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 466 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 467 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 468 "Ts1S" } 469 470 #define ASMC_MBP113_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 471 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 472 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 473 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 474 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 475 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 476 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 477 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 478 "Ts1S" } 479 480 #define ASMC_MBP114_TEMPS { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 481 "IO3R", "IO5R", "IM0C", "IC1C", "IC2C", \ 482 "IC3C", "ILDC", "IBLC", "IAPC", "IHSC", \ 483 "ICMC", "TC0P", "TP0P", "TM0P", \ 484 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 485 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 486 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 487 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 488 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 489 "PCPG", "PCPT", "PSTR", "PDTR", NULL } 490 491 #define ASMC_MBP114_TEMPNAMES { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 492 "IO3R", "IO5R", "IM0C", "IC1C", "IC2C", \ 493 "IC3C", "ILDC", "IBLC", "IAPC", "IHSC", \ 494 "ICMC", "TC0P", "TP0P", "TM0P", \ 495 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 496 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 497 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 498 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 499 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 500 "PCPG", "PCPT", "PSTR", "PDTR" } 501 502 #define ASMC_MBP114_TEMPDESCS { "CPU High (CPU, I/O)", "DC In", "SSD", "Charger (BMON)", "CPU", \ 503 "Other 3.3V", "Other 5V", "Memory", "Platform Controller Hub Core", "CPU Load Current Monitor", \ 504 "CPU DDR", "LCD Panel", "LCD Backlight", "Airport", "Thunderbolt", \ 505 "S2", "CPU Proximity", "Platform Controller Hub", "Memory Proximity", "Air Flow Proximity", \ 506 "Left Fin Stack", "Right Fin Stack", "Airport Proximity", "Palm Rest", "Palm Rest Actuator", \ 507 "Battery Max", "Battery Sensor 1", "Battery Sensor 2", "SSD A", "SSD B", \ 508 "CPU Core 1", "CPU Core 2", "CPU Core 3", "CPU Core 4", "CPU PECI Die", \ 509 "Intel GPU", "Platform Controller Hub PECI", "CPU System Agent Core", "CPU VCore", "DC In", \ 510 "Pbus", "Ambient Light", "Leftside", "Rightside", "CPU Package Core", \ 511 "CPU Package GPU", "CPU Package Total", "System Total", "DC In" } 512 513 /* MacBookPro11,5 - same as 11,4 but without IBLC, ICMC, and IC2C keys */ 514 #define ASMC_MBP115_TEMPS { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 515 "IO3R", "IO5R", "IM0C", "IC1C", \ 516 "IC3C", "ILDC", "IAPC", "IHSC", \ 517 "TC0P", "TP0P", "TM0P", \ 518 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 519 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 520 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 521 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 522 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 523 "PCPG", "PCPT", "PSTR", "PDTR", NULL } 524 525 526 #define ASMC_MBP115_TEMPNAMES { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 527 "IO3R", "IO5R", "IM0C", "IC1C", \ 528 "IC3C", "ILDC", "IAPC", "IHSC", \ 529 "TC0P", "TP0P", "TM0P", \ 530 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 531 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 532 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 533 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 534 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 535 "PCPG", "PCPT", "PSTR", "PDTR" } 536 537 #define ASMC_MBP115_TEMPDESCS { "CPU High (CPU, I/O)", "DC In", "SSD", "Charger (BMON)", "CPU", \ 538 "Other 3.3V", "Other 5V", "Memory", "Platform Controller Hub Core", \ 539 "CPU DDR", "LCD Panel", "Airport", "Thunderbolt", \ 540 "CPU Proximity", "Platform Controller Hub", "Memory Proximity", "Air Flow Proximity", \ 541 "Left Fin Stack", "Right Fin Stack", "Airport Proximity", "Palm Rest", "Palm Rest Actuator", \ 542 "Battery Max", "Battery Sensor 1", "Battery Sensor 2", "SSD A", "SSD B", \ 543 "CPU Core 1", "CPU Core 2", "CPU Core 3", "CPU Core 4", "CPU PECI Die", \ 544 "Intel GPU", "Platform Controller Hub PECI", "CPU System Agent Core", "CPU VCore", "DC In", \ 545 "Pbus", "Ambient Light", "Leftside", "Rightside", "CPU Package Core", \ 546 "CPU Package GPU", "CPU Package Total", "System Total", "DC In" } 547 548 #define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL } 549 #define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" } 550 #define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \ 551 "Northbridge Point 2" } 552 553 #define ASMC_MM21_TEMPS { "TA0P", "TC0D", \ 554 "TC0H", "TC0P", \ 555 "TC1P", "TN0P", \ 556 "TN1P", NULL } 557 558 #define ASMC_MM21_TEMPNAMES { "ambient_air", "cpu_die", \ 559 "cpu_heatsink", "cpu_proximity1", \ 560 "cpu_proximity2", "northbridge_proximity1", \ 561 "northbridge_proximity2", } 562 563 #define ASMC_MM21_TEMPDESCS { "Ambient Air Temperature" \ 564 "CPU Die Core Temperature", \ 565 "CPU Heatsink Temperature", \ 566 "CPU Proximity 1 Temperature", \ 567 "CPU Proximity 2 Temperature", \ 568 "Northbridge Proximity 1 Temperature", \ 569 "Northbridge Proximity 2 Temperature", } 570 571 #define ASMC_MM31_TEMPS { "TC0D", "TC0H", \ 572 "TC0P", "TH0P", \ 573 "TN0D", "TN0P", \ 574 "TW0P", NULL } 575 576 #define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \ 577 "cpu0_proximity", "hdd_bay", \ 578 "northbridge_die", \ 579 "northbridge_proximity", \ 580 "wireless_proximity", } 581 582 #define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \ 583 "CPU0 Heatsink Temperature", \ 584 "CPU0 Proximity Temperature", \ 585 "HDD Bay Temperature", \ 586 "Northbridge Die Core Temperature", \ 587 "Northbridge Proximity Temperature", \ 588 "Wireless Module Proximity Temperature", } 589 590 #define ASMC_MM41_TEMPS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 591 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 592 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 593 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 594 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 595 "TW0P", "Tm0P", "Tp0C", NULL } 596 597 #define ASMC_MM41_TEMPNAMES { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 598 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 599 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 600 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 601 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 602 "TW0P", "Tm0P", "Tp0C", NULL } 603 604 #define ASMC_MM41_TEMPDESCS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 605 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 606 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 607 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 608 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 609 "TW0P", "Tm0P", "Tp0C", NULL } 610 611 #define ASMC_MM52_TEMPS { "TA0P", "TA1P", \ 612 "TC0D", "TC0P", \ 613 "TG0D", "TG1D", \ 614 "TG0P", "TG0M", \ 615 "TI0P", \ 616 "TM0S", "TMBS", \ 617 "TM0P", "TP0P", \ 618 "TPCD", "Tp0C", \ 619 "TW0P", NULL } 620 621 #define ASMC_MM52_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 622 "cpu_die", "cpu_proximity", \ 623 "gpu_diode1", "gpu_diode2", \ 624 "gpu_proximity", "gpu_integrated_switcher", \ 625 "thunderbolt_proximity", \ 626 "memory_slot1", "memory_slot2", \ 627 "memory_proximity", "pch_controller_proximity", \ 628 "pch_controller_die", "pwr_supply", \ 629 "wireless_proximity", } 630 631 #define ASMC_MM52_TEMPDESCS { "Ambient Air Proximity Temperature", \ 632 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 633 "CPU Die Temperature", "CPU Proximity Temperature", \ 634 "GPU Diode 1 Temperature" , "GPU Diode 2 Temperature", \ 635 "GPU Proximity Temperature", \ 636 "Integrated Graphics/GPU Switcher Temperature", \ 637 "Thunderbolt Proximity Temperature", \ 638 "Memory Slot 1 Temperature", \ 639 "Memory Slot 2 Temperature", \ 640 "Memory Slots Proximity Temperature", \ 641 "Platform Controller Hub Proximity Temperature", \ 642 "Platform Controller Hub Die Temperature", \ 643 "Power Supply Temperature", \ 644 "Wireless Module Proximity Temperature", } 645 646 #define ASMC_MM61_TEMPS { "TA0P", "TA1P", \ 647 "TC0D", "TC0G", "TC0P", "TCPG", \ 648 "TI0P", \ 649 "TM0S", "TMBS", "TM0P", \ 650 "TP0P", "TPCD", \ 651 "Tp0C", \ 652 "TW0P", NULL } 653 654 #define ASMC_MM61_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 655 "cpu_die", "TC0G", "cpu_proximity", "TCPG", \ 656 "thunderbolt_proximity", \ 657 "memory_slot1", "memory_slot2", "memory_proximity", \ 658 "pch_controller_proximity", "pch_controller_die", \ 659 "pwr_supply", \ 660 "wireless_proximity", NULL } 661 662 #define ASMC_MM61_TEMPDESCS { "Ambient Air Proximity Temperature", \ 663 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 664 "CPU Die Temperature", \ 665 NULL, \ 666 "CPU Proximity Temperature", \ 667 NULL, \ 668 "Thunderbolt Proximity Temperature", \ 669 "Memory Slot 1 Temperature", \ 670 "Memory Slot 2 Temperature", \ 671 "Memory Slots Proximity Temperature", \ 672 "Platform Controller Hub Proximity Temperature", \ 673 "Platform Controller Hub Die Temperature", \ 674 "Power Supply Temperature", \ 675 "Wireless Module Proximity Temperature", NULL } 676 677 #define ASMC_MM62_TEMPS { "TA0P", "TA1P", \ 678 "TC0D", "TC0G", "TC0P", "TCPG", \ 679 "TI0P", \ 680 "TM0S", "TMBS", "TM0P", \ 681 "TP0P", "TPCD", \ 682 "Tp0C", \ 683 "TW0P", NULL } 684 685 #define ASMC_MM62_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 686 "cpu_die", "TC0G", "cpu_proximity", "TCPG", \ 687 "thunderbolt_proximity", \ 688 "memory_slot1", "memory_slot2", "memory_proximity", \ 689 "pch_controller_proximity", "pch_controller_die", \ 690 "pwr_supply", \ 691 "wireless_proximity", NULL } 692 693 #define ASMC_MM62_TEMPDESCS { "Ambient Air Proximity Temperature", \ 694 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 695 "CPU Die Temperature", \ 696 NULL, \ 697 "CPU Proximity Temperature", \ 698 NULL, \ 699 "Thunderbolt Proximity Temperature", \ 700 "Memory Slot 1 Temperature", \ 701 "Memory Slot 2 Temperature", \ 702 "Memory Slots Proximity Temperature", \ 703 "Platform Controller Hub Proximity Temperature", \ 704 "Platform Controller Hub Die Temperature", \ 705 "Power Supply Temperature", \ 706 "Wireless Module Proximity Temperature", NULL } 707 708 #define ASMC_MM71_TEMPS { "TA0p", "TA1p", \ 709 "TA2p", "TC0c", \ 710 "TC0p", "TC1c", \ 711 "TCGc", "TCSc", \ 712 "TCXC", "TCXR", \ 713 "TM0p", "TPCd", \ 714 "TW0p", "Te0T", \ 715 "Tm0P", NULL } 716 717 #define ASMC_MM71_TEMPNAMES { "ambient_air1", "ambient_air2", \ 718 "ambient_air3", "cpu_core1_peci", \ 719 "cpu_proximity", "cpu_core2_peci", \ 720 "intel_gpu", "cpu_sa_core_peci", \ 721 "cpu_core", "cpu_peci_dts", \ 722 "memory_proximity", "pch_controller_die", \ 723 "wireless_proximity", "thunderbolt_diode", \ 724 "logic_board", } 725 726 #define ASMC_MM71_TEMPDESCS { "Ambient Air Temperature 1", \ 727 "Ambient Air Temperature 2", \ 728 "Ambient Air Temperature 3", \ 729 "CPU Core 1 PECI Temperature", "CPU Proximity Temperature", \ 730 "CPU Core 2 PECI Temperature", "Intel GPU Temperature", \ 731 "CPU System Agent Core PECI Temperature", \ 732 "CPU Core Temperature", "CPU PECI DTS Temperature", \ 733 "Memory Proximity Temperature", \ 734 "Platform Controller Hub Die Temperature", \ 735 "Wireless Module Proximity Temperature", \ 736 "Thunderbolt Diode Temperature", \ 737 "Logic Board temperature", } 738 739 #define ASMC_MP1_TEMPS { "TA0P", \ 740 "TCAH", "TCBH", \ 741 "TC0P", "TC0C", "TC1C", \ 742 "TC2C", "TC3C", "THTG", \ 743 "TH0P", "TH1P", \ 744 "TH2P", "TH3P", \ 745 "TM0P", "TM1P", "TM2P", \ 746 "TM8P", "TM9P", "TMAP", \ 747 "TM0S", "TM1S", "TM2P", "TM3S", \ 748 "TM8S", "TM9S", "TMAS", "TMBS", \ 749 "TN0H", "TS0C", \ 750 "Tp0C", "Tp1C", "Tv0S", "Tv1S", NULL } 751 752 #define ASMC_MP1_TEMPNAMES { "ambient", \ 753 "cpu_a_heatsink", "cpu_b_heatsink", \ 754 "cpu_a_proximity", "cpu_core0", "cpu_core1", \ 755 "cpu_core2", "cpu_core3", "THTG", \ 756 "hdd_bay0", "hdd_bay1", \ 757 "hdd_bay2", "hdd_bay3", \ 758 "memory_card_a_proximity0", \ 759 "memory_card_a_proximity1", \ 760 "memory_card_a_proximity2", \ 761 "memory_card_b_proximity0", \ 762 "memory_card_b_proximity1", \ 763 "memory_card_b_proximity2", \ 764 "memory_card_a_slot0", \ 765 "memory_card_a_slot1", \ 766 "memory_card_a_slot2", \ 767 "memory_card_a_slot3", \ 768 "memory_card_b_slot0", \ 769 "memory_card_b_slot1", \ 770 "memory_card_b_slot2", \ 771 "memory_card_b_slot3", \ 772 "mch_heatsink", "expansion_slots", \ 773 "power_supply_loc0", "power_supply_loc1", \ 774 "Tv0S", "Tv1S", } 775 776 #define ASMC_MP1_TEMPDESCS { "Ambient Air", \ 777 "CPU A Heatsink", "CPU B Heatsink", \ 778 "CPU A Proximity", \ 779 "CPU Core 1", "CPU Core 2", \ 780 "CPU Core 3", "CPU Core 4", "THTG", \ 781 "Hard Drive Bay 1", "Hard Drive Bay 2", \ 782 "Hard Drive Bay 3", "Hard Drive Bay 4", \ 783 "Memory Riser A, Proximity 1", \ 784 "Memory Riser A, Proximity 2", \ 785 "Memory Riser A, Proximity 3", \ 786 "Memory Riser B, Proximity 1", \ 787 "Memory Riser B, Proximity 2", \ 788 "Memory Riser B, Proximity 3", \ 789 "Memory Riser A, Slot 1", \ 790 "Memory Riser A, Slot 2", \ 791 "Memory Riser A, Slot 3", \ 792 "Memory Riser A, Slot 4", \ 793 "Memory Riser B, Slot 1", \ 794 "Memory Riser B, Slot 2", \ 795 "Memory Riser B, Slot 3", \ 796 "Memory Riser B, Slot 4", \ 797 "MCH Heatsink", "Expansion Slots", \ 798 "Power Supply, Location 1", \ 799 "Power Supply, Location 2", \ 800 "Tv0S", "Tv1S", } 801 802 #define ASMC_MP31_TEMPS { "TA0P", \ 803 "TC0C", "TC0D", "TC0P", \ 804 "TC1C", "TC1D", \ 805 "TC2C", "TC2D", \ 806 "TC3C", "TC3D", \ 807 "TCAG", "TCAH", "TCBG", "TCBH", \ 808 "TH0P", "TH1P", "TH2P", "TH3P", \ 809 "TM0P", "TM0S", "TM1P", "TM1S", \ 810 "TM2P", "TM2S", "TM3S", \ 811 "TM8P", "TM8S", "TM9P", "TM9S", \ 812 "TMAP", "TMAS", "TMBS", \ 813 "TN0C", "TN0D", "TN0H", \ 814 "TS0C", \ 815 "Tp0C", "Tp1C", \ 816 "Tv0S", "Tv1S", NULL } 817 818 #define ASMC_MP31_TEMPNAMES { "ambient", \ 819 "cpu_core0", "cpu_diode0", "cpu_a_proximity", \ 820 "cpu_core1", "cpu_diode1", \ 821 "cpu_core2", "cpu_diode2", \ 822 "cpu_core3", "cpu_diode3", \ 823 "cpu_a_pkg", "cpu_a_heatsink", \ 824 "cpu_b_pkg", "cpu_b_heatsink", \ 825 "hdd_bay0", "hdd_bay1", \ 826 "hdd_bay2", "hdd_bay3", \ 827 "mem_riser_a_prox0", "mem_riser_a_slot0", \ 828 "mem_riser_a_prox1", "mem_riser_a_slot1", \ 829 "mem_riser_a_prox2", "mem_riser_a_slot2", \ 830 "mem_riser_a_slot3", \ 831 "mem_riser_b_prox0", "mem_riser_b_slot0", \ 832 "mem_riser_b_prox1", "mem_riser_b_slot1", \ 833 "mem_riser_b_prox2", "mem_riser_b_slot2", \ 834 "mem_riser_b_slot3", \ 835 "northbridge_core", "northbridge_diode", \ 836 "northbridge_heatsink", \ 837 "expansion_slots", \ 838 "power_supply0", "power_supply1", \ 839 "vrm0", "vrm1", } 840 841 #define ASMC_MP31_TEMPDESCS { "Ambient Air", \ 842 "CPU Core 1", "CPU Diode 1", \ 843 "CPU A Proximity", \ 844 "CPU Core 2", "CPU Diode 2", \ 845 "CPU Core 3", "CPU Diode 3", \ 846 "CPU Core 4", "CPU Diode 4", \ 847 "CPU A Package", "CPU A Heatsink", \ 848 "CPU B Package", "CPU B Heatsink", \ 849 "Hard Drive Bay 1", "Hard Drive Bay 2", \ 850 "Hard Drive Bay 3", "Hard Drive Bay 4", \ 851 "Memory Riser A, Proximity 1", \ 852 "Memory Riser A, Slot 1", \ 853 "Memory Riser A, Proximity 2", \ 854 "Memory Riser A, Slot 2", \ 855 "Memory Riser A, Proximity 3", \ 856 "Memory Riser A, Slot 3", \ 857 "Memory Riser A, Slot 4", \ 858 "Memory Riser B, Proximity 1", \ 859 "Memory Riser B, Slot 1", \ 860 "Memory Riser B, Proximity 2", \ 861 "Memory Riser B, Slot 2", \ 862 "Memory Riser B, Proximity 3", \ 863 "Memory Riser B, Slot 3", \ 864 "Memory Riser B, Slot 4", \ 865 "Northbridge Core", "Northbridge Diode", \ 866 "Northbridge Heatsink", \ 867 "Expansion Slots", \ 868 "Power Supply 1", "Power Supply 2", \ 869 "VRM 1", "VRM 2", } 870 871 #define ASMC_MP2_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 872 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 873 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 874 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 875 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 876 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 877 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \ 878 NULL } 879 880 #define ASMC_MP2_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 881 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 882 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 883 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 884 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 885 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 886 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 887 888 #define ASMC_MP2_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 889 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 890 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 891 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 892 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 893 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 894 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 895 896 #define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 897 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 898 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 899 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 900 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 901 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 902 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 903 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 904 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 905 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 906 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 907 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 908 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 909 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 910 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \ 911 NULL } 912 913 #define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \ 914 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 915 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 916 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 917 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 918 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 919 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 920 "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \ 921 "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \ 922 "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \ 923 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 924 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 925 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 926 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 927 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 928 929 #define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 930 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 931 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 932 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 933 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 934 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 935 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 936 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 937 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 938 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 939 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 940 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 941 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 942 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 943 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 944 945 #define ASMC_MP6_TEMPS { "TA0P", "TA1P", "TC0P", "TG0D", "TG0P", \ 946 "TG1D", "TG1P", "TM0P", "TM1P", NULL } 947 948 #define ASMC_MP6_TEMPNAMES { "ambient_air_1", "ambient_air_2", \ 949 "cpu_proximity", "gpu_diode_1", \ 950 "gpu_proximity_1", "gpu_diode_2", \ 951 "gpu_proximity_2", "mem_proximity_1", \ 952 "mem_proximity_2" } 953 954 #define ASMC_MP6_TEMPDESCS { "Ambient Air 1", "Ambient Air 2", \ 955 "CPU Proximity", "GPU Diode 1", \ 956 "GPU Proximity 1", "GPU Diode 2", \ 957 "GPU Proximity 2", "Memory Bank A", \ 958 "Memory Bank B" } 959 960 #define ASMC_MBA_TEMPS { "TB0T", NULL } 961 #define ASMC_MBA_TEMPNAMES { "enclosure" } 962 #define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" } 963 964 #define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \ 965 "TC0D", "TC0E", "TC0P", NULL } 966 967 #define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \ 968 "TC0D", "TC0E", "TC0P" } 969 970 #define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \ 971 "TC0D", "TC0E", "TC0P" } 972 973 #define ASMC_MBA4_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 974 "TC0D", "TC0E", "TC0F", "TC0P", \ 975 "TC1C", "TC2C", "TCGC", "TCSA", \ 976 "TH0F", "TH0J", "TH0O", "TH0o", \ 977 "TM0P", "TPCD", "Ta0P", "Th1H", \ 978 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 979 NULL } 980 981 #define ASMC_MBA4_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TC0C", \ 982 "TC0D", "TC0E", "TC0F", "TC0P", \ 983 "TC1C", "TC2C", "TCGC", "TCSA", \ 984 "TH0F", "TH0J", "TH0O", "TH0o", \ 985 "TM0P", "TPCD", "Ta0P", "Th1H", \ 986 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 987 NULL } 988 989 #define ASMC_MBA4_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TC0C", \ 990 "TC0D", "TC0E", "TC0F", "TC0P", \ 991 "TC1C", "TC2C", "TCGC", "TCSA", \ 992 "TH0F", "TH0J", "TH0O", "TH0o", \ 993 "TM0P", "TPCD", "Ta0P", "Th1H", \ 994 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 995 NULL } 996 997 #define ASMC_MBA5_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 998 "TC0D", "TC0E", "TC0F", "TC0P", \ 999 "TC1C", "TC2C", "TCGC", "TCSA", \ 1000 "TCXC", "THSP", "TM0P", "TPCD", \ 1001 "Ta0P", "Th1H", "Tm0P", "Tm1P", \ 1002 "Ts0P", "Ts0S", NULL } 1003 1004 #define ASMC_MBA5_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", "TC0C", \ 1005 "cpudiode", "cputemp1", "cputemp2", "cpuproximity", \ 1006 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 1007 "TCXC", "THSP", "memorybank", "pchdie", \ 1008 "Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \ 1009 "palmrest", "memoryproximity" } 1010 1011 #define ASMC_MBA5_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\ 1012 "CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 1013 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 1014 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 1015 "Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \ 1016 "Palm Rest", "Memory Proximity" } 1017 1018 /* 1019 * TODO: validate the temp zones for MBA 6.x ! 1020 */ 1021 #define ASMC_MBA6_TEMPS { "TB0T", "TB1T", "TB2T", \ 1022 "TC0E", "TC0F", "TC0P", \ 1023 "TC1C", "TC2C", "TCGC", "TCSA", \ 1024 "TCXC", "THSP", "TM0P", "TPCD", \ 1025 "Ta0P", "Th1H", "Tm0P", \ 1026 "Ts0P", "Ts0S", NULL } 1027 1028 #define ASMC_MBA6_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \ 1029 "cputemp1", "cputemp2", "cpuproximity", \ 1030 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 1031 "TCXC", "THSP", "memorybank", "pchdie", \ 1032 "Ta0P", "heatpipe", "mainboardproximity1", \ 1033 "palmrest", "memoryproximity" } 1034 1035 #define ASMC_MBA6_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \ 1036 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 1037 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 1038 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 1039 "Ta0P", "Heatpipe", "Mainboard Proximity 1", \ 1040 "Palm Rest", "Memory Proximity" } 1041 1042 1043 #define ASMC_MBA7_TEMPS { "TB0T", "TB1T", "TB2T", \ 1044 "TC0E", "TC0F", "TC0P", \ 1045 "TC1C", "TC2C", \ 1046 "TCGC", "TCSA", "TCXC", \ 1047 "THSP", "TM0P", "TPCD", \ 1048 "TW0P" "Ta0P", "Th1H", \ 1049 "Tm0P", "Ts0P", "Ts0S", NULL } 1050 1051 #define ASMC_MBA7_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \ 1052 "cputemp1", "cputemp2", "cpuproximity", \ 1053 "cpucore1", "cpucore2", \ 1054 "pecigpu", "pecisa", "pecicpu", \ 1055 "thunderboltproximity", "memorybank", "pchdie", \ 1056 "wirelessproximity", "airflowproximity", "heatpipe", \ 1057 "mainboardproximity", "palmrest", "memoryproximity" } 1058 1059 #define ASMC_MBA7_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \ 1060 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 1061 "CPU Core 1", "CPU Core 2", \ 1062 "PECI GPU", "PECI SA", "PECI CPU", \ 1063 "Thunderbolt Proximity", "Memory Bank A", "PCH Die", \ 1064 "Wireless Proximity", "Airflow Proxmity", "Heatpipe", \ 1065 "Mainboard Proximity", "Palm Rest", "Memory Proximity" } 1066