1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 #define ASMC_MAXFANS 6 31 32 struct asmc_softc { 33 device_t sc_dev; 34 struct mtx sc_mtx; 35 int sc_nfan; 36 int sc_nkeys; 37 int16_t sms_rest_x; 38 int16_t sms_rest_y; 39 int16_t sms_rest_z; 40 struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1]; 41 struct sysctl_oid *sc_temp_tree; 42 struct sysctl_oid *sc_sms_tree; 43 struct sysctl_oid *sc_light_tree; 44 const struct asmc_model *sc_model; 45 int sc_rid_port; 46 int sc_rid_irq; 47 struct resource *sc_ioport; 48 struct resource *sc_irq; 49 void *sc_cookie; 50 int sc_sms_intrtype; 51 struct taskqueue *sc_sms_tq; 52 struct task sc_sms_task; 53 uint8_t sc_sms_intr_works; 54 }; 55 56 /* 57 * Data port. 58 */ 59 #define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00) 60 #define ASMC_DATAPORT_WRITE(sc, val) \ 61 bus_write_1(sc->sc_ioport, 0x00, val) 62 #define ASMC_STATUS_MASK 0x0f 63 64 /* 65 * Command port. 66 */ 67 #define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04) 68 #define ASMC_CMDPORT_WRITE(sc, val) \ 69 bus_write_1(sc->sc_ioport, 0x04, val) 70 #define ASMC_CMDREAD 0x10 71 #define ASMC_CMDWRITE 0x11 72 73 /* 74 * Interrupt port. 75 */ 76 #define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f) 77 78 /* Number of keys */ 79 #define ASMC_NKEYS "#KEY" /* RO; 4 bytes */ 80 81 /* Query the ASMC revision */ 82 #define ASMC_KEY_REV "REV " /* RO: 6 bytes */ 83 84 /* 85 * Fan control via SMC. 86 */ 87 #define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */ 88 #define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */ 89 #define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */ 90 #define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */ 91 #define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */ 92 #define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */ 93 #define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */ 94 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */ 95 96 /* 97 * Sudden Motion Sensor (SMS). 98 */ 99 #define ASMC_SMS_INIT1 0xe0 100 #define ASMC_SMS_INIT2 0xf8 101 #define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */ 102 #define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */ 103 #define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */ 104 #define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */ 105 #define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */ 106 #define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */ 107 #define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */ 108 #define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */ 109 #define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */ 110 #define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */ 111 #define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */ 112 #define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */ 113 114 /* 115 * Light Sensor. 116 */ 117 #define ASMC_ALSL_INT2A 0x2a /* Ambient Light related Interrupt */ 118 119 /* 120 * Keyboard backlight. 121 */ 122 #define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */ 123 #define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */ 124 #define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */ 125 126 /* 127 * Clamshell. 128 */ 129 #define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */ 130 131 /* 132 * Auto power on / Wake-on-LAN. 133 */ 134 #define ASMC_KEY_AUPO "AUPO" /* RW; 1 byte */ 135 136 /* 137 * Interrupt keys. 138 */ 139 #define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */ 140 141 /* 142 * Temperatures. 143 * 144 * First for MacBook, second for MacBook Pro, third for Intel Mac Mini, 145 * fourth the Mac Pro 8-core and finally the MacBook Air. 146 * 147 */ 148 /* maximum array size for temperatures including the last NULL */ 149 #define ASMC_TEMP_MAX 80 150 #define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \ 151 "TM0P", NULL } 152 #define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \ 153 "northbridge2", "heatsink1", \ 154 "heatsink2", "memory", } 155 #define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \ 156 "Northbridge Point 1", \ 157 "Northbridge Point 2", "Heatsink 1", \ 158 "Heatsink 2", "Memory Bank A", } 159 160 #define ASMC_MB31_TEMPS { "TB0T", "TN0P", "Th0H", "Th1H", \ 161 "TM0P", NULL } 162 163 #define ASMC_MB31_TEMPNAMES { "enclosure", "northbridge1", \ 164 "heatsink1", "heatsink2", \ 165 "memory", } 166 167 #define ASMC_MB31_TEMPDESCS { "Enclosure Bottomside", \ 168 "Northbridge Point 1", \ 169 "Heatsink 1","Heatsink 2" \ 170 "Memory Bank A", } 171 172 #define ASMC_MB71_TEMPS { "TB0T", "TB1T", "TB2T", "TC0D", "TC0P", \ 173 "TH0P", "TN0D", "TN0P", "TN0S", "TN1D", \ 174 "TN1E", "TN1F", "TN1G", "TN1S", "Th1H", \ 175 "Ts0P", "Ts0S", NULL } 176 177 #define ASMC_MB71_TEMPNAMES { "enclosure_bottom0", "battery_1", "battery_2", "cpu_package", "cpu_proximity", \ 178 "hdd_bay", "northbridge0_diode", "northbridge0_proximity", "TN0S", "mpc_die2", \ 179 "TN1E", "TN1F", "TN1G", "TN1S", "heatsink1", \ 180 "palm_rest", "memory_proximity", } 181 182 #define ASMC_MB71_TEMPDESCS { "Enclosure Bottom 0", "Battery 1", "Battery 2", "CPU Package", "CPU Proximity", \ 183 "HDD Bay", "Northbridge Diode", "Northbridge Proximity", "TN0S", "MPC Die 2", \ 184 "TN1E", "TN1F", "TN1G", "TN1S", "Heatsink 1", \ 185 "Palm Rest", "Memory Proximity", } 186 187 #define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \ 188 "TG0H", "TG0P", "TG0T", NULL } 189 190 #define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \ 191 "heatsink2", "memory", "graphics", \ 192 "graphicssink", "unknown", } 193 194 #define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \ 195 "Heatsink 1", "Heatsink 2", \ 196 "Memory Controller", \ 197 "Graphics Chip", "Graphics Heatsink", \ 198 "Unknown", } 199 200 #define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \ 201 "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \ 202 "TTF0", "TW0P", NULL } 203 204 #define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \ 205 "heatsink3", "memory", "graphicssink", \ 206 "graphics", "cpu", "cpu2", "unknown1", \ 207 "unknown2", "wireless", } 208 209 #define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \ 210 "Main Heatsink 1", "Main Heatsink 2", \ 211 "Main Heatsink 3", \ 212 "Memory Controller", \ 213 "Graphics Chip Heatsink", \ 214 "Graphics Chip Diode", \ 215 "CPU Temperature Diode", "CPU Point 2", \ 216 "Unknown", "Unknown", \ 217 "Wireless Module", } 218 219 #define ASMC_MBP51_TEMPS { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", \ 220 "TC0F", "TC0P", "TG0D", "TG0F", "TG0H", \ 221 "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", \ 222 "TTF0", "Th2H", "Tm0P", "Ts0P", "Ts0S", \ 223 NULL } 224 225 #define ASMC_MBP51_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 226 "enclosure_bottom_2", "enclosure_bottom_3", \ 227 "cpu_diode", "cpu", \ 228 "cpu_pin", "gpu_diode", \ 229 "gpu", "gpu_heatsink", \ 230 "gpu_pin", "gpu_transistor", \ 231 "gpu_2_heatsink", "northbridge_diode", \ 232 "northbridge_pin", "unknown", \ 233 "heatsink_2", "memory_controller", \ 234 "pci_express_slot_pin", "pci_express_slot_unk" } 235 236 #define ASMC_MBP51_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 237 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 238 "CPU Diode", "CPU ???", \ 239 "CPU Pin", "GPU Diode", \ 240 "GPU ???", "GPU Heatsink", \ 241 "GPU Pin", "GPU Transistor", \ 242 "GPU 2 Heatsink", "Northbridge Diode", \ 243 "Northbridge Pin", "Unknown", \ 244 "Heatsink 2", "Memory Controller", \ 245 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 246 247 #define ASMC_MBP62_TEMPS { "TB0T", "TB1T", "TB2T", \ 248 "TC0C", "TC0D", "TC0P", \ 249 "TC1C", "TG0D", "TG0P", \ 250 "TG0T", "TMCD", "TP0P", \ 251 "TPCD", "Th1H", "Th2H", \ 252 "Tm0P", "Ts0P", "Ts0S" } 253 254 #define ASMC_MBP62_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 255 "enclosure_bottom_2", "cpu0", \ 256 "cpu_diode", "cpu_proximity", \ 257 "cpu1", "gpu_diode", \ 258 "gpu_pin", "gpu_transistor", \ 259 "TMCD", "pch_controller_proximity", \ 260 "pch_die", "heatsink1", \ 261 "heatsink2", "memory-controller", \ 262 "palmrest", "memoryproximity" } 263 264 #define ASMC_MBP62_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 265 "Enclosure Bottom 2", "CPU 0", \ 266 "CPU Diode", "CPU Proximity", \ 267 "CPU 1", "GPU Diode", \ 268 "GPU Pin", "GPU Transistor", \ 269 "TMCD", "PCH Controller Proximity", \ 270 "PCH Die", "Heat Sink 1", \ 271 "Heat Sink 2", "Memory Controller", \ 272 "Palm Rest", "Memory Proximity" } 273 274 #define ASMC_MBP55_TEMPS { "TB0T", "TB1T", \ 275 "TB2T", "TB3T", \ 276 "TC0D", "TC0P", \ 277 "TN0D", "TN0P", \ 278 "TTF0", \ 279 "Th0H", "Th1H", "ThFH", \ 280 "Ts0P", "Ts0S", \ 281 NULL } 282 283 #define ASMC_MBP55_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 284 "enclosure_bottom_2", "enclosure_bottom_3", \ 285 "cpu_diode", "cpu_pin", \ 286 "northbridge_diode", "northbridge_pin", \ 287 "unknown", \ 288 "heatsink_0", "heatsink_1", "heatsink_2", \ 289 "pci_express_slot_pin", "pci_express_slot_unk" } 290 291 #define ASMC_MBP55_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 292 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 293 "CPU Diode", "CPU Pin", \ 294 "Northbridge Diode", "Northbridge Pin", \ 295 "Unknown", \ 296 "Heatsink 0", "Heatsink 1", "Heatsink 2", \ 297 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 298 299 #define ASMC_MBP81_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 300 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 301 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 302 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 303 "Ts0S", NULL } 304 305 #define ASMC_MBP81_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 306 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 307 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 308 "TP0P", "TPCD", "wireless", "Th1H", "Ts0P", \ 309 "Ts0S" } 310 311 #define ASMC_MBP81_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 312 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 313 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 314 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 315 "Ts0S" } 316 317 #define ASMC_MBP82_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 318 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 319 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 320 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 321 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 322 "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL } 323 324 #define ASMC_MBP82_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 325 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 326 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 327 "TCTD", "graphics", "TG0P", "THSP", "TM0S", \ 328 "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \ 329 "Th2H", "memory", "Ts0P", "Ts0S" } 330 331 #define ASMC_MBP82_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 332 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 333 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 334 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 335 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 336 "Th2H", "Tm0P", "Ts0P", "Ts0S" } 337 338 #define ASMC_MBP91_TEMPS { "TA0P", "TB0T", "TB1T", "TB2T", "TC0E", \ 339 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 340 "TC4C", "TCGC", "TCSA", "TCXC", "TG0D", \ 341 "TG0P", "TG1D", "TG1F", "TG1d", "TGTC", \ 342 "TGTD", "TM0P", "TM0S", "TP0P", "TPCD", \ 343 "Th1H", "Th2H", "Ts0P", "Ts0S", "Tsqf", NULL } 344 345 #define ASMC_MBP91_TEMPNAMES { "ambient", "enclosure_bottom_1", "enclosure_bottom_2", \ 346 "enclosure_bottom_3", "cpu_die_peci_0", "cpu_die_peci_1", \ 347 "cpu_proximity", "cpu_core_1", "cpu_core_2", "cpu_core_3", \ 348 "cpu_core_4", "intel_gpu", "cpu_sys_agent", \ 349 "cpu_core_peci", "gpu_analog", \ 350 "gpu_proximity", "geforce_gpu_digital", "tg1f", \ 351 "gpu_2_die", "tgtc", "tgtd", "memory_proximity", \ 352 "mem_bank_a1", "platform_ctrl_hub", "pch_digital", \ 353 "main_heatsink_r", "main_heatsink_l", "palm_rest", \ 354 "bottom_skin", "tsqf" } 355 356 #define ASMC_MBP91_TEMPDESCS { "Ambient", "Enclosure Bottom 1", "Enclosure Bottom 2", \ 357 "Enclosure Bottom 3", "CPU Die PECI 0", "CPU Die PECI 1", \ 358 "CPU Proximity", "CPU Core 1", "CPU Core 2", \ 359 "CPU Core 3", "CPU Core 4", "Intel GPU", \ 360 "CPU System Agent Core", "CPU Core - PECI", \ 361 "GPU Die - Analog", "GPU Proximity", \ 362 "GeForce GPU Die - Digital", "TG1F", "GPU 2 Die" \ 363 "TGTC", "TGTD", "Memory Proximity", \ 364 "Memory Bank A1", "Platform Controller Hub", "PCH Die - Digital", \ 365 "Main Heatsink Right", "Main Heatsink Left", "Palm Rest", \ 366 "Bottom Skin", "Tsqf" } 367 368 #define ASMC_MBP92_TEMPS { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 369 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 370 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 371 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 372 "TPCD", NULL } 373 374 #define ASMC_MBP92_TEMPNAMES { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 375 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 376 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 377 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 378 "TPCD" } 379 380 #define ASMC_MBP92_TEMPDESCS { "Palm Rest", "Memory Proximity", "Airflow 1", \ 381 "Battery 1", "Battery 2", "Battery TS_MAX", \ 382 "CPU Core 1", "CPU Core 2", "CPU1", "CPU1", \ 383 "TC0J", "CPU 1 Proximity", "TCFC", \ 384 "PECI GPU", "PECI SA", "TCTD", "PECI CPU", \ 385 "GPU Die", "Memory Bank A1", "Memory Module A1", \ 386 "PCH Die" } 387 388 #define ASMC_MBP112_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 389 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 390 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 391 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 392 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 393 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 394 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 395 "Ts1S", NULL } 396 397 #define ASMC_MBP112_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 398 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 399 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 400 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 401 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 402 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 403 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 404 "Ts1S" } 405 406 #define ASMC_MBP112_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 407 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 408 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 409 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 410 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 411 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 412 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 413 "Ts1S" } 414 415 #define ASMC_MBP113_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 416 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 417 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 418 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 419 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 420 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 421 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 422 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 423 "Ts1S", NULL } 424 425 #define ASMC_MBP113_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 426 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 427 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 428 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 429 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 430 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 431 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 432 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 433 "Ts1S" } 434 435 #define ASMC_MBP113_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 436 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 437 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 438 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 439 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 440 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 441 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 442 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 443 "Ts1S" } 444 445 #define ASMC_MBP114_TEMPS { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 446 "IO3R", "IO5R", "IM0C", "IC1C", "IC2C", \ 447 "IC3C", "ILDC", "IBLC", "IAPC", "IHSC", \ 448 "ICMC", "TC0P", "TP0P", "TM0P", \ 449 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 450 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 451 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 452 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 453 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 454 "PCPG", "PCPT", "PSTR", "PDTR", NULL } 455 456 #define ASMC_MBP114_TEMPNAMES { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 457 "IO3R", "IO5R", "IM0C", "IC1C", "IC2C", \ 458 "IC3C", "ILDC", "IBLC", "IAPC", "IHSC", \ 459 "ICMC", "TC0P", "TP0P", "TM0P", \ 460 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 461 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 462 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 463 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 464 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 465 "PCPG", "PCPT", "PSTR", "PDTR" } 466 467 #define ASMC_MBP114_TEMPDESCS { "CPU High (CPU, I/O)", "DC In", "SSD", "Charger (BMON)", "CPU", \ 468 "Other 3.3V", "Other 5V", "Memory", "Platform Controller Hub Core", "CPU Load Current Monitor", \ 469 "CPU DDR", "LCD Panel", "LCD Backlight", "Airport", "Thunderbolt", \ 470 "S2", "CPU Proximity", "Platform Controller Hub", "Memory Proximity", "Air Flow Proximity", \ 471 "Left Fin Stack", "Right Fin Stack", "Airport Proximity", "Palm Rest", "Palm Rest Actuator", \ 472 "Battery Max", "Battery Sensor 1", "Battery Sensor 2", "SSD A", "SSD B", \ 473 "CPU Core 1", "CPU Core 2", "CPU Core 3", "CPU Core 4", "CPU PECI Die", \ 474 "Intel GPU", "Platform Controller Hub PECI", "CPU System Agent Core", "CPU VCore", "DC In", \ 475 "Pbus", "Ambient Light", "Leftside", "Rightside", "CPU Package Core", \ 476 "CPU Package GPU", "CPU Package Total", "System Total", "DC In" } 477 478 /* MacBookPro11,5 - same as 11,4 but without IBLC, ICMC, and IC2C keys */ 479 #define ASMC_MBP115_TEMPS { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 480 "IO3R", "IO5R", "IM0C", "IC1C", \ 481 "IC3C", "ILDC", "IAPC", "IHSC", \ 482 "TC0P", "TP0P", "TM0P", \ 483 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 484 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 485 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 486 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 487 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 488 "PCPG", "PCPT", "PSTR", "PDTR", NULL } 489 490 491 #define ASMC_MBP115_TEMPNAMES { "IC0C", "ID0R", "IHDC", "IPBR", "IC0R", \ 492 "IO3R", "IO5R", "IM0C", "IC1C", \ 493 "IC3C", "ILDC", "IAPC", "IHSC", \ 494 "TC0P", "TP0P", "TM0P", \ 495 "Ta0P", "Th2H", "Th1H", "TW0P", "Ts0P", \ 496 "Ts1P", "TB0T", "TB1T", "TB2T", "TH0A", "TH0B", \ 497 "TC1C", "TC2C", "TC3C", "TC4C", "TCXC", \ 498 "TCGC", "TPCD", "TCSA", "VC0C", "VD0R", \ 499 "VP0R", "ALSL", "F0Ac", "F1Ac", "PCPC", \ 500 "PCPG", "PCPT", "PSTR", "PDTR" } 501 502 #define ASMC_MBP115_TEMPDESCS { "CPU High (CPU, I/O)", "DC In", "SSD", "Charger (BMON)", "CPU", \ 503 "Other 3.3V", "Other 5V", "Memory", "Platform Controller Hub Core", \ 504 "CPU DDR", "LCD Panel", "Airport", "Thunderbolt", \ 505 "CPU Proximity", "Platform Controller Hub", "Memory Proximity", "Air Flow Proximity", \ 506 "Left Fin Stack", "Right Fin Stack", "Airport Proximity", "Palm Rest", "Palm Rest Actuator", \ 507 "Battery Max", "Battery Sensor 1", "Battery Sensor 2", "SSD A", "SSD B", \ 508 "CPU Core 1", "CPU Core 2", "CPU Core 3", "CPU Core 4", "CPU PECI Die", \ 509 "Intel GPU", "Platform Controller Hub PECI", "CPU System Agent Core", "CPU VCore", "DC In", \ 510 "Pbus", "Ambient Light", "Leftside", "Rightside", "CPU Package Core", \ 511 "CPU Package GPU", "CPU Package Total", "System Total", "DC In" } 512 513 #define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL } 514 #define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" } 515 #define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \ 516 "Northbridge Point 2" } 517 518 #define ASMC_MM21_TEMPS { "TA0P", "TC0D", \ 519 "TC0H", "TC0P", \ 520 "TC1P", "TN0P", \ 521 "TN1P", NULL } 522 523 #define ASMC_MM21_TEMPNAMES { "ambient_air", "cpu_die", \ 524 "cpu_heatsink", "cpu_proximity1", \ 525 "cpu_proximity2", "northbridge_proximity1", \ 526 "northbridge_proximity2", } 527 528 #define ASMC_MM21_TEMPDESCS { "Ambient Air Temperature" \ 529 "CPU Die Core Temperature", \ 530 "CPU Heatsink Temperature", \ 531 "CPU Proximity 1 Temperature", \ 532 "CPU Proximity 2 Temperature", \ 533 "Northbridge Proximity 1 Temperature", \ 534 "Northbridge Proximity 2 Temperature", } 535 536 #define ASMC_MM31_TEMPS { "TC0D", "TC0H", \ 537 "TC0P", "TH0P", \ 538 "TN0D", "TN0P", \ 539 "TW0P", NULL } 540 541 #define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \ 542 "cpu0_proximity", "hdd_bay", \ 543 "northbridge_die", \ 544 "northbridge_proximity", \ 545 "wireless_proximity", } 546 547 #define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \ 548 "CPU0 Heatsink Temperature", \ 549 "CPU0 Proximity Temperature", \ 550 "HDD Bay Temperature", \ 551 "Northbridge Die Core Temperature", \ 552 "Northbridge Proximity Temperature", \ 553 "Wireless Module Proximity Temperature", } 554 555 #define ASMC_MM41_TEMPS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 556 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 557 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 558 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 559 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 560 "TW0P", "Tm0P", "Tp0C", NULL } 561 562 #define ASMC_MM41_TEMPNAMES { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 563 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 564 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 565 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 566 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 567 "TW0P", "Tm0P", "Tp0C", NULL } 568 569 #define ASMC_MM41_TEMPDESCS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 570 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 571 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 572 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 573 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 574 "TW0P", "Tm0P", "Tp0C", NULL } 575 576 #define ASMC_MM52_TEMPS { "TA0P", "TA1P", \ 577 "TC0D", "TC0P", \ 578 "TG0D", "TG1D", \ 579 "TG0P", "TG0M", \ 580 "TI0P", \ 581 "TM0S", "TMBS", \ 582 "TM0P", "TP0P", \ 583 "TPCD", "Tp0C", \ 584 "TW0P", NULL } 585 586 #define ASMC_MM52_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 587 "cpu_die", "cpu_proximity", \ 588 "gpu_diode1", "gpu_diode2", \ 589 "gpu_proximity", "gpu_integrated_switcher", \ 590 "thunderbolt_proximity", \ 591 "memory_slot1", "memory_slot2", \ 592 "memory_proximity", "pch_controller_proximity", \ 593 "pch_controller_die", "pwr_supply", \ 594 "wireless_proximity", } 595 596 #define ASMC_MM52_TEMPDESCS { "Ambient Air Proximity Temperature", \ 597 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 598 "CPU Die Temperature", "CPU Proximity Temperature", \ 599 "GPU Diode 1 Temperature" , "GPU Diode 2 Temperature", \ 600 "GPU Proximity Temperature", \ 601 "Integrated Graphics/GPU Switcher Temperature", \ 602 "Thunderbolt Proximity Temperature", \ 603 "Memory Slot 1 Temperature", \ 604 "Memory Slot 2 Temperature", \ 605 "Memory Slots Proximity Temperature", \ 606 "Platform Controller Hub Proximity Temperature", \ 607 "Platform Controller Hub Die Temperature", \ 608 "Power Supply Temperature", \ 609 "Wireless Module Proximity Temperature", } 610 611 #define ASMC_MM61_TEMPS { "TA0P", "TA1P", \ 612 "TC0D", "TC0G", "TC0P", "TCPG", \ 613 "TI0P", \ 614 "TM0S", "TMBS", "TM0P", \ 615 "TP0P", "TPCD", \ 616 "Tp0C", \ 617 "TW0P", NULL } 618 619 #define ASMC_MM61_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 620 "cpu_die", "TC0G", "cpu_proximity", "TCPG", \ 621 "thunderbolt_proximity", \ 622 "memory_slot1", "memory_slot2", "memory_proximity", \ 623 "pch_controller_proximity", "pch_controller_die", \ 624 "pwr_supply", \ 625 "wireless_proximity", NULL } 626 627 #define ASMC_MM61_TEMPDESCS { "Ambient Air Proximity Temperature", \ 628 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 629 "CPU Die Temperature", \ 630 NULL, \ 631 "CPU Proximity Temperature", \ 632 NULL, \ 633 "Thunderbolt Proximity Temperature", \ 634 "Memory Slot 1 Temperature", \ 635 "Memory Slot 2 Temperature", \ 636 "Memory Slots Proximity Temperature", \ 637 "Platform Controller Hub Proximity Temperature", \ 638 "Platform Controller Hub Die Temperature", \ 639 "Power Supply Temperature", \ 640 "Wireless Module Proximity Temperature", NULL } 641 642 #define ASMC_MM62_TEMPS { "TA0P", "TA1P", \ 643 "TC0D", "TC0G", "TC0P", "TCPG", \ 644 "TI0P", \ 645 "TM0S", "TMBS", "TM0P", \ 646 "TP0P", "TPCD", \ 647 "Tp0C", \ 648 "TW0P", NULL } 649 650 #define ASMC_MM62_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 651 "cpu_die", "TC0G", "cpu_proximity", "TCPG", \ 652 "thunderbolt_proximity", \ 653 "memory_slot1", "memory_slot2", "memory_proximity", \ 654 "pch_controller_proximity", "pch_controller_die", \ 655 "pwr_supply", \ 656 "wireless_proximity", NULL } 657 658 #define ASMC_MM62_TEMPDESCS { "Ambient Air Proximity Temperature", \ 659 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 660 "CPU Die Temperature", \ 661 NULL, \ 662 "CPU Proximity Temperature", \ 663 NULL, \ 664 "Thunderbolt Proximity Temperature", \ 665 "Memory Slot 1 Temperature", \ 666 "Memory Slot 2 Temperature", \ 667 "Memory Slots Proximity Temperature", \ 668 "Platform Controller Hub Proximity Temperature", \ 669 "Platform Controller Hub Die Temperature", \ 670 "Power Supply Temperature", \ 671 "Wireless Module Proximity Temperature", NULL } 672 673 #define ASMC_MM71_TEMPS { "TA0p", "TA1p", \ 674 "TA2p", "TC0c", \ 675 "TC0p", "TC1c", \ 676 "TCGc", "TCSc", \ 677 "TCXC", "TCXR", \ 678 "TM0p", "TPCd", \ 679 "TW0p", "Te0T", \ 680 "Tm0P", NULL } 681 682 #define ASMC_MM71_TEMPNAMES { "ambient_air1", "ambient_air2", \ 683 "ambient_air3", "cpu_core1_peci", \ 684 "cpu_proximity", "cpu_core2_peci", \ 685 "intel_gpu", "cpu_sa_core_peci", \ 686 "cpu_core", "cpu_peci_dts", \ 687 "memory_proximity", "pch_controller_die", \ 688 "wireless_proximity", "thunderbolt_diode", \ 689 "logic_board", } 690 691 #define ASMC_MM71_TEMPDESCS { "Ambient Air Temperature 1", \ 692 "Ambient Air Temperature 2", \ 693 "Ambient Air Temperature 3", \ 694 "CPU Core 1 PECI Temperature", "CPU Proximity Temperature", \ 695 "CPU Core 2 PECI Temperature", "Intel GPU Temperature", \ 696 "CPU System Agent Core PECI Temperature", \ 697 "CPU Core Temperature", "CPU PECI DTS Temperature", \ 698 "Memory Proximity Temperature", \ 699 "Platform Controller Hub Die Temperature", \ 700 "Wireless Module Proximity Temperature", \ 701 "Thunderbolt Diode Temperature", \ 702 "Logic Board temperature", } 703 704 #define ASMC_MP1_TEMPS { "TA0P", \ 705 "TCAH", "TCBH", \ 706 "TC0P", "TC0C", "TC1C", \ 707 "TC2C", "TC3C", "THTG", \ 708 "TH0P", "TH1P", \ 709 "TH2P", "TH3P", \ 710 "TM0P", "TM1P", "TM2P", \ 711 "TM8P", "TM9P", "TMAP", \ 712 "TM0S", "TM1S", "TM2P", "TM3S", \ 713 "TM8S", "TM9S", "TMAS", "TMBS", \ 714 "TN0H", "TS0C", \ 715 "Tp0C", "Tp1C", "Tv0S", "Tv1S", NULL } 716 717 #define ASMC_MP1_TEMPNAMES { "ambient", \ 718 "cpu_a_heatsink", "cpu_b_heatsink", \ 719 "cpu_a_proximity", "cpu_core0", "cpu_core1", \ 720 "cpu_core2", "cpu_core3", "THTG", \ 721 "hdd_bay0", "hdd_bay1", \ 722 "hdd_bay2", "hdd_bay3", \ 723 "memory_card_a_proximity0", \ 724 "memory_card_a_proximity1", \ 725 "memory_card_a_proximity2", \ 726 "memory_card_b_proximity0", \ 727 "memory_card_b_proximity1", \ 728 "memory_card_b_proximity2", \ 729 "memory_card_a_slot0", \ 730 "memory_card_a_slot1", \ 731 "memory_card_a_slot2", \ 732 "memory_card_a_slot3", \ 733 "memory_card_b_slot0", \ 734 "memory_card_b_slot1", \ 735 "memory_card_b_slot2", \ 736 "memory_card_b_slot3", \ 737 "mch_heatsink", "expansion_slots", \ 738 "power_supply_loc0", "power_supply_loc1", \ 739 "Tv0S", "Tv1S", } 740 741 #define ASMC_MP1_TEMPDESCS { "Ambient Air", \ 742 "CPU A Heatsink", "CPU B Heatsink", \ 743 "CPU A Proximity", \ 744 "CPU Core 1", "CPU Core 2", \ 745 "CPU Core 3", "CPU Core 4", "THTG", \ 746 "Hard Drive Bay 1", "Hard Drive Bay 2", \ 747 "Hard Drive Bay 3", "Hard Drive Bay 4", \ 748 "Memory Riser A, Proximity 1", \ 749 "Memory Riser A, Proximity 2", \ 750 "Memory Riser A, Proximity 3", \ 751 "Memory Riser B, Proximity 1", \ 752 "Memory Riser B, Proximity 2", \ 753 "Memory Riser B, Proximity 3", \ 754 "Memory Riser A, Slot 1", \ 755 "Memory Riser A, Slot 2", \ 756 "Memory Riser A, Slot 3", \ 757 "Memory Riser A, Slot 4", \ 758 "Memory Riser B, Slot 1", \ 759 "Memory Riser B, Slot 2", \ 760 "Memory Riser B, Slot 3", \ 761 "Memory Riser B, Slot 4", \ 762 "MCH Heatsink", "Expansion Slots", \ 763 "Power Supply, Location 1", \ 764 "Power Supply, Location 2", \ 765 "Tv0S", "Tv1S", } 766 767 #define ASMC_MP31_TEMPS { "TA0P", \ 768 "TC0C", "TC0D", "TC0P", \ 769 "TC1C", "TC1D", \ 770 "TC2C", "TC2D", \ 771 "TC3C", "TC3D", \ 772 "TCAG", "TCAH", "TCBG", "TCBH", \ 773 "TH0P", "TH1P", "TH2P", "TH3P", \ 774 "TM0P", "TM0S", "TM1P", "TM1S", \ 775 "TM2P", "TM2S", "TM3S", \ 776 "TM8P", "TM8S", "TM9P", "TM9S", \ 777 "TMAP", "TMAS", "TMBS", \ 778 "TN0C", "TN0D", "TN0H", \ 779 "TS0C", \ 780 "Tp0C", "Tp1C", \ 781 "Tv0S", "Tv1S", NULL } 782 783 #define ASMC_MP31_TEMPNAMES { "ambient", \ 784 "cpu_core0", "cpu_diode0", "cpu_a_proximity", \ 785 "cpu_core1", "cpu_diode1", \ 786 "cpu_core2", "cpu_diode2", \ 787 "cpu_core3", "cpu_diode3", \ 788 "cpu_a_pkg", "cpu_a_heatsink", \ 789 "cpu_b_pkg", "cpu_b_heatsink", \ 790 "hdd_bay0", "hdd_bay1", \ 791 "hdd_bay2", "hdd_bay3", \ 792 "mem_riser_a_prox0", "mem_riser_a_slot0", \ 793 "mem_riser_a_prox1", "mem_riser_a_slot1", \ 794 "mem_riser_a_prox2", "mem_riser_a_slot2", \ 795 "mem_riser_a_slot3", \ 796 "mem_riser_b_prox0", "mem_riser_b_slot0", \ 797 "mem_riser_b_prox1", "mem_riser_b_slot1", \ 798 "mem_riser_b_prox2", "mem_riser_b_slot2", \ 799 "mem_riser_b_slot3", \ 800 "northbridge_core", "northbridge_diode", \ 801 "northbridge_heatsink", \ 802 "expansion_slots", \ 803 "power_supply0", "power_supply1", \ 804 "vrm0", "vrm1", } 805 806 #define ASMC_MP31_TEMPDESCS { "Ambient Air", \ 807 "CPU Core 1", "CPU Diode 1", \ 808 "CPU A Proximity", \ 809 "CPU Core 2", "CPU Diode 2", \ 810 "CPU Core 3", "CPU Diode 3", \ 811 "CPU Core 4", "CPU Diode 4", \ 812 "CPU A Package", "CPU A Heatsink", \ 813 "CPU B Package", "CPU B Heatsink", \ 814 "Hard Drive Bay 1", "Hard Drive Bay 2", \ 815 "Hard Drive Bay 3", "Hard Drive Bay 4", \ 816 "Memory Riser A, Proximity 1", \ 817 "Memory Riser A, Slot 1", \ 818 "Memory Riser A, Proximity 2", \ 819 "Memory Riser A, Slot 2", \ 820 "Memory Riser A, Proximity 3", \ 821 "Memory Riser A, Slot 3", \ 822 "Memory Riser A, Slot 4", \ 823 "Memory Riser B, Proximity 1", \ 824 "Memory Riser B, Slot 1", \ 825 "Memory Riser B, Proximity 2", \ 826 "Memory Riser B, Slot 2", \ 827 "Memory Riser B, Proximity 3", \ 828 "Memory Riser B, Slot 3", \ 829 "Memory Riser B, Slot 4", \ 830 "Northbridge Core", "Northbridge Diode", \ 831 "Northbridge Heatsink", \ 832 "Expansion Slots", \ 833 "Power Supply 1", "Power Supply 2", \ 834 "VRM 1", "VRM 2", } 835 836 #define ASMC_MP2_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 837 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 838 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 839 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 840 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 841 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 842 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \ 843 NULL } 844 845 #define ASMC_MP2_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 846 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 847 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 848 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 849 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 850 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 851 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 852 853 #define ASMC_MP2_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 854 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 855 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 856 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 857 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 858 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 859 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 860 861 #define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 862 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 863 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 864 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 865 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 866 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 867 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 868 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 869 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 870 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 871 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 872 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 873 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 874 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 875 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \ 876 NULL } 877 878 #define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \ 879 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 880 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 881 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 882 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 883 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 884 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 885 "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \ 886 "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \ 887 "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \ 888 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 889 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 890 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 891 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 892 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 893 894 #define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 895 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 896 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 897 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 898 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 899 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 900 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 901 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 902 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 903 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 904 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 905 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 906 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 907 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 908 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 909 910 #define ASMC_MP6_TEMPS { "TA0P", "TA1P", "TC0P", "TG0D", "TG0P", \ 911 "TG1D", "TG1P", "TM0P", "TM1P", NULL } 912 913 #define ASMC_MP6_TEMPNAMES { "ambient_air_1", "ambient_air_2", \ 914 "cpu_proximity", "gpu_diode_1", \ 915 "gpu_proximity_1", "gpu_diode_2", \ 916 "gpu_proximity_2", "mem_proximity_1", \ 917 "mem_proximity_2" } 918 919 #define ASMC_MP6_TEMPDESCS { "Ambient Air 1", "Ambient Air 2", \ 920 "CPU Proximity", "GPU Diode 1", \ 921 "GPU Proximity 1", "GPU Diode 2", \ 922 "GPU Proximity 2", "Memory Bank A", \ 923 "Memory Bank B" } 924 925 #define ASMC_MBA_TEMPS { "TB0T", NULL } 926 #define ASMC_MBA_TEMPNAMES { "enclosure" } 927 #define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" } 928 929 #define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \ 930 "TC0D", "TC0E", "TC0P", NULL } 931 932 #define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \ 933 "TC0D", "TC0E", "TC0P" } 934 935 #define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \ 936 "TC0D", "TC0E", "TC0P" } 937 938 #define ASMC_MBA4_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 939 "TC0D", "TC0E", "TC0F", "TC0P", \ 940 "TC1C", "TC2C", "TCGC", "TCSA", \ 941 "TH0F", "TH0J", "TH0O", "TH0o", \ 942 "TM0P", "TPCD", "Ta0P", "Th1H", \ 943 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 944 NULL } 945 946 #define ASMC_MBA4_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TC0C", \ 947 "TC0D", "TC0E", "TC0F", "TC0P", \ 948 "TC1C", "TC2C", "TCGC", "TCSA", \ 949 "TH0F", "TH0J", "TH0O", "TH0o", \ 950 "TM0P", "TPCD", "Ta0P", "Th1H", \ 951 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 952 NULL } 953 954 #define ASMC_MBA4_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TC0C", \ 955 "TC0D", "TC0E", "TC0F", "TC0P", \ 956 "TC1C", "TC2C", "TCGC", "TCSA", \ 957 "TH0F", "TH0J", "TH0O", "TH0o", \ 958 "TM0P", "TPCD", "Ta0P", "Th1H", \ 959 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 960 NULL } 961 962 #define ASMC_MBA5_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 963 "TC0D", "TC0E", "TC0F", "TC0P", \ 964 "TC1C", "TC2C", "TCGC", "TCSA", \ 965 "TCXC", "THSP", "TM0P", "TPCD", \ 966 "Ta0P", "Th1H", "Tm0P", "Tm1P", \ 967 "Ts0P", "Ts0S", NULL } 968 969 #define ASMC_MBA5_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", "TC0C", \ 970 "cpudiode", "cputemp1", "cputemp2", "cpuproximity", \ 971 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 972 "TCXC", "THSP", "memorybank", "pchdie", \ 973 "Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \ 974 "palmrest", "memoryproximity" } 975 976 #define ASMC_MBA5_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\ 977 "CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 978 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 979 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 980 "Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \ 981 "Palm Rest", "Memory Proximity" } 982 983 /* 984 * TODO: validate the temp zones for MBA 6.x ! 985 */ 986 #define ASMC_MBA6_TEMPS { "TB0T", "TB1T", "TB2T", \ 987 "TC0E", "TC0F", "TC0P", \ 988 "TC1C", "TC2C", "TCGC", "TCSA", \ 989 "TCXC", "THSP", "TM0P", "TPCD", \ 990 "Ta0P", "Th1H", "Tm0P", \ 991 "Ts0P", "Ts0S", NULL } 992 993 #define ASMC_MBA6_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \ 994 "cputemp1", "cputemp2", "cpuproximity", \ 995 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 996 "TCXC", "THSP", "memorybank", "pchdie", \ 997 "Ta0P", "heatpipe", "mainboardproximity1", \ 998 "palmrest", "memoryproximity" } 999 1000 #define ASMC_MBA6_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \ 1001 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 1002 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 1003 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 1004 "Ta0P", "Heatpipe", "Mainboard Proximity 1", \ 1005 "Palm Rest", "Memory Proximity" } 1006 1007 1008 #define ASMC_MBA7_TEMPS { "TB0T", "TB1T", "TB2T", \ 1009 "TC0E", "TC0F", "TC0P", \ 1010 "TC1C", "TC2C", \ 1011 "TCGC", "TCSA", "TCXC", \ 1012 "THSP", "TM0P", "TPCD", \ 1013 "TW0P" "Ta0P", "Th1H", \ 1014 "Tm0P", "Ts0P", "Ts0S", NULL } 1015 1016 #define ASMC_MBA7_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \ 1017 "cputemp1", "cputemp2", "cpuproximity", \ 1018 "cpucore1", "cpucore2", \ 1019 "pecigpu", "pecisa", "pecicpu", \ 1020 "thunderboltproximity", "memorybank", "pchdie", \ 1021 "wirelessproximity", "airflowproximity", "heatpipe", \ 1022 "mainboardproximity", "palmrest", "memoryproximity" } 1023 1024 #define ASMC_MBA7_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \ 1025 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 1026 "CPU Core 1", "CPU Core 2", \ 1027 "PECI GPU", "PECI SA", "PECI CPU", \ 1028 "Thunderbolt Proximity", "Memory Bank A", "PCH Die", \ 1029 "Wireless Proximity", "Airflow Proxmity", "Heatpipe", \ 1030 "Mainboard Proximity", "Palm Rest", "Memory Proximity" } 1031