1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 #define ASMC_MAXFANS 6 31 32 struct asmc_softc { 33 device_t sc_dev; 34 struct mtx sc_mtx; 35 int sc_nfan; 36 int16_t sms_rest_x; 37 int16_t sms_rest_y; 38 int16_t sms_rest_z; 39 struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1]; 40 struct sysctl_oid *sc_temp_tree; 41 struct sysctl_oid *sc_sms_tree; 42 struct sysctl_oid *sc_light_tree; 43 const struct asmc_model *sc_model; 44 int sc_rid_port; 45 int sc_rid_irq; 46 struct resource *sc_ioport; 47 struct resource *sc_irq; 48 void *sc_cookie; 49 int sc_sms_intrtype; 50 struct taskqueue *sc_sms_tq; 51 struct task sc_sms_task; 52 uint8_t sc_sms_intr_works; 53 }; 54 55 /* 56 * Data port. 57 */ 58 #define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00) 59 #define ASMC_DATAPORT_WRITE(sc, val) \ 60 bus_write_1(sc->sc_ioport, 0x00, val) 61 #define ASMC_STATUS_MASK 0x0f 62 63 /* 64 * Command port. 65 */ 66 #define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04) 67 #define ASMC_CMDPORT_WRITE(sc, val) \ 68 bus_write_1(sc->sc_ioport, 0x04, val) 69 #define ASMC_CMDREAD 0x10 70 #define ASMC_CMDWRITE 0x11 71 72 /* 73 * Interrupt port. 74 */ 75 #define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f) 76 77 /* Number of keys */ 78 #define ASMC_NKEYS "#KEY" /* RO; 4 bytes */ 79 80 /* 81 * Fan control via SMC. 82 */ 83 #define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */ 84 #define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */ 85 #define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */ 86 #define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */ 87 #define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */ 88 #define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */ 89 #define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */ 90 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */ 91 92 /* 93 * Sudden Motion Sensor (SMS). 94 */ 95 #define ASMC_SMS_INIT1 0xe0 96 #define ASMC_SMS_INIT2 0xf8 97 #define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */ 98 #define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */ 99 #define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */ 100 #define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */ 101 #define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */ 102 #define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */ 103 #define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */ 104 #define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */ 105 #define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */ 106 #define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */ 107 #define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */ 108 #define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */ 109 110 /* 111 * Light Sensor. 112 */ 113 #define ASMC_ALSL_INT2A 0x2a /* Ambient Light related Interrupt */ 114 115 /* 116 * Keyboard backlight. 117 */ 118 #define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */ 119 #define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */ 120 #define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */ 121 122 /* 123 * Clamshell. 124 */ 125 #define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */ 126 127 /* 128 * Interrupt keys. 129 */ 130 #define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */ 131 132 /* 133 * Temperatures. 134 * 135 * First for MacBook, second for MacBook Pro, third for Intel Mac Mini, 136 * fourth the Mac Pro 8-core and finally the MacBook Air. 137 * 138 */ 139 /* maximum array size for temperatures including the last NULL */ 140 #define ASMC_TEMP_MAX 80 141 #define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \ 142 "TM0P", NULL } 143 #define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \ 144 "northbridge2", "heatsink1", \ 145 "heatsink2", "memory", } 146 #define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \ 147 "Northbridge Point 1", \ 148 "Northbridge Point 2", "Heatsink 1", \ 149 "Heatsink 2", "Memory Bank A", } 150 151 #define ASMC_MB31_TEMPS { "TB0T", "TN0P", "Th0H", "Th1H", \ 152 "TM0P", NULL } 153 154 #define ASMC_MB31_TEMPNAMES { "enclosure", "northbridge1", \ 155 "heatsink1", "heatsink2", \ 156 "memory", } 157 158 #define ASMC_MB31_TEMPDESCS { "Enclosure Bottomside", \ 159 "Northbridge Point 1", \ 160 "Heatsink 1","Heatsink 2" \ 161 "Memory Bank A", } 162 163 #define ASMC_MB71_TEMPS { "TB0T", "TB1T", "TB2T", "TC0D", "TC0P", \ 164 "TH0P", "TN0D", "TN0P", "TN0S", "TN1D", \ 165 "TN1E", "TN1F", "TN1G", "TN1S", "Th1H", \ 166 "Ts0P", "Ts0S", NULL } 167 168 #define ASMC_MB71_TEMPNAMES { "enclosure_bottom0", "battery_1", "battery_2", "cpu_package", "cpu_proximity", \ 169 "hdd_bay", "northbridge0_diode", "northbridge0_proximity", "TN0S", "mpc_die2", \ 170 "TN1E", "TN1F", "TN1G", "TN1S", "heatsink1", \ 171 "palm_rest", "memory_proximity", } 172 173 #define ASMC_MB71_TEMPDESCS { "Enclosure Bottom 0", "Battery 1", "Battery 2", "CPU Package", "CPU Proximity", \ 174 "HDD Bay", "Northbridge Diode", "Northbridge Proximity", "TN0S", "MPC Die 2", \ 175 "TN1E", "TN1F", "TN1G", "TN1S", "Heatsink 1", \ 176 "Palm Rest", "Memory Proximity", } 177 178 #define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \ 179 "TG0H", "TG0P", "TG0T", NULL } 180 181 #define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \ 182 "heatsink2", "memory", "graphics", \ 183 "graphicssink", "unknown", } 184 185 #define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \ 186 "Heatsink 1", "Heatsink 2", \ 187 "Memory Controller", \ 188 "Graphics Chip", "Graphics Heatsink", \ 189 "Unknown", } 190 191 #define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \ 192 "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \ 193 "TTF0", "TW0P", NULL } 194 195 #define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \ 196 "heatsink3", "memory", "graphicssink", \ 197 "graphics", "cpu", "cpu2", "unknown1", \ 198 "unknown2", "wireless", } 199 200 #define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \ 201 "Main Heatsink 1", "Main Heatsink 2", \ 202 "Main Heatsink 3", \ 203 "Memory Controller", \ 204 "Graphics Chip Heatsink", \ 205 "Graphics Chip Diode", \ 206 "CPU Temperature Diode", "CPU Point 2", \ 207 "Unknown", "Unknown", \ 208 "Wireless Module", } 209 210 #define ASMC_MBP51_TEMPS { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", \ 211 "TC0F", "TC0P", "TG0D", "TG0F", "TG0H", \ 212 "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", \ 213 "TTF0", "Th2H", "Tm0P", "Ts0P", "Ts0S", \ 214 NULL } 215 216 #define ASMC_MBP51_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 217 "enclosure_bottom_2", "enclosure_bottom_3", \ 218 "cpu_diode", "cpu", \ 219 "cpu_pin", "gpu_diode", \ 220 "gpu", "gpu_heatsink", \ 221 "gpu_pin", "gpu_transistor", \ 222 "gpu_2_heatsink", "northbridge_diode", \ 223 "northbridge_pin", "unknown", \ 224 "heatsink_2", "memory_controller", \ 225 "pci_express_slot_pin", "pci_express_slot_unk" } 226 227 #define ASMC_MBP51_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 228 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 229 "CPU Diode", "CPU ???", \ 230 "CPU Pin", "GPU Diode", \ 231 "GPU ???", "GPU Heatsink", \ 232 "GPU Pin", "GPU Transistor", \ 233 "GPU 2 Heatsink", "Northbridge Diode", \ 234 "Northbridge Pin", "Unknown", \ 235 "Heatsink 2", "Memory Controller", \ 236 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 237 238 #define ASMC_MBP62_TEMPS { "TB0T", "TB1T", "TB2T", \ 239 "TC0C", "TC0D", "TC0P", \ 240 "TC1C", "TG0D", "TG0P", \ 241 "TG0T", "TMCD", "TP0P", \ 242 "TPCD", "Th1H", "Th2H", \ 243 "Tm0P", "Ts0P", "Ts0S" } 244 245 #define ASMC_MBP62_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 246 "enclosure_bottom_2", "cpu0", \ 247 "cpu_diode", "cpu_proximity", \ 248 "cpu1", "gpu_diode", \ 249 "gpu_pin", "gpu_transistor", \ 250 "TMCD", "pch_controller_proximity", \ 251 "pch_die", "heatsink1", \ 252 "heatsink2", "memory-controller", \ 253 "palmrest", "memoryproximity" } 254 255 #define ASMC_MBP62_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 256 "Enclosure Bottom 2", "CPU 0", \ 257 "CPU Diode", "CPU Proximity", \ 258 "CPU 1", "GPU Diode", \ 259 "GPU Pin", "GPU Transistor", \ 260 "TMCD", "PCH Controller Proximity", \ 261 "PCH Die", "Heat Sink 1", \ 262 "Heat Sink 2", "Memory Controller", \ 263 "Palm Rest", "Memory Proximity" } 264 265 #define ASMC_MBP55_TEMPS { "TB0T", "TB1T", \ 266 "TB2T", "TB3T", \ 267 "TC0D", "TC0P", \ 268 "TN0D", "TN0P", \ 269 "TTF0", \ 270 "Th0H", "Th1H", "ThFH", \ 271 "Ts0P", "Ts0S", \ 272 NULL } 273 274 #define ASMC_MBP55_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 275 "enclosure_bottom_2", "enclosure_bottom_3", \ 276 "cpu_diode", "cpu_pin", \ 277 "northbridge_diode", "northbridge_pin", \ 278 "unknown", \ 279 "heatsink_0", "heatsink_1", "heatsink_2", \ 280 "pci_express_slot_pin", "pci_express_slot_unk" } 281 282 #define ASMC_MBP55_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 283 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 284 "CPU Diode", "CPU Pin", \ 285 "Northbridge Diode", "Northbridge Pin", \ 286 "Unknown", \ 287 "Heatsink 0", "Heatsink 1", "Heatsink 2", \ 288 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 289 290 #define ASMC_MBP81_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 291 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 292 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 293 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 294 "Ts0S", NULL } 295 296 #define ASMC_MBP81_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 297 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 298 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 299 "TP0P", "TPCD", "wireless", "Th1H", "Ts0P", \ 300 "Ts0S" } 301 302 #define ASMC_MBP81_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 303 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 304 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 305 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 306 "Ts0S" } 307 308 #define ASMC_MBP82_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 309 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 310 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 311 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 312 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 313 "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL } 314 315 #define ASMC_MBP82_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 316 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 317 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 318 "TCTD", "graphics", "TG0P", "THSP", "TM0S", \ 319 "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \ 320 "Th2H", "memory", "Ts0P", "Ts0S" } 321 322 #define ASMC_MBP82_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 323 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 324 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 325 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 326 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 327 "Th2H", "Tm0P", "Ts0P", "Ts0S" } 328 329 #define ASMC_MBP91_TEMPS { "TA0P", "TB0T", "TB1T", "TB2T", "TC0E", \ 330 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 331 "TC4C", "TCGC", "TCSA", "TCXC", "TG0D", \ 332 "TG0P", "TG1D", "TG1F", "TG1d", "TGTC", \ 333 "TGTD", "TM0P", "TM0S", "TP0P", "TPCD", \ 334 "Th1H", "Th2H", "Ts0P", "Ts0S", "Tsqf", NULL } 335 336 #define ASMC_MBP91_TEMPNAMES { "ambient", "enclosure_bottom_1", "enclosure_bottom_2", \ 337 "enclosure_bottom_3", "cpu_die_peci_0", "cpu_die_peci_1", \ 338 "cpu_proximity", "cpu_core_1", "cpu_core_2", "cpu_core_3", \ 339 "cpu_core_4", "intel_gpu", "cpu_sys_agent", \ 340 "cpu_core_peci", "gpu_analog", \ 341 "gpu_proximity", "geforce_gpu_digital", "tg1f", \ 342 "gpu_2_die", "tgtc", "tgtd", "memory_proximity", \ 343 "mem_bank_a1", "platform_ctrl_hub", "pch_digital", \ 344 "main_heatsink_r", "main_heatsink_l", "palm_rest", \ 345 "bottom_skin", "tsqf" } 346 347 #define ASMC_MBP91_TEMPDESCS { "Ambient", "Enclosure Bottom 1", "Enclosure Bottom 2", \ 348 "Enclosure Bottom 3", "CPU Die PECI 0", "CPU Die PECI 1", \ 349 "CPU Proximity", "CPU Core 1", "CPU Core 2", \ 350 "CPU Core 3", "CPU Core 4", "Intel GPU", \ 351 "CPU System Agent Core", "CPU Core - PECI", \ 352 "GPU Die - Analog", "GPU Proximity", \ 353 "GeForce GPU Die - Digital", "TG1F", "GPU 2 Die" \ 354 "TGTC", "TGTD", "Memory Proximity", \ 355 "Memory Bank A1", "Platform Controller Hub", "PCH Die - Digital", \ 356 "Main Heatsink Right", "Main Heatsink Left", "Palm Rest", \ 357 "Bottom Skin", "Tsqf" } 358 359 #define ASMC_MBP92_TEMPS { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 360 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 361 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 362 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 363 "TPCD", NULL } 364 365 #define ASMC_MBP92_TEMPNAMES { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 366 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 367 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 368 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 369 "TPCD" } 370 371 #define ASMC_MBP92_TEMPDESCS { "Palm Rest", "Memory Proximity", "Airflow 1", \ 372 "Battery 1", "Battery 2", "Battery TS_MAX", \ 373 "CPU Core 1", "CPU Core 2", "CPU1", "CPU1", \ 374 "TC0J", "CPU 1 Proximity", "TCFC", \ 375 "PECI GPU", "PECI SA", "TCTD", "PECI CPU", \ 376 "GPU Die", "Memory Bank A1", "Memory Module A1", \ 377 "PCH Die" } 378 379 #define ASMC_MBP112_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 380 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 381 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 382 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 383 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 384 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 385 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 386 "Ts1S", NULL } 387 388 #define ASMC_MBP112_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 389 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 390 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 391 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 392 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 393 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 394 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 395 "Ts1S" } 396 397 #define ASMC_MBP112_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 398 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 399 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 400 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 401 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 402 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 403 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 404 "Ts1S" } 405 406 #define ASMC_MBP113_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 407 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 408 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 409 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 410 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 411 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 412 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 413 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 414 "Ts1S", NULL } 415 416 #define ASMC_MBP113_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 417 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 418 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 419 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 420 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 421 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 422 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 423 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 424 "Ts1S" } 425 426 #define ASMC_MBP113_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 427 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 428 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 429 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 430 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 431 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 432 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 433 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 434 "Ts1S" } 435 #define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL } 436 #define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" } 437 #define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \ 438 "Northbridge Point 2" } 439 440 #define ASMC_MM21_TEMPS { "TA0P", "TC0D", \ 441 "TC0H", "TC0P", \ 442 "TC1P", "TN0P", \ 443 "TN1P", NULL } 444 445 #define ASMC_MM21_TEMPNAMES { "ambient_air", "cpu_die", \ 446 "cpu_heatsink", "cpu_proximity1", \ 447 "cpu_proximity2", "northbridge_proximity1", \ 448 "northbridge_proximity2", } 449 450 #define ASMC_MM21_TEMPDESCS { "Ambient Air Temperature" \ 451 "CPU Die Core Temperature", \ 452 "CPU Heatsink Temperature", \ 453 "CPU Proximity 1 Temperature", \ 454 "CPU Proximity 2 Temperature", \ 455 "Northbridge Proximity 1 Temperature", \ 456 "Northbridge Proximity 2 Temperature", } 457 458 #define ASMC_MM31_TEMPS { "TC0D", "TC0H", \ 459 "TC0P", "TH0P", \ 460 "TN0D", "TN0P", \ 461 "TW0P", NULL } 462 463 #define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \ 464 "cpu0_proximity", "hdd_bay", \ 465 "northbridge_die", \ 466 "northbridge_proximity", \ 467 "wireless_proximity", } 468 469 #define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \ 470 "CPU0 Heatsink Temperature", \ 471 "CPU0 Proximity Temperature", \ 472 "HDD Bay Temperature", \ 473 "Northbridge Die Core Temperature", \ 474 "Northbridge Proximity Temperature", \ 475 "Wireless Module Proximity Temperature", } 476 477 #define ASMC_MM41_TEMPS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 478 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 479 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 480 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 481 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 482 "TW0P", "Tm0P", "Tp0C", NULL } 483 484 #define ASMC_MM41_TEMPNAMES { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 485 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 486 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 487 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 488 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 489 "TW0P", "Tm0P", "Tp0C", NULL } 490 491 #define ASMC_MM41_TEMPDESCS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 492 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 493 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 494 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 495 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 496 "TW0P", "Tm0P", "Tp0C", NULL } 497 498 #define ASMC_MM52_TEMPS { "TA0P", "TA1P", \ 499 "TC0D", "TC0P", \ 500 "TG0D", "TG1D", \ 501 "TG0P", "TG0M", \ 502 "TI0P", \ 503 "TM0S", "TMBS", \ 504 "TM0P", "TP0P", \ 505 "TPCD", "Tp0C", \ 506 "TW0P", NULL } 507 508 #define ASMC_MM52_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 509 "cpu_die", "cpu_proximity", \ 510 "gpu_diode1", "gpu_diode2", \ 511 "gpu_proximity", "gpu_integrated_switcher", \ 512 "thunderbolt_proximity", \ 513 "memory_slot1", "memory_slot2", \ 514 "memory_proximity", "pch_controller_proximity", \ 515 "pch_controller_die", "pwr_supply", \ 516 "wireless_proximity", } 517 518 #define ASMC_MM52_TEMPDESCS { "Ambient Air Proximity Temperature", \ 519 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 520 "CPU Die Temperature", "CPU Proximity Temperature", \ 521 "GPU Diode 1 Temperature" , "GPU Diode 2 Temperature", \ 522 "GPU Proximity Temperature", \ 523 "Integrated Graphics/GPU Switcher Temperature", \ 524 "Thunderbolt Proximity Temperature", \ 525 "Memory Slot 1 Temperature", \ 526 "Memory Slot 2 Temperature", \ 527 "Memory Slots Proximity Temperature", \ 528 "Platform Controller Hub Proximity Temperature", \ 529 "Platform Controller Hub Die Temperature", \ 530 "Power Supply Temperature", \ 531 "Wireless Module Proximity Temperature", } 532 533 #define ASMC_MM71_TEMPS { "TA0p", "TA1p", \ 534 "TA2p", "TC0c", \ 535 "TC0p", "TC1c", \ 536 "TCGc", "TCSc", \ 537 "TCXC", "TCXR", \ 538 "TM0p", "TPCd", \ 539 "TW0p", "Te0T", \ 540 "Tm0P", NULL } 541 542 #define ASMC_MM71_TEMPNAMES { "ambient_air1", "ambient_air2", \ 543 "ambient_air3", "cpu_core1_peci", \ 544 "cpu_proximity", "cpu_core2_peci", \ 545 "intel_gpu", "cpu_sa_core_peci", \ 546 "cpu_core", "cpu_peci_dts", \ 547 "memory_proximity", "pch_controller_die", \ 548 "wireless_proximity", "thunderbolt_diode", \ 549 "logic_board", } 550 551 #define ASMC_MM71_TEMPDESCS { "Ambient Air Temperature 1", \ 552 "Ambient Air Temperature 2", \ 553 "Ambient Air Temperature 3", \ 554 "CPU Core 1 PECI Temperature", "CPU Proximity Temperature", \ 555 "CPU Core 2 PECI Temperature", "Intel GPU Temperature", \ 556 "CPU System Agent Core PECI Temperature", \ 557 "CPU Core Temperature", "CPU PECI DTS Temperature", \ 558 "Memory Proximity Temperature", \ 559 "Platform Controller Hub Die Temperature", \ 560 "Wireless Module Proximity Temperature", \ 561 "Thunderbolt Diode Temperature", \ 562 "Logic Board temperature", } 563 564 #define ASMC_MP1_TEMPS { "TA0P", \ 565 "TCAH", "TCBH", \ 566 "TC0P", "TC0C", "TC1C", \ 567 "TC2C", "TC3C", "THTG", \ 568 "TH0P", "TH1P", \ 569 "TH2P", "TH3P", \ 570 "TM0P", "TM1P", "TM2P", \ 571 "TM8P", "TM9P", "TMAP", \ 572 "TM0S", "TM1S", "TM2P", "TM3S", \ 573 "TM8S", "TM9S", "TMAS", "TMBS", \ 574 "TN0H", "TS0C", \ 575 "Tp0C", "Tp1C", "Tv0S", "Tv1S", NULL } 576 577 #define ASMC_MP1_TEMPNAMES { "ambient", \ 578 "cpu_a_heatsink", "cpu_b_heatsink", \ 579 "cpu_a_proximity", "cpu_core0", "cpu_core1", \ 580 "cpu_core2", "cpu_core3", "THTG", \ 581 "hdd_bay0", "hdd_bay1", \ 582 "hdd_bay2", "hdd_bay3", \ 583 "memory_card_a_proximity0", \ 584 "memory_card_a_proximity1", \ 585 "memory_card_a_proximity2", \ 586 "memory_card_b_proximity0", \ 587 "memory_card_b_proximity1", \ 588 "memory_card_b_proximity2", \ 589 "memory_card_a_slot0", \ 590 "memory_card_a_slot1", \ 591 "memory_card_a_slot2", \ 592 "memory_card_a_slot3", \ 593 "memory_card_b_slot0", \ 594 "memory_card_b_slot1", \ 595 "memory_card_b_slot2", \ 596 "memory_card_b_slot3", \ 597 "mch_heatsink", "expansion_slots", \ 598 "power_supply_loc0", "power_supply_loc1", \ 599 "Tv0S", "Tv1S", } 600 601 #define ASMC_MP1_TEMPDESCS { "Ambient Air", \ 602 "CPU A Heatsink", "CPU B Heatsink", \ 603 "CPU A Proximity", \ 604 "CPU Core 1", "CPU Core 2", \ 605 "CPU Core 3", "CPU Core 4", "THTG", \ 606 "Hard Drive Bay 1", "Hard Drive Bay 2", \ 607 "Hard Drive Bay 3", "Hard Drive Bay 4", \ 608 "Memory Riser A, Proximity 1", \ 609 "Memory Riser A, Proximity 2", \ 610 "Memory Riser A, Proximity 3", \ 611 "Memory Riser B, Proximity 1", \ 612 "Memory Riser B, Proximity 2", \ 613 "Memory Riser B, Proximity 3", \ 614 "Memory Riser A, Slot 1", \ 615 "Memory Riser A, Slot 2", \ 616 "Memory Riser A, Slot 3", \ 617 "Memory Riser A, Slot 4", \ 618 "Memory Riser B, Slot 1", \ 619 "Memory Riser B, Slot 2", \ 620 "Memory Riser B, Slot 3", \ 621 "Memory Riser B, Slot 4", \ 622 "MCH Heatsink", "Expansion Slots", \ 623 "Power Supply, Location 1", \ 624 "Power Supply, Location 2", \ 625 "Tv0S", "Tv1S", } 626 627 #define ASMC_MP2_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 628 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 629 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 630 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 631 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 632 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 633 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \ 634 NULL } 635 636 #define ASMC_MP2_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 637 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 638 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 639 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 640 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 641 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 642 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 643 644 #define ASMC_MP2_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 645 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 646 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 647 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 648 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 649 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 650 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 651 652 #define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 653 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 654 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 655 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 656 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 657 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 658 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 659 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 660 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 661 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 662 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 663 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 664 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 665 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 666 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \ 667 NULL } 668 669 #define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \ 670 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 671 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 672 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 673 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 674 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 675 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 676 "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \ 677 "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \ 678 "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \ 679 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 680 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 681 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 682 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 683 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 684 685 #define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 686 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 687 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 688 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 689 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 690 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 691 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 692 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 693 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 694 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 695 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 696 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 697 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 698 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 699 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 700 701 #define ASMC_MP6_TEMPS { "TA0P", "TA1P", "TC0P", "TG0D", "TG0P", \ 702 "TG1D", "TG1P", "TM0P", "TM1P", NULL } 703 704 #define ASMC_MP6_TEMPNAMES { "ambient_air_1", "ambient_air_2", \ 705 "cpu_proximity", "gpu_diode_1", \ 706 "gpu_proximity_1", "gpu_diode_2", \ 707 "gpu_proximity_2", "mem_proximity_1", \ 708 "mem_proximity_2" } 709 710 #define ASMC_MP6_TEMPDESCS { "Ambient Air 1", "Ambient Air 2", \ 711 "CPU Proximity", "GPU Diode 1", \ 712 "GPU Proximity 1", "GPU Diode 2", \ 713 "GPU Proximity 2", "Memory Bank A", \ 714 "Memory Bank B" } 715 716 #define ASMC_MBA_TEMPS { "TB0T", NULL } 717 #define ASMC_MBA_TEMPNAMES { "enclosure" } 718 #define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" } 719 720 #define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \ 721 "TC0D", "TC0E", "TC0P", NULL } 722 723 #define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \ 724 "TC0D", "TC0E", "TC0P" } 725 726 #define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \ 727 "TC0D", "TC0E", "TC0P" } 728 729 #define ASMC_MBA4_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 730 "TC0D", "TC0E", "TC0F", "TC0P", \ 731 "TC1C", "TC2C", "TCGC", "TCSA", \ 732 "TH0F", "TH0J", "TH0O", "TH0o", \ 733 "TM0P", "TPCD", "Ta0P", "Th1H", \ 734 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 735 NULL } 736 737 #define ASMC_MBA4_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TC0C", \ 738 "TC0D", "TC0E", "TC0F", "TC0P", \ 739 "TC1C", "TC2C", "TCGC", "TCSA", \ 740 "TH0F", "TH0J", "TH0O", "TH0o", \ 741 "TM0P", "TPCD", "Ta0P", "Th1H", \ 742 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 743 NULL } 744 745 #define ASMC_MBA4_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TC0C", \ 746 "TC0D", "TC0E", "TC0F", "TC0P", \ 747 "TC1C", "TC2C", "TCGC", "TCSA", \ 748 "TH0F", "TH0J", "TH0O", "TH0o", \ 749 "TM0P", "TPCD", "Ta0P", "Th1H", \ 750 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 751 NULL } 752 753 #define ASMC_MBA5_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 754 "TC0D", "TC0E", "TC0F", "TC0P", \ 755 "TC1C", "TC2C", "TCGC", "TCSA", \ 756 "TCXC", "THSP", "TM0P", "TPCD", \ 757 "Ta0P", "Th1H", "Tm0P", "Tm1P", \ 758 "Ts0P", "Ts0S", NULL } 759 760 #define ASMC_MBA5_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", "TC0C", \ 761 "cpudiode", "cputemp1", "cputemp2", "cpuproximity", \ 762 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 763 "TCXC", "THSP", "memorybank", "pchdie", \ 764 "Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \ 765 "palmrest", "memoryproximity" } 766 767 #define ASMC_MBA5_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\ 768 "CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 769 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 770 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 771 "Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \ 772 "Palm Rest", "Memory Proximity" } 773 774 /* 775 * TODO: validate the temp zones for MBA 6.x ! 776 */ 777 #define ASMC_MBA6_TEMPS { "TB0T", "TB1T", "TB2T", \ 778 "TC0E", "TC0F", "TC0P", \ 779 "TC1C", "TC2C", "TCGC", "TCSA", \ 780 "TCXC", "THSP", "TM0P", "TPCD", \ 781 "Ta0P", "Th1H", "Tm0P", \ 782 "Ts0P", "Ts0S", NULL } 783 784 #define ASMC_MBA6_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \ 785 "cputemp1", "cputemp2", "cpuproximity", \ 786 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 787 "TCXC", "THSP", "memorybank", "pchdie", \ 788 "Ta0P", "heatpipe", "mainboardproximity1", \ 789 "palmrest", "memoryproximity" } 790 791 #define ASMC_MBA6_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \ 792 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 793 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 794 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 795 "Ta0P", "Heatpipe", "Mainboard Proximity 1", \ 796 "Palm Rest", "Memory Proximity" } 797 798 799 #define ASMC_MBA7_TEMPS { "TB0T", "TB1T", "TB2T", \ 800 "TC0E", "TC0F", "TC0P", \ 801 "TC1C", "TC2C", \ 802 "TCGC", "TCSA", "TCXC", \ 803 "THSP", "TM0P", "TPCD", \ 804 "TW0P" "Ta0P", "Th1H", \ 805 "Tm0P", "Ts0P", "Ts0S", NULL } 806 807 #define ASMC_MBA7_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \ 808 "cputemp1", "cputemp2", "cpuproximity", \ 809 "cpucore1", "cpucore2", \ 810 "pecigpu", "pecisa", "pecicpu", \ 811 "thunderboltproximity", "memorybank", "pchdie", \ 812 "wirelessproximity", "airflowproximity", "heatpipe", \ 813 "mainboardproximity", "palmrest", "memoryproximity" } 814 815 #define ASMC_MBA7_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \ 816 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 817 "CPU Core 1", "CPU Core 2", \ 818 "PECI GPU", "PECI SA", "PECI CPU", \ 819 "Thunderbolt Proximity", "Memory Bank A", "PCH Die", \ 820 "Wireless Proximity", "Airflow Proxmity", "Heatpipe", \ 821 "Mainboard Proximity", "Palm Rest", "Memory Proximity" } 822